m68k: bvme6000: Convert to clocksource API
Add a platform clocksource by adapting the existing arch_gettimeoffset implementation. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
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@ -18,6 +18,7 @@
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/tty.h>
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#include <linux/clocksource.h>
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#include <linux/console.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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@ -147,6 +148,21 @@ irqreturn_t bvme6000_abort_int (int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static u64 bvme6000_read_clk(struct clocksource *cs);
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static struct clocksource bvme6000_clk = {
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.name = "rtc",
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.rating = 250,
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.read = bvme6000_read_clk,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static u32 clk_total, clk_offset;
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#define RTC_TIMER_CLOCK_FREQ 8000000
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#define RTC_TIMER_CYCLES (RTC_TIMER_CLOCK_FREQ / HZ)
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#define RTC_TIMER_COUNT ((RTC_TIMER_CYCLES / 2) - 1)
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static irqreturn_t bvme6000_timer_int (int irq, void *dev_id)
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{
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@ -158,6 +174,8 @@ static irqreturn_t bvme6000_timer_int (int irq, void *dev_id)
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local_irq_save(flags);
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msr = rtc->msr & 0xc0;
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rtc->msr = msr | 0x20; /* Ack the interrupt */
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clk_total += RTC_TIMER_CYCLES;
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clk_offset = 0;
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timer_routine(0, NULL);
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local_irq_restore(flags);
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@ -180,13 +198,13 @@ void bvme6000_sched_init (irq_handler_t timer_routine)
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rtc->msr = 0; /* Ensure timer registers accessible */
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if (request_irq(BVME_IRQ_RTC, bvme6000_timer_int, 0, "timer",
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if (request_irq(BVME_IRQ_RTC, bvme6000_timer_int, IRQF_TIMER, "timer",
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timer_routine))
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panic ("Couldn't register timer int");
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rtc->t1cr_omr = 0x04; /* Mode 2, ext clk */
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rtc->t1msb = 39999 >> 8;
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rtc->t1lsb = 39999 & 0xff;
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rtc->t1msb = RTC_TIMER_COUNT >> 8;
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rtc->t1lsb = RTC_TIMER_COUNT & 0xff;
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rtc->irr_icr1 &= 0xef; /* Route timer 1 to INTR pin */
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rtc->msr = 0x40; /* Access int.cntrl, etc */
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rtc->pfr_icr0 = 0x80; /* Just timer 1 ints enabled */
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@ -198,14 +216,14 @@ void bvme6000_sched_init (irq_handler_t timer_routine)
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rtc->msr = msr;
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clocksource_register_hz(&bvme6000_clk, RTC_TIMER_CLOCK_FREQ);
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if (request_irq(BVME_IRQ_ABORT, bvme6000_abort_int, 0,
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"abort", bvme6000_abort_int))
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panic ("Couldn't register abort int");
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}
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/* This is always executed with interrupts disabled. */
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/*
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* NOTE: Don't accept any readings within 5us of rollover, as
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* the T1INT bit may be a little slow getting set. There is also
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@ -213,14 +231,18 @@ void bvme6000_sched_init (irq_handler_t timer_routine)
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* results...
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*/
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u32 bvme6000_gettimeoffset(void)
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static u64 bvme6000_read_clk(struct clocksource *cs)
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{
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unsigned long flags;
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volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
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volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE;
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unsigned char msr = rtc->msr & 0xc0;
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unsigned char msr, msb;
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unsigned char t1int, t1op;
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u32 v = 800000, ov;
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local_irq_save(flags);
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msr = rtc->msr & 0xc0;
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rtc->msr = 0; /* Ensure timer registers accessible */
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do {
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@ -228,22 +250,25 @@ u32 bvme6000_gettimeoffset(void)
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t1int = rtc->msr & 0x20;
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t1op = pit->pcdr & 0x04;
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rtc->t1cr_omr |= 0x40; /* Latch timer1 */
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v = rtc->t1msb << 8; /* Read timer1 */
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v |= rtc->t1lsb; /* Read timer1 */
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msb = rtc->t1msb; /* Read timer1 */
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v = (msb << 8) | rtc->t1lsb; /* Read timer1 */
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} while (t1int != (rtc->msr & 0x20) ||
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t1op != (pit->pcdr & 0x04) ||
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abs(ov-v) > 80 ||
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v > 39960);
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v > RTC_TIMER_COUNT - (RTC_TIMER_COUNT / 100));
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v = 39999 - v;
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v = RTC_TIMER_COUNT - v;
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if (!t1op) /* If in second half cycle.. */
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v += 40000;
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v /= 8; /* Convert ticks to microseconds */
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if (t1int)
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v += 10000; /* Int pending, + 10ms */
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v += RTC_TIMER_CYCLES / 2;
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if (msb > 0 && t1int)
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clk_offset = RTC_TIMER_CYCLES;
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rtc->msr = msr;
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return v * 1000;
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v += clk_offset + clk_total;
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local_irq_restore(flags);
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return v;
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}
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/*
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