powerpc: Avoid link stack corruption in misc asm functions
bl;mflr is used at several places to get code position.
Use bcl 20,31,+4 instead of bl in order to preserve link stack.
See commit c974809a26
("powerpc/vdso: Avoid link stack corruption
in __get_datapage()") for details.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/c6eabb4fb6c156f75d56dcbcc6f243e5ac0fba42.1629791763.git.christophe.leroy@csgroup.eu
This commit is contained in:
Родитель
f5007dbf4d
Коммит
33e1402435
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@ -29,7 +29,7 @@ _GLOBAL(reloc_offset)
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li r3, 0
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li r3, 0
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_GLOBAL(add_reloc_offset)
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_GLOBAL(add_reloc_offset)
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mflr r0
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mflr r0
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bl 1f
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bcl 20,31,$+4
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1: mflr r5
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1: mflr r5
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PPC_LL r4,(2f-1b)(r5)
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PPC_LL r4,(2f-1b)(r5)
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subf r5,r4,r5
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subf r5,r4,r5
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@ -67,7 +67,7 @@ _GLOBAL(reloc_got2)
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srwi. r8,r8,2
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srwi. r8,r8,2
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beqlr
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beqlr
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mtctr r8
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mtctr r8
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bl 1f
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bcl 20,31,$+4
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1: mflr r0
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1: mflr r0
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lis r4,1b@ha
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lis r4,1b@ha
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addi r4,r4,1b@l
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addi r4,r4,1b@l
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@ -255,7 +255,7 @@ _GLOBAL(scom970_write)
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* Physical (hardware) cpu id should be in r3.
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* Physical (hardware) cpu id should be in r3.
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*/
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*/
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_GLOBAL(kexec_wait)
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_GLOBAL(kexec_wait)
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bl 1f
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bcl 20,31,$+4
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1: mflr r5
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1: mflr r5
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addi r5,r5,kexec_flag-1b
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addi r5,r5,kexec_flag-1b
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@ -30,7 +30,7 @@ R_PPC_RELATIVE = 22
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_GLOBAL(relocate)
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_GLOBAL(relocate)
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mflr r0 /* Save our LR */
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mflr r0 /* Save our LR */
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bl 0f /* Find our current runtime address */
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bcl 20,31,$+4 /* Find our current runtime address */
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0: mflr r12 /* Make it accessible */
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0: mflr r12 /* Make it accessible */
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mtlr r0
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mtlr r0
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@ -93,7 +93,7 @@ wmmucr:
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* Invalidate all the TLB entries except the current entry
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* Invalidate all the TLB entries except the current entry
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* where we are running from
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* where we are running from
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*/
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*/
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bl 0f /* Find our address */
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bcl 20,31,$+4 /* Find our address */
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0: mflr r5 /* Make it accessible */
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0: mflr r5 /* Make it accessible */
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tlbsx r23,0,r5 /* Find entry we are in */
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tlbsx r23,0,r5 /* Find entry we are in */
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li r4,0 /* Start at TLB entry 0 */
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li r4,0 /* Start at TLB entry 0 */
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@ -158,7 +158,7 @@ write_out:
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/* Switch to other address space in MSR */
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/* Switch to other address space in MSR */
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insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
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insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
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bl 1f
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bcl 20,31,$+4
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1: mflr r8
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1: mflr r8
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addi r8, r8, (2f-1b) /* Find the target offset */
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addi r8, r8, (2f-1b) /* Find the target offset */
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@ -202,7 +202,7 @@ next_tlb:
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li r9,0
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li r9,0
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insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
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insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
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bl 1f
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bcl 20,31,$+4
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1: mflr r8
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1: mflr r8
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and r8, r8, r11 /* Get our offset within page */
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and r8, r8, r11 /* Get our offset within page */
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addi r8, r8, (2f-1b)
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addi r8, r8, (2f-1b)
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@ -240,7 +240,7 @@ setup_map_47x:
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sync
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sync
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/* Find the entry we are running from */
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/* Find the entry we are running from */
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bl 2f
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bcl 20,31,$+4
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2: mflr r23
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2: mflr r23
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tlbsx r23, 0, r23
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tlbsx r23, 0, r23
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tlbre r24, r23, 0 /* TLB Word 0 */
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tlbre r24, r23, 0 /* TLB Word 0 */
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@ -296,7 +296,7 @@ clear_utlb_entry:
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/* Update the msr to the new TS */
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/* Update the msr to the new TS */
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insrwi r5, r7, 1, 26
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insrwi r5, r7, 1, 26
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bl 1f
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bcl 20,31,$+4
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1: mflr r6
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1: mflr r6
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addi r6, r6, (2f-1b)
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addi r6, r6, (2f-1b)
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@ -355,7 +355,7 @@ write_utlb:
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/* Defaults to 256M */
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/* Defaults to 256M */
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lis r10, 0x1000
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lis r10, 0x1000
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bl 1f
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bcl 20,31,$+4
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1: mflr r4
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1: mflr r4
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addi r4, r4, (2f-1b) /* virtual address of 2f */
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addi r4, r4, (2f-1b) /* virtual address of 2f */
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