PCI: Decode PCIe 64 GT/s link speed
PCIe r6.0, sec 7.5.3.18, defines a new 64.0 GT/s bit in the Supported Link Speeds Vector of Link Capabilities 2. This patch does not affect the speed of the link, which should be negotiated automatically by the hardware; it only adds decoding when showing the speed to the user. Decode this new speed. Previously, reading the speed of a link operating at this speed showed "Unknown speed" instead of "64.0 GT/s". Link: https://lore.kernel.org/r/aaaab33fe18975e123a84aebce2adb85f44e2bbe.1605739760.git.gustavo.pimentel@synopsys.com Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
This commit is contained in:
Gustavo Pimentel
Bjorn Helgaas
Родитель
f8394f232b
Коммит
341917490d
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@ -294,7 +294,8 @@ void pci_bus_put(struct pci_bus *bus);
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/* PCIe link information from Link Capabilities 2 */
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#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
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((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
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((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
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(lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
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@ -303,7 +304,8 @@ void pci_bus_put(struct pci_bus *bus);
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/* PCIe speed to Mb/s reduced by encoding overhead */
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#define PCIE_SPEED2MBS_ENC(speed) \
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((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
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((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
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(speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
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(speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
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(speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
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(speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
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@ -677,7 +677,7 @@ const unsigned char pcie_link_speed[] = {
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PCIE_SPEED_8_0GT, /* 3 */
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PCIE_SPEED_16_0GT, /* 4 */
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PCIE_SPEED_32_0GT, /* 5 */
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PCI_SPEED_UNKNOWN, /* 6 */
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PCIE_SPEED_64_0GT, /* 6 */
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PCI_SPEED_UNKNOWN, /* 7 */
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PCI_SPEED_UNKNOWN, /* 8 */
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PCI_SPEED_UNKNOWN, /* 9 */
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@ -719,6 +719,7 @@ const char *pci_speed_string(enum pci_bus_speed speed)
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"8.0 GT/s PCIe", /* 0x16 */
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"16.0 GT/s PCIe", /* 0x17 */
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"32.0 GT/s PCIe", /* 0x18 */
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"64.0 GT/s PCIe", /* 0x19 */
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};
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if (speed < ARRAY_SIZE(speed_strings))
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@ -281,6 +281,7 @@ enum pci_bus_speed {
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PCIE_SPEED_8_0GT = 0x16,
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PCIE_SPEED_16_0GT = 0x17,
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PCIE_SPEED_32_0GT = 0x18,
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PCIE_SPEED_64_0GT = 0x19,
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PCI_SPEED_UNKNOWN = 0xff,
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};
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@ -531,6 +531,7 @@
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#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
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#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
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#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
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#define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
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#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
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#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
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@ -562,6 +563,7 @@
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#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
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#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
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#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */
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#define PCI_EXP_LNKSTA_CLS_64_0GB 0x0006 /* Current Link Speed 64.0GT/s */
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#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
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#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */
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#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */
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@ -670,6 +672,7 @@
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#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */
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#define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040 /* Supported Speed 64GT/s */
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#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
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#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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#define PCI_EXP_LNKCTL2_TLS 0x000f
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@ -678,6 +681,7 @@
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#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
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#define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */
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#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
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#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
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#define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
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