OMAP: Improve register access in L3 Error handler.
* Changed the way of accessing L3 target registers from standard base rather than relative to STDERRLOG_MAIN. * Use ffs() to find error source from the L3_FLAGMUX_REGERRn register. * Remove extra l3_base[] entry. * Modified L3 custom error message. Signed-off-by: Todd Poynor <toddpoynor@google.com> Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
This commit is contained in:
Todd Poynor
Santosh Shilimkar
Родитель
b6fd41e29d
Коммит
342fd14429
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@ -56,10 +56,9 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
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{
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struct omap4_l3 *l3 = _l3;
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int inttype, i, j;
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int inttype, i;
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int err_src = 0;
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u32 std_err_main_addr, std_err_main, err_reg;
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u32 base, slave_addr, clear;
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u32 std_err_main, err_reg, clear, base, l3_targ_base;
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char *source_name;
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/* Get the Type of interrupt */
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@ -71,42 +70,43 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
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* to determine the source
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*/
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base = (u32)l3->l3_base[i];
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err_reg = readl(base + l3_flagmux[i] + (inttype << 3));
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err_reg = readl(base + l3_flagmux[i] +
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+ L3_FLAGMUX_REGERR0 + (inttype << 3));
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/* Get the corresponding error and analyse */
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if (err_reg) {
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/* Identify the source from control status register */
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for (j = 0; !(err_reg & (1 << j)); j++)
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;
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err_src = __ffs(err_reg);
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err_src = j;
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/* Read the stderrlog_main_source from clk domain */
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std_err_main_addr = base + *(l3_targ[i] + err_src);
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std_err_main = readl(std_err_main_addr);
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l3_targ_base = base + *(l3_targ[i] + err_src);
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std_err_main = readl(l3_targ_base +
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L3_TARG_STDERRLOG_MAIN);
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switch (std_err_main & CUSTOM_ERROR) {
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case STANDARD_ERROR:
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source_name =
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l3_targ_stderrlog_main_name[i][err_src];
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slave_addr = std_err_main_addr +
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L3_SLAVE_ADDRESS_OFFSET;
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l3_targ_inst_name[i][err_src];
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WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
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source_name, readl(slave_addr));
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source_name,
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readl(l3_targ_base +
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L3_TARG_STDERRLOG_SLVOFSLSB));
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/* clear the std error log*/
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clear = std_err_main | CLEAR_STDERR_LOG;
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writel(clear, std_err_main_addr);
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writel(clear, l3_targ_base +
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L3_TARG_STDERRLOG_MAIN);
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break;
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case CUSTOM_ERROR:
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source_name =
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l3_targ_stderrlog_main_name[i][err_src];
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l3_targ_inst_name[i][err_src];
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WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
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source_name);
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WARN(true, "L3 custom error: SOURCE:%s\n",
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source_name);
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/* clear the std error log*/
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clear = std_err_main | CLEAR_STDERR_LOG;
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writel(clear, std_err_main_addr);
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writel(clear, l3_targ_base +
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L3_TARG_STDERRLOG_MAIN);
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break;
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default:
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@ -123,9 +123,8 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
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static int __init omap4_l3_probe(struct platform_device *pdev)
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{
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static struct omap4_l3 *l3;
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struct resource *res;
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int ret;
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int irq;
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struct resource *res;
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int ret, irq;
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l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
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if (!l3)
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@ -23,63 +23,60 @@
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#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
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#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
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/*
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* L3 register offsets
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*/
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#define L3_MODULES 3
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#define CLEAR_STDERR_LOG (1 << 31)
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#define CUSTOM_ERROR 0x2
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#define STANDARD_ERROR 0x0
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#define INBAND_ERROR 0x0
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#define EMIF_KERRLOG_OFFSET 0x10
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#define L3_SLAVE_ADDRESS_OFFSET 0x14
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#define LOGICAL_ADDR_ERRORLOG 0x4
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#define L3_APPLICATION_ERROR 0x0
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#define L3_DEBUG_ERROR 0x1
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/* L3 TARG register offsets */
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#define L3_TARG_STDERRLOG_MAIN 0x48
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#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
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#define L3_FLAGMUX_REGERR0 0xc
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u32 l3_flagmux[L3_MODULES] = {
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0x50C,
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0x100C,
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0X020C
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0x500,
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0x1000,
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0X0200
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};
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/*
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* L3 Target standard Error register offsets
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*/
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u32 l3_targ_stderrlog_main_clk1[] = {
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0x148, /* DMM1 */
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0x248, /* DMM2 */
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0x348, /* ABE */
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0x448, /* L4CFG */
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0x648 /* CLK2 PWR DISC */
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/* L3 Target standard Error register offsets */
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u32 l3_targ_inst_clk1[] = {
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0x100, /* DMM1 */
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0x200, /* DMM2 */
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0x300, /* ABE */
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0x400, /* L4CFG */
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0x600 /* CLK2 PWR DISC */
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};
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u32 l3_targ_stderrlog_main_clk2[] = {
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0x548, /* CORTEX M3 */
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0x348, /* DSS */
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0x148, /* GPMC */
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0x448, /* ISS */
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0x748, /* IVAHD */
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0xD48, /* missing in TRM corresponds to AES1*/
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0x948, /* L4 PER0*/
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0x248, /* OCMRAM */
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0x148, /* missing in TRM corresponds to GPMC sERROR*/
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0x648, /* SGX */
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0x848, /* SL2 */
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0x1648, /* C2C */
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0x1148, /* missing in TRM corresponds PWR DISC CLK1*/
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0xF48, /* missing in TRM corrsponds to SHA1*/
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0xE48, /* missing in TRM corresponds to AES2*/
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0xC48, /* L4 PER3 */
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0xA48, /* L4 PER1*/
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0xB48 /* L4 PER2*/
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u32 l3_targ_inst_clk2[] = {
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0x500, /* CORTEX M3 */
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0x300, /* DSS */
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0x100, /* GPMC */
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0x400, /* ISS */
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0x700, /* IVAHD */
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0xD00, /* missing in TRM corresponds to AES1*/
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0x900, /* L4 PER0*/
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0x200, /* OCMRAM */
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0x100, /* missing in TRM corresponds to GPMC sERROR*/
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0x600, /* SGX */
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0x800, /* SL2 */
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0x1600, /* C2C */
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0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
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0xF00, /* missing in TRM corrsponds to SHA1*/
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0xE00, /* missing in TRM corresponds to AES2*/
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0xC00, /* L4 PER3 */
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0xA00, /* L4 PER1*/
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0xB00 /* L4 PER2*/
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};
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u32 l3_targ_stderrlog_main_clk3[] = {
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0x0148 /* EMUSS */
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u32 l3_targ_inst_clk3[] = {
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0x0100 /* EMUSS */
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};
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char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
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char *l3_targ_inst_name[L3_MODULES][18] = {
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{
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"DMM1",
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"DMM2",
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@ -113,9 +110,9 @@ char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
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};
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u32 *l3_targ[L3_MODULES] = {
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l3_targ_stderrlog_main_clk1,
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l3_targ_stderrlog_main_clk2,
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l3_targ_stderrlog_main_clk3,
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l3_targ_inst_clk1,
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l3_targ_inst_clk2,
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l3_targ_inst_clk3,
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};
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struct omap4_l3 {
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@ -123,10 +120,9 @@ struct omap4_l3 {
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struct clk *ick;
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/* memory base */
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void __iomem *l3_base[4];
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void __iomem *l3_base[L3_MODULES];
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int debug_irq;
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int app_irq;
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};
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#endif
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@ -191,10 +191,9 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
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}
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/* identify the error source */
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for (err_source = 0; !(status & (1 << err_source)); err_source++)
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;
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err_source = __ffs(status);
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base = l3->rt + *(omap3_l3_bases[int_type] + err_source);
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base = l3->rt + omap3_l3_bases[int_type][err_source];
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error = omap3_l3_readll(base, L3_ERROR_LOG);
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if (error) {
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error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
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@ -40,7 +40,7 @@
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#define L3_SI_CONTROL 0x020
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#define L3_SI_FLAG_STATUS_0 0x510
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const u64 shift = 1;
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static const u64 shift = 1;
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#define L3_STATUS_0_MPUIA_BRST (shift << 0)
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#define L3_STATUS_0_MPUIA_RSP (shift << 1)
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