Merge branch 'x86/amd-nb' into x86/urgent
Merge reason: This is one followup commit that was not in x86/mm - merge it via the urgent path Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar
Коммит
344c21c322
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@ -9,15 +9,17 @@ struct amd_nb_bus_dev_range {
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u8 dev_limit;
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};
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extern struct pci_device_id amd_nb_misc_ids[];
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extern const struct pci_device_id amd_nb_misc_ids[];
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extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
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struct bootnode;
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extern int early_is_amd_nb(u32 value);
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extern bool early_is_amd_nb(u32 value);
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extern int amd_cache_northbridges(void);
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extern void amd_flush_garts(void);
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extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn);
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extern int amd_scan_nodes(void);
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extern int amd_get_subcaches(int);
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extern int amd_set_subcaches(int, int);
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#ifdef CONFIG_NUMA_EMU
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extern void amd_fake_nodes(const struct bootnode *nodes, int nr_nodes);
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@ -26,6 +28,7 @@ extern void amd_get_nodes(struct bootnode *nodes);
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struct amd_northbridge {
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struct pci_dev *misc;
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struct pci_dev *link;
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};
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struct amd_northbridge_info {
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@ -35,17 +38,18 @@ struct amd_northbridge_info {
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};
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extern struct amd_northbridge_info amd_northbridges;
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#define AMD_NB_GART 0x1
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#define AMD_NB_L3_INDEX_DISABLE 0x2
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#define AMD_NB_GART BIT(0)
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#define AMD_NB_L3_INDEX_DISABLE BIT(1)
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#define AMD_NB_L3_PARTITIONING BIT(2)
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#ifdef CONFIG_AMD_NB
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static inline int amd_nb_num(void)
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static inline u16 amd_nb_num(void)
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{
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return amd_northbridges.num;
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}
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static inline int amd_nb_has_feature(int feature)
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static inline bool amd_nb_has_feature(unsigned feature)
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{
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return ((amd_northbridges.flags & feature) == feature);
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}
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@ -12,7 +12,7 @@
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static u32 *flush_words;
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struct pci_device_id amd_nb_misc_ids[] = {
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const struct pci_device_id amd_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) },
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@ -20,6 +20,11 @@ struct pci_device_id amd_nb_misc_ids[] = {
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};
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EXPORT_SYMBOL(amd_nb_misc_ids);
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static struct pci_device_id amd_nb_link_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_LINK) },
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{}
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};
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const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
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{ 0x00, 0x18, 0x20 },
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{ 0xff, 0x00, 0x20 },
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@ -31,7 +36,7 @@ struct amd_northbridge_info amd_northbridges;
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EXPORT_SYMBOL(amd_northbridges);
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static struct pci_dev *next_northbridge(struct pci_dev *dev,
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struct pci_device_id *ids)
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const struct pci_device_id *ids)
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{
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do {
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dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
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@ -43,9 +48,9 @@ static struct pci_dev *next_northbridge(struct pci_dev *dev,
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int amd_cache_northbridges(void)
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{
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int i = 0;
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u16 i = 0;
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struct amd_northbridge *nb;
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struct pci_dev *misc;
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struct pci_dev *misc, *link;
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if (amd_nb_num())
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return 0;
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@ -64,10 +69,12 @@ int amd_cache_northbridges(void)
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amd_northbridges.nb = nb;
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amd_northbridges.num = i;
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misc = NULL;
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link = misc = NULL;
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for (i = 0; i != amd_nb_num(); i++) {
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node_to_amd_nb(i)->misc = misc =
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next_northbridge(misc, amd_nb_misc_ids);
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node_to_amd_nb(i)->link = link =
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next_northbridge(link, amd_nb_link_ids);
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}
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/* some CPU families (e.g. family 0x11) do not support GART */
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@ -85,26 +92,95 @@ int amd_cache_northbridges(void)
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boot_cpu_data.x86_mask >= 0x1))
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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if (boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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/* L3 cache partitioning is supported on family 0x15 */
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if (boot_cpu_data.x86 == 0x15)
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amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
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return 0;
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}
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EXPORT_SYMBOL_GPL(amd_cache_northbridges);
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/* Ignores subdevice/subvendor but as far as I can figure out
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they're useless anyways */
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int __init early_is_amd_nb(u32 device)
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/*
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* Ignores subdevice/subvendor but as far as I can figure out
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* they're useless anyways
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*/
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bool __init early_is_amd_nb(u32 device)
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{
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struct pci_device_id *id;
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const struct pci_device_id *id;
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u32 vendor = device & 0xffff;
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device >>= 16;
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for (id = amd_nb_misc_ids; id->vendor; id++)
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if (vendor == id->vendor && device == id->device)
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return 1;
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return true;
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return false;
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}
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int amd_get_subcaches(int cpu)
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{
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struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
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unsigned int mask;
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int cuid = 0;
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if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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return 0;
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pci_read_config_dword(link, 0x1d4, &mask);
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#ifdef CONFIG_SMP
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cuid = cpu_data(cpu).compute_unit_id;
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#endif
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return (mask >> (4 * cuid)) & 0xf;
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}
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int amd_set_subcaches(int cpu, int mask)
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{
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static unsigned int reset, ban;
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struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
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unsigned int reg;
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int cuid = 0;
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if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
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return -EINVAL;
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/* if necessary, collect reset state of L3 partitioning and BAN mode */
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if (reset == 0) {
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pci_read_config_dword(nb->link, 0x1d4, &reset);
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pci_read_config_dword(nb->misc, 0x1b8, &ban);
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ban &= 0x180000;
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}
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/* deactivate BAN mode if any subcaches are to be disabled */
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if (mask != 0xf) {
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pci_read_config_dword(nb->misc, 0x1b8, ®);
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pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
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}
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#ifdef CONFIG_SMP
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cuid = cpu_data(cpu).compute_unit_id;
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#endif
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mask <<= 4 * cuid;
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mask |= (0xf ^ (1 << cuid)) << 26;
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pci_write_config_dword(nb->link, 0x1d4, mask);
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/* reset BAN mode if L3 partitioning returned to reset state */
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pci_read_config_dword(nb->link, 0x1d4, ®);
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if (reg == reset) {
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pci_read_config_dword(nb->misc, 0x1b8, ®);
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reg &= ~0x180000;
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pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
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}
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return 0;
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}
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int amd_cache_gart(void)
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static int amd_cache_gart(void)
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{
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int i;
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u16 i;
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if (!amd_nb_has_feature(AMD_NB_GART))
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return 0;
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@ -261,7 +261,7 @@ static int __cpuinit nearby_node(int apicid)
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#ifdef CONFIG_X86_HT
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static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
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{
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u32 nodes;
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u32 nodes, cores_per_cu = 1;
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u8 node_id;
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int cpu = smp_processor_id();
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@ -276,6 +276,7 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
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/* get compute unit information */
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smp_num_siblings = ((ebx >> 8) & 3) + 1;
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c->compute_unit_id = ebx & 0xff;
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cores_per_cu += ((ebx >> 8) & 3);
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} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
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u64 value;
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@ -288,15 +289,18 @@ static void __cpuinit amd_get_topology(struct cpuinfo_x86 *c)
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/* fixup multi-node processor information */
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if (nodes > 1) {
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u32 cores_per_node;
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u32 cus_per_node;
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set_cpu_cap(c, X86_FEATURE_AMD_DCM);
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cores_per_node = c->x86_max_cores / nodes;
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cus_per_node = cores_per_node / cores_per_cu;
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/* store NodeID, use llc_shared_map to store sibling info */
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per_cpu(cpu_llc_id, cpu) = node_id;
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/* core id to be in range from 0 to (cores_per_node - 1) */
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c->cpu_core_id = c->cpu_core_id % cores_per_node;
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/* core id has to be in the [0 .. cores_per_node - 1] range */
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c->cpu_core_id %= cores_per_node;
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c->compute_unit_id %= cus_per_node;
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}
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}
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#endif
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@ -304,8 +304,9 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
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struct _cache_attr {
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struct attribute attr;
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ssize_t (*show)(struct _cpuid4_info *, char *);
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ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
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ssize_t (*show)(struct _cpuid4_info *, char *, unsigned int);
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ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count,
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unsigned int);
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};
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#ifdef CONFIG_AMD_NB
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@ -400,7 +401,8 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
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#define SHOW_CACHE_DISABLE(slot) \
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static ssize_t \
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show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf) \
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show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf, \
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unsigned int cpu) \
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{ \
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return show_cache_disable(this_leaf, buf, slot); \
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}
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@ -512,7 +514,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
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#define STORE_CACHE_DISABLE(slot) \
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static ssize_t \
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store_cache_disable_##slot(struct _cpuid4_info *this_leaf, \
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const char *buf, size_t count) \
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const char *buf, size_t count, \
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unsigned int cpu) \
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{ \
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return store_cache_disable(this_leaf, buf, count, slot); \
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}
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@ -524,6 +527,39 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
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static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
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show_cache_disable_1, store_cache_disable_1);
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static ssize_t
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show_subcaches(struct _cpuid4_info *this_leaf, char *buf, unsigned int cpu)
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{
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if (!this_leaf->l3 || !amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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return -EINVAL;
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return sprintf(buf, "%x\n", amd_get_subcaches(cpu));
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}
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static ssize_t
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store_subcaches(struct _cpuid4_info *this_leaf, const char *buf, size_t count,
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unsigned int cpu)
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{
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unsigned long val;
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if (!capable(CAP_SYS_ADMIN))
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return -EPERM;
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if (!this_leaf->l3 || !amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
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return -EINVAL;
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if (strict_strtoul(buf, 16, &val) < 0)
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return -EINVAL;
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if (amd_set_subcaches(cpu, val))
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return -EINVAL;
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return count;
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}
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static struct _cache_attr subcaches =
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__ATTR(subcaches, 0644, show_subcaches, store_subcaches);
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#else /* CONFIG_AMD_NB */
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#define amd_init_l3_cache(x, y)
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#endif /* CONFIG_AMD_NB */
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@ -532,9 +568,9 @@ static int
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__cpuinit cpuid4_cache_lookup_regs(int index,
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struct _cpuid4_info_regs *this_leaf)
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{
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union _cpuid4_leaf_eax eax;
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union _cpuid4_leaf_ebx ebx;
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union _cpuid4_leaf_ecx ecx;
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union _cpuid4_leaf_eax eax;
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union _cpuid4_leaf_ebx ebx;
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union _cpuid4_leaf_ecx ecx;
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unsigned edx;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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@ -870,8 +906,8 @@ static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject);
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#define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y]))
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#define show_one_plus(file_name, object, val) \
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static ssize_t show_##file_name \
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(struct _cpuid4_info *this_leaf, char *buf) \
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static ssize_t show_##file_name(struct _cpuid4_info *this_leaf, char *buf, \
|
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unsigned int cpu) \
|
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{ \
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return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
|
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}
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@ -882,7 +918,8 @@ show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
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show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
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show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
|
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static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
|
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static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf,
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unsigned int cpu)
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{
|
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return sprintf(buf, "%luK\n", this_leaf->size / 1024);
|
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}
|
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@ -906,17 +943,20 @@ static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
|
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return n;
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}
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static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
|
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static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf,
|
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unsigned int cpu)
|
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{
|
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return show_shared_cpu_map_func(leaf, 0, buf);
|
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}
|
||||
|
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static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
|
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static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf,
|
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unsigned int cpu)
|
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{
|
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return show_shared_cpu_map_func(leaf, 1, buf);
|
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}
|
||||
|
||||
static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
|
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static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf,
|
||||
unsigned int cpu)
|
||||
{
|
||||
switch (this_leaf->eax.split.type) {
|
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case CACHE_TYPE_DATA:
|
||||
|
|
@ -974,6 +1014,9 @@ static struct attribute ** __cpuinit amd_l3_attrs(void)
|
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if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
|
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n += 2;
|
||||
|
||||
if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
|
||||
n += 1;
|
||||
|
||||
attrs = kzalloc(n * sizeof (struct attribute *), GFP_KERNEL);
|
||||
if (attrs == NULL)
|
||||
return attrs = default_attrs;
|
||||
|
|
@ -986,6 +1029,9 @@ static struct attribute ** __cpuinit amd_l3_attrs(void)
|
|||
attrs[n++] = &cache_disable_1.attr;
|
||||
}
|
||||
|
||||
if (amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
|
||||
attrs[n++] = &subcaches.attr;
|
||||
|
||||
return attrs;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -998,7 +1044,7 @@ static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
|
|||
|
||||
ret = fattr->show ?
|
||||
fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
|
||||
buf) :
|
||||
buf, this_leaf->cpu) :
|
||||
0;
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1012,7 +1058,7 @@ static ssize_t store(struct kobject *kobj, struct attribute *attr,
|
|||
|
||||
ret = fattr->store ?
|
||||
fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
|
||||
buf, count) :
|
||||
buf, count, this_leaf->cpu) :
|
||||
0;
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -414,6 +414,7 @@ void __cpuinit set_cpu_sibling_map(int cpu)
|
|||
|
||||
if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
|
||||
if (c->phys_proc_id == o->phys_proc_id &&
|
||||
per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
|
||||
c->compute_unit_id == o->compute_unit_id)
|
||||
link_thread_siblings(cpu, i);
|
||||
} else if (c->phys_proc_id == o->phys_proc_id &&
|
||||
|
|
|
|||
|
|
@ -350,7 +350,7 @@ static int __init early_fill_mp_bus_info(void)
|
|||
|
||||
#define ENABLE_CF8_EXT_CFG (1ULL << 46)
|
||||
|
||||
static void enable_pci_io_ecs(void *unused)
|
||||
static void __cpuinit enable_pci_io_ecs(void *unused)
|
||||
{
|
||||
u64 reg;
|
||||
rdmsrl(MSR_AMD64_NB_CFG, reg);
|
||||
|
|
|
|||
|
|
@ -518,6 +518,7 @@
|
|||
#define PCI_DEVICE_ID_AMD_11H_NB_MISC 0x1303
|
||||
#define PCI_DEVICE_ID_AMD_11H_NB_LINK 0x1304
|
||||
#define PCI_DEVICE_ID_AMD_15H_NB_MISC 0x1603
|
||||
#define PCI_DEVICE_ID_AMD_15H_NB_LINK 0x1604
|
||||
#define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703
|
||||
#define PCI_DEVICE_ID_AMD_LANCE 0x2000
|
||||
#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001
|
||||
|
|
|
|||
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