perf, x86: Use unlocked bitops
There is no concurrency on these variables, so don't use LOCK'ed ops. As to the intel_pmu_handle_irq() status bit clean, nobody uses that so remove it all together. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: paulus@samba.org Cc: eranian@google.com Cc: robert.richter@amd.com Cc: fweisbec@gmail.com Cc: Arnaldo Carvalho de Melo <acme@infradead.org> LKML-Reference: <20100304140100.240023029@chello.nl> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -643,7 +643,7 @@ static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
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if (test_bit(hwc->idx, used_mask))
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break;
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set_bit(hwc->idx, used_mask);
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__set_bit(hwc->idx, used_mask);
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if (assign)
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assign[i] = hwc->idx;
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}
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@ -692,7 +692,7 @@ static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
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if (j == X86_PMC_IDX_MAX)
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break;
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set_bit(j, used_mask);
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__set_bit(j, used_mask);
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if (assign)
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assign[i] = j;
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@ -842,7 +842,7 @@ void hw_perf_enable(void)
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* clear active_mask and events[] yet it preserves
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* idx
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*/
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set_bit(hwc->idx, cpuc->active_mask);
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__set_bit(hwc->idx, cpuc->active_mask);
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cpuc->events[hwc->idx] = event;
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x86_pmu.enable(event);
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@ -1057,7 +1057,7 @@ static void x86_pmu_stop(struct perf_event *event)
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* Must be done before we disable, otherwise the nmi handler
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* could reenable again:
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*/
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clear_bit(idx, cpuc->active_mask);
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__clear_bit(idx, cpuc->active_mask);
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x86_pmu.disable(event);
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/*
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@ -287,7 +287,7 @@ static struct amd_nb *amd_alloc_nb(int cpu, int nb_id)
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* initialize all possible NB constraints
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*/
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for (i = 0; i < x86_pmu.num_events; i++) {
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set_bit(i, nb->event_constraints[i].idxmsk);
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__set_bit(i, nb->event_constraints[i].idxmsk);
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nb->event_constraints[i].weight = 1;
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}
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return nb;
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@ -765,7 +765,6 @@ again:
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for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
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struct perf_event *event = cpuc->events[bit];
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clear_bit(bit, (unsigned long *) &status);
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if (!test_bit(bit, cpuc->active_mask))
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continue;
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