powerpc/fsl-pci: Keep PCI SoC controller registers in pci_controller
Move to keeping the SoC registers that control and config the PCI controllers on FSL SoCs in the pci_controller struct. This allows us to not need to ioremap() the registers in multiple different places that use them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
Родитель
9f4c350d52
Коммит
34642bbb3d
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@ -70,6 +70,8 @@ struct pci_controller {
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* BIG_ENDIAN - cfg_addr is a big endian register
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* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
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* the PLB4. Effectively disable MRM commands by setting this.
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* FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
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* link status is in a RC PCIe cfg register (vs being a SoC register)
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*/
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#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
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#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
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@ -77,6 +79,7 @@ struct pci_controller {
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#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
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#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
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#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
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#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
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u32 indirect_type;
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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* ranges since the common pci_bus structure can't handle more
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@ -90,9 +93,9 @@ struct pci_controller {
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#ifdef CONFIG_PPC64
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unsigned long buid;
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#endif /* CONFIG_PPC64 */
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void *private_data;
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#endif /* CONFIG_PPC64 */
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};
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/* These are used for config access before all the PCI probing
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@ -54,34 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
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return;
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}
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static int __init fsl_pcie_check_link(struct pci_controller *hose,
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struct resource *rsrc)
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static int __init fsl_pcie_check_link(struct pci_controller *hose)
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{
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struct ccsr_pci __iomem *pci = NULL;
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u32 val;
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/* for PCIe IP rev 3.0 or greater use CSR0 for link state */
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if (rsrc) {
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pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
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(u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
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pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
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if (!pci) {
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dev_err(hose->parent, "Unable to map PCIe registers\n");
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return -ENOMEM;
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}
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if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_3_0) {
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val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
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>> PEX_CSR0_LTSSM_SHIFT;
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if (val != PEX_CSR0_LTSSM_L0)
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return 1;
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iounmap(pci);
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return 0;
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}
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iounmap(pci);
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if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
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early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return 1;
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} else {
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struct ccsr_pci __iomem *pci = hose->private_data;
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/* for PCIe IP rev 3.0 or greater use CSR0 for link state */
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val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
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>> PEX_CSR0_LTSSM_SHIFT;
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if (val != PEX_CSR0_LTSSM_L0)
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return 1;
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}
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early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
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if (val < PCIE_LTSSM_L0)
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return 1;
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return 0;
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}
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@ -148,10 +136,9 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
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}
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/* atmu setup for fsl pci/pcie controller */
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static void setup_pci_atmu(struct pci_controller *hose,
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struct resource *rsrc)
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static void setup_pci_atmu(struct pci_controller *hose)
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{
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struct ccsr_pci __iomem *pci;
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struct ccsr_pci __iomem *pci = hose->private_data;
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int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
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u64 mem, sz, paddr_hi = 0;
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u64 paddr_lo = ULLONG_MAX;
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@ -162,15 +149,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
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const u64 *reg;
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int len;
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pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
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(u64)rsrc->start, (u64)resource_size(rsrc));
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pci = ioremap(rsrc->start, resource_size(rsrc));
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if (!pci) {
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dev_err(hose->parent, "Unable to map ATMU registers\n");
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return;
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}
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if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
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if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
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win_idx = 2;
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@ -451,6 +429,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
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const int *bus_range;
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u8 hdr_type, progif;
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struct device_node *dev;
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struct ccsr_pci __iomem *pci;
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dev = pdev->dev.of_node;
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@ -483,9 +462,19 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
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(u64)rsrc.start, (u64)resource_size(&rsrc));
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pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
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if (!hose->private_data)
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goto no_bridge;
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
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PPC_INDIRECT_TYPE_BIG_ENDIAN);
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if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
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hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
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if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
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/* For PCIE read HEADER_TYPE to identify controler mode */
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early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
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@ -505,7 +494,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
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if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
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hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
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PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
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if (fsl_pcie_check_link(hose, &rsrc))
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if (fsl_pcie_check_link(hose))
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hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
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}
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@ -522,11 +511,12 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
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pci_process_bridge_OF_ranges(hose, dev, is_primary);
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/* Setup PEX window registers */
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setup_pci_atmu(hose, &rsrc);
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setup_pci_atmu(hose);
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return 0;
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no_bridge:
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iounmap(hose->private_data);
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/* unmap cfg_data & cfg_addr separately if not on same page */
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if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
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((unsigned long)hose->cfg_addr & PAGE_MASK))
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@ -703,11 +693,12 @@ static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
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WARN_ON(hose->dn->data);
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hose->dn->data = pcie;
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hose->ops = &mpc83xx_pcie_ops;
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hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
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out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
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out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
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if (fsl_pcie_check_link(hose, NULL))
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if (fsl_pcie_check_link(hose))
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hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
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return 0;
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