clk: tegra: Fix ISP clock modelling
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model this as 1 mux/divider clock and child gate clocks. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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34ac2c278b
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@ -307,6 +307,7 @@ enum clk_id {
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tegra_clk_xusb_ssp_src,
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tegra_clk_sclk_mux,
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tegra_clk_sor_safe,
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tegra_clk_ispa,
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tegra_clk_max,
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};
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@ -168,6 +168,12 @@
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0, TEGRA_PERIPH_NO_GATE, _clk_id,\
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_parents##_idx, 0, _lock)
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#define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
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29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
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0, TEGRA_PERIPH_NO_GATE, _clk_id,\
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_parents##_idx, 0, NULL)
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#define INT(_name, _parents, _offset, \
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_clk_num, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
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@ -739,7 +745,7 @@ static struct tegra_periph_init_data periph_clks[] = {
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MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
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MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
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MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
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MUX8("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_9),
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MUX8_NOGATE("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, tegra_clk_isp_9),
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MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
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MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8),
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MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
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@ -819,7 +825,8 @@ static struct tegra_periph_init_data gate_clks[] = {
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GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
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GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
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GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
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GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
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GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
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GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
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GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
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GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
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GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
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@ -2210,6 +2210,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
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[tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
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[tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
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[tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
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[tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
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};
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static struct tegra_devclk devclks[] __initdata = {
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@ -39,7 +39,7 @@
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/* 20 (register bit affects vi and vi_sensor) */
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/* 21 */
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#define TEGRA210_CLK_USBD 22
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#define TEGRA210_CLK_ISP 23
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#define TEGRA210_CLK_ISPA 23
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/* 24 */
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/* 25 */
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#define TEGRA210_CLK_DISP2 26
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@ -349,7 +349,7 @@
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#define TEGRA210_CLK_PLL_RE_OUT1 319
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/* 320 */
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/* 321 */
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/* 322 */
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#define TEGRA210_CLK_ISP 322
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/* 323 */
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/* 324 */
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/* 325 */
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