dt-bindings: pinctrl: aspeed: Split bindings document in two
Have one for each of the AST2400 and AST2500. The only thing that was common was the fact that both support ASPEED BMC SoCs. Cc: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20190628023838.15426-2-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Andrew Jeffery
Linus Walleij
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Коммит
34ae69998b
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@ -0,0 +1,80 @@
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=============================
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Aspeed AST2400 Pin Controller
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=============================
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Required properties for the AST2400:
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- compatible : Should be one of the following:
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"aspeed,ast2400-pinctrl"
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"aspeed,g4-pinctrl"
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The pin controller node should be the child of a syscon node with the required
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property:
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- compatible : Should be one of the following:
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"aspeed,ast2400-scu", "syscon", "simple-mfd"
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"aspeed,g4-scu", "syscon", "simple-mfd"
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Refer to the the bindings described in
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Documentation/devicetree/bindings/mfd/syscon.txt
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Subnode Format
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==============
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The required properties of pinmux child nodes are:
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- function: the mux function to select
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- groups : the list of groups to select with this function
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Required properties of pinconf child nodes are:
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- groups: A list of groups to select (either this or "pins" must be
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specified)
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- pins : A list of ball names as strings, eg "D14" (either this or "groups"
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must be specified)
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Optional properties of pinconf child nodes are:
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- bias-disable : disable any pin bias
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- bias-pull-down: pull down the pin
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- drive-strength: sink or source at most X mA
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Definitions are as specified in
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Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt, with any
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further limitations as described above.
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For pinmux, each mux function has only one associated pin group. Each group is
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named by its function. The following values for the function and groups
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properties are supported:
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ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
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ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2
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GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4
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I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1
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MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4
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NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0
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PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
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ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
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SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
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SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
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TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
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USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
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WDTRST2
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Example
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=======
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syscon: scu@1e6e2000 {
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compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
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reg = <0x1e6e2000 0x1a8>;
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pinctrl: pinctrl {
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compatible = "aspeed,g4-pinctrl";
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pinctrl_i2c3_default: i2c3_default {
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function = "I2C3";
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groups = "I2C3";
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};
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pinctrl_gpioh0_unbiased_default: gpioh0 {
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pins = "A8";
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bias-disable;
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};
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};
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};
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@ -1,14 +1,6 @@
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======================
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Aspeed Pin Controllers
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======================
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The Aspeed SoCs vary in functionality inside a generation but have a common mux
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device register layout.
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Required properties for g4:
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- compatible : Should be one of the following:
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"aspeed,ast2400-pinctrl"
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"aspeed,g4-pinctrl"
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=============================
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Aspeed AST2500 Pin Controller
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=============================
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Required properties for g5:
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- compatible : Should be one of the following:
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@ -23,8 +15,6 @@ The pin controller node should be the child of a syscon node with the required
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property:
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- compatible : Should be one of the following:
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"aspeed,ast2400-scu", "syscon", "simple-mfd"
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"aspeed,g4-scu", "syscon", "simple-mfd"
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"aspeed,ast2500-scu", "syscon", "simple-mfd"
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"aspeed,g5-scu", "syscon", "simple-mfd"
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@ -57,24 +47,6 @@ For pinmux, each mux function has only one associated pin group. Each group is
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named by its function. The following values for the function and groups
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properties are supported:
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aspeed,ast2400-pinctrl, aspeed,g4-pinctrl:
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ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
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ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2
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GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4
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I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1
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MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4
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NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0
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PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
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ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
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SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
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SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
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TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
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USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
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WDTRST2
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aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
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ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
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ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4
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GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6
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@ -90,33 +62,8 @@ SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
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TXD3 TXD4 UART6 USB11BHID USB2AD USB2AH USB2BD USB2BH USBCKI VGABIOSROM VGAHS
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VGAVS VPI24 VPO WDTRST1 WDTRST2
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Examples
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========
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g4 Example
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----------
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syscon: scu@1e6e2000 {
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compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
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reg = <0x1e6e2000 0x1a8>;
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pinctrl: pinctrl {
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compatible = "aspeed,g4-pinctrl";
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pinctrl_i2c3_default: i2c3_default {
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function = "I2C3";
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groups = "I2C3";
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};
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pinctrl_gpioh0_unbiased_default: gpioh0 {
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pins = "A8";
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bias-disable;
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};
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};
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};
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g5 Example
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----------
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Example
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=======
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ahb {
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apb {
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