From 101353c82a4435aa2fc5bbd4aebafcd2d388171c Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sat, 21 Jun 2014 16:22:06 +0200 Subject: [PATCH 01/13] pwm: add Rockchip SoC PWM support This commit adds a driver for the PWM controller found on Rockchip RK29, RK30 and RK31 SoCs. Signed-off-by: Beniamino Galvani Signed-off-by: Thierry Reding --- drivers/pwm/Kconfig | 7 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-rockchip.c | 177 +++++++++++++++++++++++++++++++++++++ 3 files changed, 185 insertions(+) create mode 100644 drivers/pwm/pwm-rockchip.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 4ad7b89a4cb4..a86879a313e4 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -206,6 +206,13 @@ config PWM_RENESAS_TPU To compile this driver as a module, choose M here: the module will be called pwm-renesas-tpu. +config PWM_ROCKCHIP + tristate "Rockchip PWM support" + depends on ARCH_ROCKCHIP + help + Generic PWM framework driver for the PWM controller found on + Rockchip SoCs. + config PWM_SAMSUNG tristate "Samsung PWM support" depends on PLAT_SAMSUNG diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 5c86a19d5d39..e03e2ae95791 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o +obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c new file mode 100644 index 000000000000..eec214568193 --- /dev/null +++ b/drivers/pwm/pwm-rockchip.c @@ -0,0 +1,177 @@ +/* + * PWM driver for Rockchip SoCs + * + * Copyright (C) 2014 Beniamino Galvani + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PWM_CNTR 0x00 /* Counter register */ +#define PWM_HRC 0x04 /* High reference register */ +#define PWM_LRC 0x08 /* Low reference register */ +#define PWM_CTRL 0x0c /* Control register */ +#define PWM_CTRL_TIMER_EN (1 << 0) +#define PWM_CTRL_OUTPUT_EN (1 << 3) + +#define PRESCALER 2 + +struct rockchip_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + void __iomem *base; +}; + +static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) +{ + return container_of(c, struct rockchip_pwm_chip, chip); +} + +static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + unsigned long period, duty; + u64 clk_rate, div; + int ret; + + clk_rate = clk_get_rate(pc->clk); + + /* + * Since period and duty cycle registers have a width of 32 + * bits, every possible input period can be obtained using the + * default prescaler value for all practical clock rate values. + */ + div = clk_rate * period_ns; + do_div(div, PRESCALER * NSEC_PER_SEC); + period = div; + + div = clk_rate * duty_ns; + do_div(div, PRESCALER * NSEC_PER_SEC); + duty = div; + + ret = clk_enable(pc->clk); + if (ret) + return ret; + + writel(period, pc->base + PWM_LRC); + writel(duty, pc->base + PWM_HRC); + writel(0, pc->base + PWM_CNTR); + + clk_disable(pc->clk); + + return 0; +} + +static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + int ret; + u32 val; + + ret = clk_enable(pc->clk); + if (ret) + return ret; + + val = readl_relaxed(pc->base + PWM_CTRL); + val |= PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; + writel_relaxed(val, pc->base + PWM_CTRL); + + return 0; +} + +static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u32 val; + + val = readl_relaxed(pc->base + PWM_CTRL); + val &= ~(PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN); + writel_relaxed(val, pc->base + PWM_CTRL); + + clk_disable(pc->clk); +} + +static const struct pwm_ops rockchip_pwm_ops = { + .config = rockchip_pwm_config, + .enable = rockchip_pwm_enable, + .disable = rockchip_pwm_disable, + .owner = THIS_MODULE, +}; + +static int rockchip_pwm_probe(struct platform_device *pdev) +{ + struct rockchip_pwm_chip *pc; + struct resource *r; + int ret; + + pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); + if (!pc) + return -ENOMEM; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pc->base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(pc->base)) + return PTR_ERR(pc->base); + + pc->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pc->clk)) + return PTR_ERR(pc->clk); + + ret = clk_prepare(pc->clk); + if (ret) + return ret; + + platform_set_drvdata(pdev, pc); + + pc->chip.dev = &pdev->dev; + pc->chip.ops = &rockchip_pwm_ops; + pc->chip.base = -1; + pc->chip.npwm = 1; + + ret = pwmchip_add(&pc->chip); + if (ret < 0) { + clk_unprepare(pc->clk); + dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); + } + + return ret; +} + +static int rockchip_pwm_remove(struct platform_device *pdev) +{ + struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); + + clk_unprepare(pc->clk); + + return pwmchip_remove(&pc->chip); +} + +static const struct of_device_id rockchip_pwm_dt_ids[] = { + { .compatible = "rockchip,rk2928-pwm" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); + +static struct platform_driver rockchip_pwm_driver = { + .driver = { + .name = "rockchip-pwm", + .of_match_table = rockchip_pwm_dt_ids, + }, + .probe = rockchip_pwm_probe, + .remove = rockchip_pwm_remove, +}; +module_platform_driver(rockchip_pwm_driver); + +MODULE_AUTHOR("Beniamino Galvani "); +MODULE_DESCRIPTION("Rockchip SoC PWM driver"); +MODULE_LICENSE("GPL v2"); From eae266a284f370d40c50dbed7a988a744bab0d44 Mon Sep 17 00:00:00 2001 From: Beniamino Galvani Date: Sat, 21 Jun 2014 16:22:07 +0200 Subject: [PATCH 02/13] pwm: rockchip: document device tree bindings This adds binding documentation for Rockchip SoC PWM driver. Signed-off-by: Beniamino Galvani Signed-off-by: Thierry Reding --- .../devicetree/bindings/pwm/pwm-rockchip.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-rockchip.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt new file mode 100644 index 000000000000..3182126189bf --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt @@ -0,0 +1,17 @@ +Rockchip PWM controller + +Required properties: + - compatible: should be "rockchip,rk2928-pwm" + - reg: physical base address and length of the controller's registers + - clocks: phandle and clock specifier of the PWM reference clock + - #pwm-cells: should be 2. See pwm.txt in this directory for a + description of the cell format. + +Example: + + pwm0: pwm@20030000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030000 0x10>; + clocks = <&cru PCLK_PWM01>; + #pwm-cells = <2>; + }; From ed1a819a3fdbde279f3ca18e2268cc12666e9bf1 Mon Sep 17 00:00:00 2001 From: Jingoo Han Date: Wed, 18 Jun 2014 14:50:08 +0900 Subject: [PATCH 03/13] pwm: pwm-tipwmss: remove unnecessary OOM messages The site-specific OOM messages are unnecessary, because they duplicate the MM subsystem generic OOM message. The following checkpatch warning is also removed. WARNING: Possible unnecessary 'out of memory' message Signed-off-by: Jingoo Han Signed-off-by: Thierry Reding --- drivers/pwm/pwm-tipwmss.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-tipwmss.c b/drivers/pwm/pwm-tipwmss.c index 3b119bc2c3c6..67481dc6da3f 100644 --- a/drivers/pwm/pwm-tipwmss.c +++ b/drivers/pwm/pwm-tipwmss.c @@ -62,10 +62,8 @@ static int pwmss_probe(struct platform_device *pdev) struct device_node *node = pdev->dev.of_node; info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); - if (!info) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + if (!info) return -ENOMEM; - } mutex_init(&info->pwmss_lock); From 65accd87381ed96bf8893124b149bae08edd2740 Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Fri, 9 May 2014 11:35:21 +0300 Subject: [PATCH 04/13] pwm: lpss: remove dependency on clk framework Unlike other Intel LPSS devices, the PWM does not have the clock dividers or the gate. All we get from the clock is the rate. Since PCI case uses the driver data to get the rate, we can drop the clk and use the same data also in case of ACPI. The frequency is the same. Signed-off-by: Heikki Krogerus Reviewed-by: Mika Westerberg Reviewed-by: Chew, Chiau Ee Signed-off-by: Thierry Reding --- drivers/pwm/pwm-lpss.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index 44ce6c6103ae..4df994f72d96 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -14,7 +14,6 @@ */ #include -#include #include #include #include @@ -37,7 +36,6 @@ static int pci_drv, plat_drv; /* So we know which drivers registered */ struct pwm_lpss_chip { struct pwm_chip chip; void __iomem *regs; - struct clk *clk; unsigned long clk_rate; }; @@ -97,11 +95,6 @@ static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm) { struct pwm_lpss_chip *lpwm = to_lpwm(chip); u32 ctrl; - int ret; - - ret = clk_prepare_enable(lpwm->clk); - if (ret) - return ret; ctrl = readl(lpwm->regs + PWM); writel(ctrl | PWM_ENABLE, lpwm->regs + PWM); @@ -116,8 +109,6 @@ static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm) ctrl = readl(lpwm->regs + PWM); writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); - - clk_disable_unprepare(lpwm->clk); } static const struct pwm_ops pwm_lpss_ops = { @@ -142,17 +133,7 @@ static struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, if (IS_ERR(lpwm->regs)) return ERR_CAST(lpwm->regs); - if (info) { - lpwm->clk_rate = info->clk_rate; - } else { - lpwm->clk = devm_clk_get(dev, NULL); - if (IS_ERR(lpwm->clk)) { - dev_err(dev, "failed to get PWM clock\n"); - return ERR_CAST(lpwm->clk); - } - lpwm->clk_rate = clk_get_rate(lpwm->clk); - } - + lpwm->clk_rate = info->clk_rate; lpwm->chip.dev = dev; lpwm->chip.ops = &pwm_lpss_ops; lpwm->chip.base = -1; @@ -221,12 +202,19 @@ static struct pci_driver pwm_lpss_driver_pci = { static int pwm_lpss_probe_platform(struct platform_device *pdev) { + const struct pwm_lpss_boardinfo *info; + const struct acpi_device_id *id; struct pwm_lpss_chip *lpwm; struct resource *r; + id = acpi_match_device(pdev->dev.driver->acpi_match_table, &pdev->dev); + if (!id) + return -ENODEV; + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - lpwm = pwm_lpss_probe(&pdev->dev, r, NULL); + info = (struct pwm_lpss_boardinfo *)id->driver_data; + lpwm = pwm_lpss_probe(&pdev->dev, r, info); if (IS_ERR(lpwm)) return PTR_ERR(lpwm); @@ -242,7 +230,7 @@ static int pwm_lpss_remove_platform(struct platform_device *pdev) } static const struct acpi_device_id pwm_lpss_acpi_match[] = { - { "80860F09", 0 }, + { "80860F09", (unsigned long)&byt_info }, { }, }; MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match); From 31c4fa3442570d001f58303dea36d81693bc199c Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Fri, 23 May 2014 16:41:28 +0800 Subject: [PATCH 05/13] pwm: imx: set can_sleep flag for imx_pwm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The .config() hook imx_pwm_config() calls clk APIs like clk_prepare() and clk_get_rate(), which might sleep, so we need to set can_sleep flag on pwm_chip. Signed-off-by: Shawn Guo Acked-by: Uwe Kleine-König Signed-off-by: Thierry Reding --- drivers/pwm/pwm-imx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index d797c7b84c3f..5449d9150d40 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -262,6 +262,7 @@ static int imx_pwm_probe(struct platform_device *pdev) imx->chip.dev = &pdev->dev; imx->chip.base = -1; imx->chip.npwm = 1; + imx->chip.can_sleep = true; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); imx->mmio_base = devm_ioremap_resource(&pdev->dev, r); From 378fe115d19d6ab9e9210a2ac330159afabf0237 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 14 Jul 2014 15:33:27 +0100 Subject: [PATCH 06/13] pwm: sti: Add new driver for ST's PWM IP This driver supports all current STi platforms' PWM IPs. Signed-off-by: Ajit Pal Singh Signed-off-by: Lee Jones [thierry.reding: rename module to pwm-sti, fix build breakage] Signed-off-by: Thierry Reding --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sti.c | 366 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 377 insertions(+) create mode 100644 drivers/pwm/pwm-sti.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index a86879a313e4..fabd0c5cd6cc 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -233,6 +233,16 @@ config PWM_SPEAR To compile this driver as a module, choose M here: the module will be called pwm-spear. +config PWM_STI + tristate "STiH4xx PWM support" + depends on ARCH_STI + depends on OF + help + Generic PWM framework driver for STiH4xx SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sti. + config PWM_TEGRA tristate "NVIDIA Tegra PWM support" depends on ARCH_TEGRA diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index e03e2ae95791..f8c577d41091 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o +obj-$(CONFIG_PWM_STI) += pwm-sti.o obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o obj-$(CONFIG_PWM_TIEHRPWM) += pwm-tiehrpwm.o diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c new file mode 100644 index 000000000000..0b714e45e5c0 --- /dev/null +++ b/drivers/pwm/pwm-sti.c @@ -0,0 +1,366 @@ +/* + * PWM device driver for ST SoCs. + * Author: Ajit Pal Singh + * + * Copyright (C) 2013-2014 STMicroelectronics (R&D) Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STI_DS_REG(ch) (4 * (ch)) /* Channel's Duty Cycle register */ +#define STI_PWMCR 0x50 /* Control/Config register */ +#define STI_INTEN 0x54 /* Interrupt Enable/Disable register */ + +/* Regfield IDs */ +enum { + PWMCLK_PRESCALE, + PWM_EN, + PWM_INT_EN, + + /* Keep last */ + MAX_REGFIELDS +}; + +struct sti_pwm_compat_data { + const struct reg_field *reg_fields; + unsigned int num_chan; + unsigned int max_pwm_cnt; + unsigned int max_prescale; +}; + +struct sti_pwm_chip { + struct device *dev; + struct clk *clk; + unsigned long clk_rate; + struct regmap *regmap; + struct sti_pwm_compat_data *cdata; + struct regmap_field *prescale; + struct regmap_field *pwm_en; + struct regmap_field *pwm_int_en; + unsigned long *pwm_periods; + struct pwm_chip chip; + void __iomem *mmio; +}; + +static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = { + [PWMCLK_PRESCALE] = REG_FIELD(STI_PWMCR, 0, 3), + [PWM_EN] = REG_FIELD(STI_PWMCR, 9, 9), + [PWM_INT_EN] = REG_FIELD(STI_INTEN, 0, 0), +}; + +static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip) +{ + return container_of(chip, struct sti_pwm_chip, chip); +} + +/* + * Calculate the period values supported by the PWM for the + * current clock rate. + */ +static void sti_pwm_calc_periods(struct sti_pwm_chip *pc) +{ + struct sti_pwm_compat_data *cdata = pc->cdata; + struct device *dev = pc->dev; + unsigned long val; + int i; + + /* + * period_ns = (10^9 * (prescaler + 1) * (MAX_PWM_COUNT + 1)) / CLK_RATE + */ + val = NSEC_PER_SEC / pc->clk_rate; + val *= cdata->max_pwm_cnt + 1; + + dev_dbg(dev, "possible periods for clkrate[HZ]:%lu\n", pc->clk_rate); + + for (i = 0; i <= cdata->max_prescale; i++) { + pc->pwm_periods[i] = val * (i + 1); + dev_dbg(dev, "prescale:%d, period[ns]:%lu\n", + i, pc->pwm_periods[i]); + } +} + +static int sti_pwm_cmp_periods(const void *key, const void *elt) +{ + unsigned long i = *(unsigned long *)key; + unsigned long j = *(unsigned long *)elt; + + if (i < j) + return -1; + else + return i == j ? 0 : 1; +} + +/* + * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. + * The only way to change the period (apart from changing the PWM input clock) + * is to change the PWM clock prescaler. + * The prescaler is of 4 bits, so only 16 prescaler values and hence only + * 16 possible period values are supported (for a particular clock rate). + * The requested period will be applied only if it matches one of these + * 16 values. + */ +static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct sti_pwm_chip *pc = to_sti_pwmchip(chip); + struct sti_pwm_compat_data *cdata = pc->cdata; + struct device *dev = pc->dev; + unsigned int prescale, pwmvalx; + unsigned long *found; + int ret; + + /* + * Search for matching period value. The corresponding index is our + * prescale value + */ + found = bsearch(&period_ns, &pc->pwm_periods[0], + cdata->max_prescale + 1, sizeof(unsigned long), + sti_pwm_cmp_periods); + if (!found) { + dev_err(dev, "failed to find matching period\n"); + return -EINVAL; + } + + prescale = found - &pc->pwm_periods[0]; + + /* + * When PWMVal == 0, PWM pulse = 1 local clock cycle. + * When PWMVal == max_pwm_count, + * PWM pulse = (max_pwm_count + 1) local cycles, + * that is continuous pulse: signal never goes low. + */ + pwmvalx = cdata->max_pwm_cnt * duty_ns / period_ns; + + dev_dbg(dev, "prescale:%u, period:%i, duty:%i, pwmvalx:%u\n", + prescale, period_ns, duty_ns, pwmvalx); + + /* Enable clock before writing to PWM registers */ + ret = clk_enable(pc->clk); + if (ret) + return ret; + + ret = regmap_field_write(pc->prescale, prescale); + if (ret) + goto clk_dis; + + ret = regmap_write(pc->regmap, STI_PWMVAL(pwm->hwpwm), pwmvalx); + if (ret) + goto clk_dis; + + ret = regmap_field_write(pc->pwm_int_en, 0); + +clk_dis: + clk_disable(pc->clk); + return ret; +} + +static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct sti_pwm_chip *pc = to_sti_pwmchip(chip); + struct device *dev = pc->dev; + int ret; + + ret = clk_enable(pc->clk); + if (ret) + return ret; + + ret = regmap_field_write(pc->pwm_en, 1); + if (ret) + dev_err(dev, "%s,pwm_en write failed\n", __func__); + + return ret; +} + +static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct sti_pwm_chip *pc = to_sti_pwmchip(chip); + struct device *dev = pc->dev; + unsigned int val; + + regmap_field_write(pc->pwm_en, 0); + + regmap_read(pc->regmap, STI_CNT, &val); + + dev_dbg(dev, "pwm counter :%u\n", val); + + clk_disable(pc->clk); +} + +static const struct pwm_ops sti_pwm_ops = { + .config = sti_pwm_config, + .enable = sti_pwm_enable, + .disable = sti_pwm_disable, + .owner = THIS_MODULE, +}; + +static int sti_pwm_probe_dt(struct sti_pwm_chip *pc) +{ + struct device *dev = pc->dev; + const struct reg_field *reg_fields; + struct device_node *np = dev->of_node; + struct sti_pwm_compat_data *cdata = pc->cdata; + u32 num_chan; + + of_property_read_u32(np, "st,pwm-num-chan", &num_chan); + if (num_chan) + cdata->num_chan = num_chan; + + reg_fields = cdata->reg_fields; + + pc->prescale = devm_regmap_field_alloc(dev, pc->regmap, + reg_fields[PWMCLK_PRESCALE]); + if (IS_ERR(pc->prescale)) + return PTR_ERR(pc->prescale); + + pc->pwm_en = devm_regmap_field_alloc(dev, pc->regmap, + reg_fields[PWM_EN]); + if (IS_ERR(pc->pwm_en)) + return PTR_ERR(pc->pwm_en); + + pc->pwm_int_en = devm_regmap_field_alloc(dev, pc->regmap, + reg_fields[PWM_INT_EN]); + if (IS_ERR(pc->pwm_int_en)) + return PTR_ERR(pc->pwm_int_en); + + return 0; +} + +static const struct regmap_config sti_pwm_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int sti_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sti_pwm_compat_data *cdata; + struct sti_pwm_chip *pc; + struct resource *res; + int ret; + + pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); + if (!pc) + return -ENOMEM; + + cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL); + if (!cdata) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + pc->mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(pc->mmio)) + return PTR_ERR(pc->mmio); + + pc->regmap = devm_regmap_init_mmio(dev, pc->mmio, + &sti_pwm_regmap_config); + if (IS_ERR(pc->regmap)) + return PTR_ERR(pc->regmap); + + /* + * Setup PWM data with default values: some values could be replaced + * with specific ones provided from Device Tree. + */ + cdata->reg_fields = &sti_pwm_regfields[0]; + cdata->max_prescale = 0xff; + cdata->max_pwm_cnt = 255; + cdata->num_chan = 1; + + pc->cdata = cdata; + pc->dev = dev; + + ret = sti_pwm_probe_dt(pc); + if (ret) + return ret; + + pc->pwm_periods = devm_kzalloc(dev, + sizeof(unsigned long) * (pc->cdata->max_prescale + 1), + GFP_KERNEL); + if (!pc->pwm_periods) + return -ENOMEM; + + pc->clk = of_clk_get_by_name(dev->of_node, "pwm"); + if (IS_ERR(pc->clk)) { + dev_err(dev, "failed to get PWM clock\n"); + return PTR_ERR(pc->clk); + } + + pc->clk_rate = clk_get_rate(pc->clk); + if (!pc->clk_rate) { + dev_err(dev, "failed to get clock rate\n"); + return -EINVAL; + } + + ret = clk_prepare(pc->clk); + if (ret) { + dev_err(dev, "failed to prepare clock\n"); + return ret; + } + + sti_pwm_calc_periods(pc); + + pc->chip.dev = dev; + pc->chip.ops = &sti_pwm_ops; + pc->chip.base = -1; + pc->chip.npwm = pc->cdata->num_chan; + pc->chip.can_sleep = true; + + ret = pwmchip_add(&pc->chip); + if (ret < 0) { + clk_unprepare(pc->clk); + return ret; + } + + platform_set_drvdata(pdev, pc); + + return 0; +} + +static int sti_pwm_remove(struct platform_device *pdev) +{ + struct sti_pwm_chip *pc = platform_get_drvdata(pdev); + unsigned int i; + + for (i = 0; i < pc->cdata->num_chan; i++) + pwm_disable(&pc->chip.pwms[i]); + + clk_unprepare(pc->clk); + + return pwmchip_remove(&pc->chip); +} + +static const struct of_device_id sti_pwm_of_match[] = { + { .compatible = "st,sti-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sti_pwm_of_match); + +static struct platform_driver sti_pwm_driver = { + .driver = { + .name = "sti-pwm", + .of_match_table = sti_pwm_of_match, + }, + .probe = sti_pwm_probe, + .remove = sti_pwm_remove, +}; +module_platform_driver(sti_pwm_driver); + +MODULE_AUTHOR("Ajit Pal Singh "); +MODULE_DESCRIPTION("STMicroelectronics ST PWM driver"); +MODULE_LICENSE("GPL"); From acad00d3d67ef2a7177beb70e7aeef5f0bd2bcf0 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 14 Jul 2014 15:33:28 +0100 Subject: [PATCH 07/13] pwm: sti: Supply Device Tree binding documentation for ST's PWM IP Signed-off-by: Ajit Pal Singh Signed-off-by: Lee Jones Signed-off-by: Thierry Reding --- .../devicetree/bindings/pwm/pwm-st.txt | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-st.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-st.txt b/Documentation/devicetree/bindings/pwm/pwm-st.txt new file mode 100644 index 000000000000..84d2fb807d3c --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-st.txt @@ -0,0 +1,41 @@ +STMicroelectronics PWM driver bindings +-------------------------------------- + +Required parameters: +- compatible : "st,pwm" +- #pwm-cells : Number of cells used to specify a PWM. First cell + specifies the per-chip index of the PWM to use and the + second cell is the period in nanoseconds - fixed to 2 + for STiH41x. +- reg : Physical base address and length of the controller's + registers. +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes + for PWM module. + For Pinctrl properties, please refer to [1]. +- clock-names: Set to "pwm". +- clocks: phandle of the clock used by the PWM module. + For Clk properties, please refer to [2]. + +Optional properties: +- st,pwm-num-chan: Number of available channels. If not passed, the driver + will consider single channel by default. + +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +[2] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Example: + +pwm1: pwm@fe510000 { + compatible = "st,pwm"; + reg = <0xfe510000 0x68>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1_chan0_default + &pinctrl_pwm1_chan1_default + &pinctrl_pwm1_chan2_default + &pinctrl_pwm1_chan3_default>; + clocks = <&clk_sysin>; + clock-names = "pwm"; + st,pwm-num-chan = <4>; +}; From bf9cc80b6c3ec2754b570d377ed7f7e2ec96868a Mon Sep 17 00:00:00 2001 From: Ajit Pal Singh Date: Mon, 14 Jul 2014 15:33:29 +0100 Subject: [PATCH 08/13] pwm: sti: Fix PWM prescaler handling This patch fixes the pwm driver to write the complete 8 bits of the prescaler value to the PWM Control register. Signed-off-by: Ajit Pal Singh Signed-off-by: Lee Jones Signed-off-by: Thierry Reding --- drivers/pwm/pwm-sti.c | 38 +++++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c index 0b714e45e5c0..76346e32f403 100644 --- a/drivers/pwm/pwm-sti.c +++ b/drivers/pwm/pwm-sti.c @@ -25,10 +25,13 @@ #define STI_DS_REG(ch) (4 * (ch)) /* Channel's Duty Cycle register */ #define STI_PWMCR 0x50 /* Control/Config register */ #define STI_INTEN 0x54 /* Interrupt Enable/Disable register */ +#define PWM_PRESCALE_LOW_MASK 0x0f +#define PWM_PRESCALE_HIGH_MASK 0xf0 /* Regfield IDs */ enum { - PWMCLK_PRESCALE, + PWMCLK_PRESCALE_LOW, + PWMCLK_PRESCALE_HIGH, PWM_EN, PWM_INT_EN, @@ -49,7 +52,8 @@ struct sti_pwm_chip { unsigned long clk_rate; struct regmap *regmap; struct sti_pwm_compat_data *cdata; - struct regmap_field *prescale; + struct regmap_field *prescale_low; + struct regmap_field *prescale_high; struct regmap_field *pwm_en; struct regmap_field *pwm_int_en; unsigned long *pwm_periods; @@ -58,7 +62,8 @@ struct sti_pwm_chip { }; static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = { - [PWMCLK_PRESCALE] = REG_FIELD(STI_PWMCR, 0, 3), + [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWMCR, 0, 3), + [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWMCR, 11, 14), [PWM_EN] = REG_FIELD(STI_PWMCR, 9, 9), [PWM_INT_EN] = REG_FIELD(STI_INTEN, 0, 0), }; @@ -109,10 +114,10 @@ static int sti_pwm_cmp_periods(const void *key, const void *elt) * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. * The only way to change the period (apart from changing the PWM input clock) * is to change the PWM clock prescaler. - * The prescaler is of 4 bits, so only 16 prescaler values and hence only - * 16 possible period values are supported (for a particular clock rate). + * The prescaler is of 8 bits, so 256 prescaler values and hence + * 256 possible period values are supported (for a particular clock rate). * The requested period will be applied only if it matches one of these - * 16 values. + * 256 values. */ static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) @@ -154,7 +159,13 @@ static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, if (ret) return ret; - ret = regmap_field_write(pc->prescale, prescale); + ret = regmap_field_write(pc->prescale_low, + prescale & PWM_PRESCALE_LOW_MASK); + if (ret) + goto clk_dis; + + ret = regmap_field_write(pc->prescale_high, + (prescale & PWM_PRESCALE_HIGH_MASK) >> 4); if (ret) goto clk_dis; @@ -222,10 +233,15 @@ static int sti_pwm_probe_dt(struct sti_pwm_chip *pc) reg_fields = cdata->reg_fields; - pc->prescale = devm_regmap_field_alloc(dev, pc->regmap, - reg_fields[PWMCLK_PRESCALE]); - if (IS_ERR(pc->prescale)) - return PTR_ERR(pc->prescale); + pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap, + reg_fields[PWMCLK_PRESCALE_LOW]); + if (IS_ERR(pc->prescale_low)) + return PTR_ERR(pc->prescale_low); + + pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap, + reg_fields[PWMCLK_PRESCALE_HIGH]); + if (IS_ERR(pc->prescale_high)) + return PTR_ERR(pc->prescale_high); pc->pwm_en = devm_regmap_field_alloc(dev, pc->regmap, reg_fields[PWM_EN]); From 5165166e8a1551fb80afa5fdaad6f2ea34d92285 Mon Sep 17 00:00:00 2001 From: Ajit Pal Singh Date: Mon, 14 Jul 2014 15:33:30 +0100 Subject: [PATCH 09/13] pwm: sti: Ensure same period values for all channels ST PWM IP shares the same clock prescaler across all the PWM channels. Hence configuration requests which change the period will affect all the channels. Do not allow period changes which will stomp period settings of the already configured channels. Signed-off-by: Ajit Pal Singh Signed-off-by: Lee Jones Signed-off-by: Thierry Reding --- drivers/pwm/pwm-sti.c | 138 +++++++++++++++++++++++++++++------------- 1 file changed, 95 insertions(+), 43 deletions(-) diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c index 76346e32f403..2d3260571b5a 100644 --- a/drivers/pwm/pwm-sti.c +++ b/drivers/pwm/pwm-sti.c @@ -58,6 +58,7 @@ struct sti_pwm_chip { struct regmap_field *pwm_int_en; unsigned long *pwm_periods; struct pwm_chip chip; + struct pwm_device *cur; void __iomem *mmio; }; @@ -99,6 +100,24 @@ static void sti_pwm_calc_periods(struct sti_pwm_chip *pc) } } +/* Calculate the number of PWM devices configured with a period. */ +static unsigned int sti_pwm_count_configured(struct pwm_chip *chip) +{ + struct pwm_device *pwm; + unsigned int ncfg = 0; + unsigned int i; + + for (i = 0; i < chip->npwm; i++) { + pwm = &chip->pwms[i]; + if (test_bit(PWMF_REQUESTED, &pwm->flags)) { + if (pwm_get_period(pwm)) + ncfg++; + } + } + + return ncfg; +} + static int sti_pwm_cmp_periods(const void *key, const void *elt) { unsigned long i = *(unsigned long *)key; @@ -124,57 +143,90 @@ static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, { struct sti_pwm_chip *pc = to_sti_pwmchip(chip); struct sti_pwm_compat_data *cdata = pc->cdata; + struct pwm_device *cur = pc->cur; struct device *dev = pc->dev; - unsigned int prescale, pwmvalx; + unsigned int prescale = 0, pwmvalx; unsigned long *found; int ret; + unsigned int ncfg; + bool period_same = false; - /* - * Search for matching period value. The corresponding index is our - * prescale value + ncfg = sti_pwm_count_configured(chip); + if (ncfg) + period_same = (period_ns == pwm_get_period(cur)); + + /* Allow configuration changes if one of the + * following conditions satisfy. + * 1. No channels have been configured. + * 2. Only one channel has been configured and the new request + * is for the same channel. + * 3. Only one channel has been configured and the new request is + * for a new channel and period of the new channel is same as + * the current configured period. + * 4. More than one channels are configured and period of the new + * requestis the same as the current period. */ - found = bsearch(&period_ns, &pc->pwm_periods[0], - cdata->max_prescale + 1, sizeof(unsigned long), - sti_pwm_cmp_periods); - if (!found) { - dev_err(dev, "failed to find matching period\n"); + if (!ncfg || + ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) || + ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) || + ((ncfg > 1) && period_same)) { + /* Enable clock before writing to PWM registers. */ + ret = clk_enable(pc->clk); + if (ret) + return ret; + + if (!period_same) { + /* + * Search for matching period value. + * The corresponding index is our prescale value. + */ + found = bsearch(&period_ns, &pc->pwm_periods[0], + cdata->max_prescale + 1, + sizeof(unsigned long), + sti_pwm_cmp_periods); + if (!found) { + dev_err(dev, + "failed to find matching period\n"); + ret = -EINVAL; + goto clk_dis; + } + prescale = found - &pc->pwm_periods[0]; + + ret = + regmap_field_write(pc->prescale_low, + prescale & PWM_PRESCALE_LOW_MASK); + if (ret) + goto clk_dis; + + ret = + regmap_field_write(pc->prescale_high, + (prescale & PWM_PRESCALE_HIGH_MASK) >> 4); + if (ret) + goto clk_dis; + } + + /* + * When PWMVal == 0, PWM pulse = 1 local clock cycle. + * When PWMVal == max_pwm_count, + * PWM pulse = (max_pwm_count + 1) local cycles, + * that is continuous pulse: signal never goes low. + */ + pwmvalx = cdata->max_pwm_cnt * duty_ns / period_ns; + + ret = regmap_write(pc->regmap, STI_DS_REG(pwm->hwpwm), pwmvalx); + if (ret) + goto clk_dis; + + ret = regmap_field_write(pc->pwm_int_en, 0); + + pc->cur = pwm; + + dev_dbg(dev, "prescale:%u, period:%i, duty:%i, pwmvalx:%u\n", + prescale, period_ns, duty_ns, pwmvalx); + } else { return -EINVAL; } - prescale = found - &pc->pwm_periods[0]; - - /* - * When PWMVal == 0, PWM pulse = 1 local clock cycle. - * When PWMVal == max_pwm_count, - * PWM pulse = (max_pwm_count + 1) local cycles, - * that is continuous pulse: signal never goes low. - */ - pwmvalx = cdata->max_pwm_cnt * duty_ns / period_ns; - - dev_dbg(dev, "prescale:%u, period:%i, duty:%i, pwmvalx:%u\n", - prescale, period_ns, duty_ns, pwmvalx); - - /* Enable clock before writing to PWM registers */ - ret = clk_enable(pc->clk); - if (ret) - return ret; - - ret = regmap_field_write(pc->prescale_low, - prescale & PWM_PRESCALE_LOW_MASK); - if (ret) - goto clk_dis; - - ret = regmap_field_write(pc->prescale_high, - (prescale & PWM_PRESCALE_HIGH_MASK) >> 4); - if (ret) - goto clk_dis; - - ret = regmap_write(pc->regmap, STI_PWMVAL(pwm->hwpwm), pwmvalx); - if (ret) - goto clk_dis; - - ret = regmap_field_write(pc->pwm_int_en, 0); - clk_dis: clk_disable(pc->clk); return ret; From 6ad6b838e11d8d67950716e0715b1d71bdd0769e Mon Sep 17 00:00:00 2001 From: Ajit Pal Singh Date: Mon, 14 Jul 2014 15:33:31 +0100 Subject: [PATCH 10/13] pwm: sti: Sync between enable/disable calls ST PWM IP has a common enable/disable control for all the PWM channels on a PWM cell. Disables PWM output on the PWM HW only when disable is called for the last channel. Signed-off-by: Ajit Pal Singh Signed-off-by: Lee Jones Signed-off-by: Thierry Reding --- drivers/pwm/pwm-sti.c | 44 +++++++++++++++++++++++++++++-------------- 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c index 2d3260571b5a..f98afe4906fb 100644 --- a/drivers/pwm/pwm-sti.c +++ b/drivers/pwm/pwm-sti.c @@ -59,6 +59,8 @@ struct sti_pwm_chip { unsigned long *pwm_periods; struct pwm_chip chip; struct pwm_device *cur; + unsigned int en_count; + struct mutex sti_pwm_lock; /* To sync between enable/disable calls */ void __iomem *mmio; }; @@ -236,32 +238,44 @@ static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { struct sti_pwm_chip *pc = to_sti_pwmchip(chip); struct device *dev = pc->dev; - int ret; + int ret = 0; - ret = clk_enable(pc->clk); - if (ret) - return ret; - - ret = regmap_field_write(pc->pwm_en, 1); - if (ret) - dev_err(dev, "%s,pwm_en write failed\n", __func__); + /* + * Since we have a common enable for all PWM channels, + * do not enable if already enabled. + */ + mutex_lock(&pc->sti_pwm_lock); + if (!pc->en_count) { + ret = clk_enable(pc->clk); + if (ret) + goto out; + ret = regmap_field_write(pc->pwm_en, 1); + if (ret) { + dev_err(dev, "failed to enable PWM device:%d\n", + pwm->hwpwm); + goto out; + } + } + pc->en_count++; +out: + mutex_unlock(&pc->sti_pwm_lock); return ret; } static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct sti_pwm_chip *pc = to_sti_pwmchip(chip); - struct device *dev = pc->dev; - unsigned int val; + mutex_lock(&pc->sti_pwm_lock); + if (--pc->en_count) { + mutex_unlock(&pc->sti_pwm_lock); + return; + } regmap_field_write(pc->pwm_en, 0); - regmap_read(pc->regmap, STI_CNT, &val); - - dev_dbg(dev, "pwm counter :%u\n", val); - clk_disable(pc->clk); + mutex_unlock(&pc->sti_pwm_lock); } static const struct pwm_ops sti_pwm_ops = { @@ -352,6 +366,8 @@ static int sti_pwm_probe(struct platform_device *pdev) pc->cdata = cdata; pc->dev = dev; + pc->en_count = 0; + mutex_init(&pc->sti_pwm_lock); ret = sti_pwm_probe_dt(pc); if (ret) From 3aacd3e1879a5359ce1483b82c9cdd31ebb348b7 Mon Sep 17 00:00:00 2001 From: Ajit Pal Singh Date: Mon, 14 Jul 2014 15:33:32 +0100 Subject: [PATCH 11/13] pwm: sti: Remove PWM period table Removes the PWM period table. Instead the prescaler is computed from the period value passed in the config() function. Signed-off-by: Ajit Pal Singh Signed-off-by: Lee Jones Signed-off-by: Thierry Reding --- drivers/pwm/pwm-sti.c | 64 +++++++++++-------------------------------- 1 file changed, 16 insertions(+), 48 deletions(-) diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c index f98afe4906fb..b95115cdaea7 100644 --- a/drivers/pwm/pwm-sti.c +++ b/drivers/pwm/pwm-sti.c @@ -10,7 +10,6 @@ * (at your option) any later version. */ -#include #include #include #include @@ -56,7 +55,6 @@ struct sti_pwm_chip { struct regmap_field *prescale_high; struct regmap_field *pwm_en; struct regmap_field *pwm_int_en; - unsigned long *pwm_periods; struct pwm_chip chip; struct pwm_device *cur; unsigned int en_count; @@ -77,29 +75,31 @@ static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip) } /* - * Calculate the period values supported by the PWM for the - * current clock rate. + * Calculate the prescaler value corresponding to the period. */ -static void sti_pwm_calc_periods(struct sti_pwm_chip *pc) +static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period, + unsigned int *prescale) { struct sti_pwm_compat_data *cdata = pc->cdata; - struct device *dev = pc->dev; unsigned long val; - int i; + unsigned int ps; /* - * period_ns = (10^9 * (prescaler + 1) * (MAX_PWM_COUNT + 1)) / CLK_RATE + * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_count + 1)) - 1 */ val = NSEC_PER_SEC / pc->clk_rate; val *= cdata->max_pwm_cnt + 1; - dev_dbg(dev, "possible periods for clkrate[HZ]:%lu\n", pc->clk_rate); - - for (i = 0; i <= cdata->max_prescale; i++) { - pc->pwm_periods[i] = val * (i + 1); - dev_dbg(dev, "prescale:%d, period[ns]:%lu\n", - i, pc->pwm_periods[i]); + if (period % val) { + return -EINVAL; + } else { + ps = period / val - 1; + if (ps > cdata->max_prescale) + return -EINVAL; } + *prescale = ps; + + return 0; } /* Calculate the number of PWM devices configured with a period. */ @@ -120,17 +120,6 @@ static unsigned int sti_pwm_count_configured(struct pwm_chip *chip) return ncfg; } -static int sti_pwm_cmp_periods(const void *key, const void *elt) -{ - unsigned long i = *(unsigned long *)key; - unsigned long j = *(unsigned long *)elt; - - if (i < j) - return -1; - else - return i == j ? 0 : 1; -} - /* * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. * The only way to change the period (apart from changing the PWM input clock) @@ -148,7 +137,6 @@ static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_device *cur = pc->cur; struct device *dev = pc->dev; unsigned int prescale = 0, pwmvalx; - unsigned long *found; int ret; unsigned int ncfg; bool period_same = false; @@ -178,21 +166,9 @@ static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, return ret; if (!period_same) { - /* - * Search for matching period value. - * The corresponding index is our prescale value. - */ - found = bsearch(&period_ns, &pc->pwm_periods[0], - cdata->max_prescale + 1, - sizeof(unsigned long), - sti_pwm_cmp_periods); - if (!found) { - dev_err(dev, - "failed to find matching period\n"); - ret = -EINVAL; + ret = sti_pwm_get_prescale(pc, period_ns, &prescale); + if (ret) goto clk_dis; - } - prescale = found - &pc->pwm_periods[0]; ret = regmap_field_write(pc->prescale_low, @@ -373,12 +349,6 @@ static int sti_pwm_probe(struct platform_device *pdev) if (ret) return ret; - pc->pwm_periods = devm_kzalloc(dev, - sizeof(unsigned long) * (pc->cdata->max_prescale + 1), - GFP_KERNEL); - if (!pc->pwm_periods) - return -ENOMEM; - pc->clk = of_clk_get_by_name(dev->of_node, "pwm"); if (IS_ERR(pc->clk)) { dev_err(dev, "failed to get PWM clock\n"); @@ -397,8 +367,6 @@ static int sti_pwm_probe(struct platform_device *pdev) return ret; } - sti_pwm_calc_periods(pc); - pc->chip.dev = dev; pc->chip.ops = &sti_pwm_ops; pc->chip.base = -1; From 695d49d941387baa3b2f3f412845a25918e030d5 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Fri, 8 Aug 2014 15:28:48 +0800 Subject: [PATCH 12/13] pwm: rockchip: document RK3288 SoC compatible Document new compatible for PWM founding on RK3288 SoC Signed-off-by: Caesar Wang Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/pwm/pwm-rockchip.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt index 3182126189bf..d47d15a6a298 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt @@ -1,7 +1,10 @@ Rockchip PWM controller Required properties: - - compatible: should be "rockchip,rk2928-pwm" + - compatible: should be "rockchip,-pwm" + "rockchip,rk2928-pwm": found on RK29XX,RK3066 and RK3188 SoCs + "rockchip,rk3288-pwm": found on RK3288 SoC + "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC - reg: physical base address and length of the controller's registers - clocks: phandle and clock specifier of the PWM reference clock - #pwm-cells: should be 2. See pwm.txt in this directory for a From f6306299080bbb1a77ad39494203f5397a5c2630 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Fri, 8 Aug 2014 15:28:49 +0800 Subject: [PATCH 13/13] pwm: rockchip: Added to support for RK3288 SoC This patch added to support the PWM controller found on RK3288 SoC. Signed-off-by: Caesar Wang Signed-off-by: Thierry Reding --- drivers/pwm/pwm-rockchip.c | 135 ++++++++++++++++++++++++++++++------- 1 file changed, 111 insertions(+), 24 deletions(-) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index eec214568193..bdd8644c01cf 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -2,6 +2,7 @@ * PWM driver for Rockchip SoCs * * Copyright (C) 2014 Beniamino Galvani + * Copyright (C) 2014 ROCKCHIP, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -12,30 +13,81 @@ #include #include #include +#include #include #include #include -#define PWM_CNTR 0x00 /* Counter register */ -#define PWM_HRC 0x04 /* High reference register */ -#define PWM_LRC 0x08 /* Low reference register */ -#define PWM_CTRL 0x0c /* Control register */ #define PWM_CTRL_TIMER_EN (1 << 0) #define PWM_CTRL_OUTPUT_EN (1 << 3) -#define PRESCALER 2 +#define PWM_ENABLE (1 << 0) +#define PWM_CONTINUOUS (1 << 1) +#define PWM_DUTY_POSITIVE (1 << 3) +#define PWM_INACTIVE_NEGATIVE (0 << 4) +#define PWM_OUTPUT_LEFT (0 << 5) +#define PWM_LP_DISABLE (0 << 8) struct rockchip_pwm_chip { struct pwm_chip chip; struct clk *clk; + const struct rockchip_pwm_data *data; void __iomem *base; }; +struct rockchip_pwm_regs { + unsigned long duty; + unsigned long period; + unsigned long cntr; + unsigned long ctrl; +}; + +struct rockchip_pwm_data { + struct rockchip_pwm_regs regs; + unsigned int prescaler; + + void (*set_enable)(struct pwm_chip *chip, bool enable); +}; + static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) { return container_of(c, struct rockchip_pwm_chip, chip); } +static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, bool enable) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; + u32 val; + + val = readl_relaxed(pc->base + pc->data->regs.ctrl); + + if (enable) + val |= enable_conf; + else + val &= ~enable_conf; + + writel_relaxed(val, pc->base + pc->data->regs.ctrl); +} + +static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, bool enable) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | + PWM_CONTINUOUS | PWM_DUTY_POSITIVE | + PWM_INACTIVE_NEGATIVE; + u32 val; + + val = readl_relaxed(pc->base + pc->data->regs.ctrl); + + if (enable) + val |= enable_conf; + else + val &= ~enable_conf; + + writel_relaxed(val, pc->base + pc->data->regs.ctrl); +} + static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { @@ -52,20 +104,20 @@ static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * default prescaler value for all practical clock rate values. */ div = clk_rate * period_ns; - do_div(div, PRESCALER * NSEC_PER_SEC); + do_div(div, pc->data->prescaler * NSEC_PER_SEC); period = div; div = clk_rate * duty_ns; - do_div(div, PRESCALER * NSEC_PER_SEC); + do_div(div, pc->data->prescaler * NSEC_PER_SEC); duty = div; ret = clk_enable(pc->clk); if (ret) return ret; - writel(period, pc->base + PWM_LRC); - writel(duty, pc->base + PWM_HRC); - writel(0, pc->base + PWM_CNTR); + writel(period, pc->base + pc->data->regs.period); + writel(duty, pc->base + pc->data->regs.duty); + writel(0, pc->base + pc->data->regs.cntr); clk_disable(pc->clk); @@ -76,15 +128,12 @@ static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); int ret; - u32 val; ret = clk_enable(pc->clk); if (ret) return ret; - val = readl_relaxed(pc->base + PWM_CTRL); - val |= PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; - writel_relaxed(val, pc->base + PWM_CTRL); + pc->data->set_enable(chip, true); return 0; } @@ -92,11 +141,8 @@ static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); - u32 val; - val = readl_relaxed(pc->base + PWM_CTRL); - val &= ~(PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN); - writel_relaxed(val, pc->base + PWM_CTRL); + pc->data->set_enable(chip, false); clk_disable(pc->clk); } @@ -108,12 +154,58 @@ static const struct pwm_ops rockchip_pwm_ops = { .owner = THIS_MODULE, }; +static const struct rockchip_pwm_data pwm_data_v1 = { + .regs = { + .duty = 0x04, + .period = 0x08, + .cntr = 0x00, + .ctrl = 0x0c, + }, + .prescaler = 2, + .set_enable = rockchip_pwm_set_enable_v1, +}; + +static const struct rockchip_pwm_data pwm_data_v2 = { + .regs = { + .duty = 0x08, + .period = 0x04, + .cntr = 0x00, + .ctrl = 0x0c, + }, + .prescaler = 1, + .set_enable = rockchip_pwm_set_enable_v2, +}; + +static const struct rockchip_pwm_data pwm_data_vop = { + .regs = { + .duty = 0x08, + .period = 0x04, + .cntr = 0x0c, + .ctrl = 0x00, + }, + .prescaler = 1, + .set_enable = rockchip_pwm_set_enable_v2, +}; + +static const struct of_device_id rockchip_pwm_dt_ids[] = { + { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, + { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, + { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); + static int rockchip_pwm_probe(struct platform_device *pdev) { + const struct of_device_id *id; struct rockchip_pwm_chip *pc; struct resource *r; int ret; + id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); + if (!id) + return -EINVAL; + pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); if (!pc) return -ENOMEM; @@ -133,6 +225,7 @@ static int rockchip_pwm_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pc); + pc->data = id->data; pc->chip.dev = &pdev->dev; pc->chip.ops = &rockchip_pwm_ops; pc->chip.base = -1; @@ -156,12 +249,6 @@ static int rockchip_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&pc->chip); } -static const struct of_device_id rockchip_pwm_dt_ids[] = { - { .compatible = "rockchip,rk2928-pwm" }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); - static struct platform_driver rockchip_pwm_driver = { .driver = { .name = "rockchip-pwm",