x86/boot/compressed: Enable 5-level paging during decompression stage
We need to cover two basic cases: when bootloader left us in 32-bit mode and when bootloader enabled long mode. The patch implements unified codepath to enabled 5-level paging for both cases. It means case when we start in 32-bit mode, we first enable long mode with 4-level and then switch over to 5-level paging. Switching from 4-level to 5-level paging is not trivial. We cannot do it directly. Setting LA57 in long mode would trigger #GP. So we need to switch off long mode first and the then re-enable with 5-level paging. NOTE: The need of switching off long mode means we are in trouble if bootloader put us above 4G boundary. If bootloader wants to boot 5-level paging kernel, it has to put kernel below 4G or enable 5-level paging on it's own, so we could avoid the step. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-arch@vger.kernel.org Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/20170606113133.22974-7-kirill.shutemov@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Коммит
34bbb0009f
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@ -346,6 +346,48 @@ preferred_addr:
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/* Set up the stack */
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leaq boot_stack_end(%rbx), %rsp
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#ifdef CONFIG_X86_5LEVEL
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/* Check if 5-level paging has already enabled */
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movq %cr4, %rax
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testl $X86_CR4_LA57, %eax
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jnz lvl5
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/*
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* At this point we are in long mode with 4-level paging enabled,
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* but we want to enable 5-level paging.
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*
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* The problem is that we cannot do it directly. Setting LA57 in
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* long mode would trigger #GP. So we need to switch off long mode
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* first.
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*
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* NOTE: This is not going to work if bootloader put us above 4G
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* limit.
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*
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* The first step is go into compatibility mode.
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*/
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/* Clear additional page table */
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leaq lvl5_pgtable(%rbx), %rdi
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xorq %rax, %rax
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movq $(PAGE_SIZE/8), %rcx
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rep stosq
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/*
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* Setup current CR3 as the first and only entry in a new top level
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* page table.
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*/
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movq %cr3, %rdi
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leaq 0x7 (%rdi), %rax
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movq %rax, lvl5_pgtable(%rbx)
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/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */
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pushq $__KERNEL32_CS
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leaq compatible_mode(%rip), %rax
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pushq %rax
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lretq
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lvl5:
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#endif
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/* Zero EFLAGS */
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pushq $0
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popfq
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@ -429,6 +471,44 @@ relocated:
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jmp *%rax
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.code32
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#ifdef CONFIG_X86_5LEVEL
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compatible_mode:
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/* Setup data and stack segments */
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movl $__KERNEL_DS, %eax
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movl %eax, %ds
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movl %eax, %ss
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/* Disable paging */
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movl %cr0, %eax
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btrl $X86_CR0_PG_BIT, %eax
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movl %eax, %cr0
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/* Point CR3 to 5-level paging */
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leal lvl5_pgtable(%ebx), %eax
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movl %eax, %cr3
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/* Enable PAE and LA57 mode */
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movl %cr4, %eax
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orl $(X86_CR4_PAE | X86_CR4_LA57), %eax
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movl %eax, %cr4
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/* Calculate address we are running at */
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call 1f
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1: popl %edi
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subl $1b, %edi
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/* Prepare stack for far return to Long Mode */
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pushl $__KERNEL_CS
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leal lvl5(%edi), %eax
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push %eax
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/* Enable paging back */
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movl $(X86_CR0_PG | X86_CR0_PE), %eax
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movl %eax, %cr0
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lret
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#endif
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no_longmode:
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/* This isn't an x86-64 CPU so hang */
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1:
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@ -442,7 +522,7 @@ gdt:
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.word gdt_end - gdt
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.long gdt
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.word 0
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.quad 0x0000000000000000 /* NULL descriptor */
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.quad 0x00cf9a000000ffff /* __KERNEL32_CS */
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.quad 0x00af9a000000ffff /* __KERNEL_CS */
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.quad 0x00cf92000000ffff /* __KERNEL_DS */
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.quad 0x0080890000000000 /* TS descriptor */
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@ -486,3 +566,7 @@ boot_stack_end:
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.balign 4096
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pgtable:
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.fill BOOT_PGT_SIZE, 1, 0
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#ifdef CONFIG_X86_5LEVEL
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lvl5_pgtable:
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.fill PAGE_SIZE, 1, 0
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#endif
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