Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
drm/vmwgfx: Fix queries if no dma buffer thrashing is occuring.
drm/nv50: fix vram ptes on IGPs to point at stolen system memory
drm/nv50: fix instmem binding on IGPs to point at stolen system memory
drm/nv50: improve vram page table construction
drm/nv50: more efficient clearing of gpu page table entries
drm/nv50: make nv50_mem_vm_{bind,unbind} operate only on vram
drm/nouveau: Fix up pre-nv17 analog load detection.
This commit is contained in:
Linus Torvalds
Коммит
34e3f91b4e
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@ -583,6 +583,7 @@ struct drm_nouveau_private {
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uint64_t vm_end;
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struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
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int vm_vram_pt_nr;
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uint64_t vram_sys_base;
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/* the mtrr covering the FB */
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int fb_mtrr;
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@ -285,53 +285,50 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
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uint32_t flags, uint64_t phys)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj **pgt;
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unsigned psz, pfl, pages;
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struct nouveau_gpuobj *pgt;
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unsigned block;
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int i;
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if (virt >= dev_priv->vm_gart_base &&
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(virt + size) < (dev_priv->vm_gart_base + dev_priv->vm_gart_size)) {
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psz = 12;
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pgt = &dev_priv->gart_info.sg_ctxdma;
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pfl = 0x21;
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virt -= dev_priv->vm_gart_base;
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} else
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if (virt >= dev_priv->vm_vram_base &&
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(virt + size) < (dev_priv->vm_vram_base + dev_priv->vm_vram_size)) {
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psz = 16;
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pgt = dev_priv->vm_vram_pt;
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pfl = 0x01;
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virt -= dev_priv->vm_vram_base;
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} else {
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NV_ERROR(dev, "Invalid address: 0x%16llx-0x%16llx\n",
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virt, virt + size - 1);
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return -EINVAL;
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virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
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size = (size >> 16) << 1;
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phys |= ((uint64_t)flags << 32);
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phys |= 1;
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if (dev_priv->vram_sys_base) {
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phys += dev_priv->vram_sys_base;
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phys |= 0x30;
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}
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pages = size >> psz;
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dev_priv->engine.instmem.prepare_access(dev, true);
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if (flags & 0x80000000) {
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while (pages--) {
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struct nouveau_gpuobj *pt = pgt[virt >> 29];
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unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
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while (size) {
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unsigned offset_h = upper_32_bits(phys);
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unsigned offset_l = lower_32_bits(phys);
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unsigned pte, end;
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nv_wo32(dev, pt, pte++, 0x00000000);
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nv_wo32(dev, pt, pte++, 0x00000000);
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virt += (1 << psz);
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for (i = 7; i >= 0; i--) {
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block = 1 << (i + 1);
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if (size >= block && !(virt & (block - 1)))
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break;
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}
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} else {
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while (pages--) {
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struct nouveau_gpuobj *pt = pgt[virt >> 29];
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unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
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unsigned offset_h = upper_32_bits(phys) & 0xff;
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unsigned offset_l = lower_32_bits(phys);
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offset_l |= (i << 7);
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nv_wo32(dev, pt, pte++, offset_l | pfl);
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nv_wo32(dev, pt, pte++, offset_h | flags);
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phys += block << 15;
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size -= block;
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phys += (1 << psz);
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virt += (1 << psz);
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while (block) {
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pgt = dev_priv->vm_vram_pt[virt >> 14];
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pte = virt & 0x3ffe;
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end = pte + block;
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if (end > 16384)
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end = 16384;
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block -= (end - pte);
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virt += (end - pte);
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while (pte < end) {
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nv_wo32(dev, pgt, pte++, offset_l);
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nv_wo32(dev, pgt, pte++, offset_h);
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}
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}
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}
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dev_priv->engine.instmem.finish_access(dev);
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@ -356,7 +353,41 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
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void
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nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
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{
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nv50_mem_vm_bind_linear(dev, virt, size, 0x80000000, 0);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *pgt;
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unsigned pages, pte, end;
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virt -= dev_priv->vm_vram_base;
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pages = (size >> 16) << 1;
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dev_priv->engine.instmem.prepare_access(dev, true);
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while (pages) {
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pgt = dev_priv->vm_vram_pt[virt >> 29];
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pte = (virt & 0x1ffe0000ULL) >> 15;
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end = pte + pages;
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if (end > 16384)
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end = 16384;
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pages -= (end - pte);
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virt += (end - pte) << 15;
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while (pte < end)
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nv_wo32(dev, pgt, pte++, 0);
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}
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dev_priv->engine.instmem.finish_access(dev);
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nv_wr32(dev, 0x100c80, 0x00050001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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return;
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}
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nv_wr32(dev, 0x100c80, 0x00000001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
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}
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}
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/*
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@ -119,7 +119,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
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struct drm_connector *connector)
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{
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struct drm_device *dev = encoder->dev;
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uint8_t saved_seq1, saved_pi, saved_rpc1;
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uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
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uint8_t saved_palette0[3], saved_palette_mask;
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uint32_t saved_rtest_ctrl, saved_rgen_ctrl;
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int i;
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@ -135,6 +135,9 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
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/* only implemented for head A for now */
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NVSetOwner(dev, 0);
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saved_cr_mode = NVReadVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX);
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NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode | 0x80);
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saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX);
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NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);
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@ -203,6 +206,7 @@ out:
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NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
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NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
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NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
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NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode);
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if (blue == 0x18) {
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NV_INFO(dev, "Load detected on head A\n");
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@ -76,6 +76,11 @@ nv50_instmem_init(struct drm_device *dev)
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for (i = 0x1700; i <= 0x1710; i += 4)
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priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
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if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
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dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;
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else
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dev_priv->vram_sys_base = 0;
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/* Reserve the last MiB of VRAM, we should probably try to avoid
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* setting up the below tables over the top of the VBIOS image at
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* some point.
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@ -172,16 +177,28 @@ nv50_instmem_init(struct drm_device *dev)
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* We map the entire fake channel into the start of the PRAMIN BAR
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*/
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000,
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0, &priv->pramin_pt);
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0, &priv->pramin_pt);
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if (ret)
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return ret;
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for (i = 0, v = c_offset; i < pt_size; i += 8, v += 0x1000) {
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if (v < (c_offset + c_size))
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BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1);
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else
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BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009);
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v = c_offset | 1;
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if (dev_priv->vram_sys_base) {
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v += dev_priv->vram_sys_base;
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v |= 0x30;
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}
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i = 0;
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while (v < dev_priv->vram_sys_base + c_offset + c_size) {
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BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v);
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BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
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v += 0x1000;
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i += 8;
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}
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while (i < pt_size) {
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BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000000);
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BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
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i += 8;
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}
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BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
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@ -416,7 +433,9 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
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uint32_t pte, pte_end, vram;
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struct nouveau_gpuobj *pramin_pt = priv->pramin_pt->gpuobj;
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uint32_t pte, pte_end;
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uint64_t vram;
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if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
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return -EINVAL;
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@ -424,20 +443,24 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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NV_DEBUG(dev, "st=0x%0llx sz=0x%0llx\n",
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gpuobj->im_pramin->start, gpuobj->im_pramin->size);
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pte = (gpuobj->im_pramin->start >> 12) << 3;
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pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
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pte = (gpuobj->im_pramin->start >> 12) << 1;
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pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
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vram = gpuobj->im_backing_start;
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NV_DEBUG(dev, "pramin=0x%llx, pte=%d, pte_end=%d\n",
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gpuobj->im_pramin->start, pte, pte_end);
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NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
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vram |= 1;
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if (dev_priv->vram_sys_base) {
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vram += dev_priv->vram_sys_base;
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vram |= 0x30;
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}
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dev_priv->engine.instmem.prepare_access(dev, true);
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while (pte < pte_end) {
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nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1);
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nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
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pte += 8;
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nv_wo32(dev, pramin_pt, pte++, lower_32_bits(vram));
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nv_wo32(dev, pramin_pt, pte++, upper_32_bits(vram));
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vram += NV50_INSTMEM_PAGE_SIZE;
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}
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dev_priv->engine.instmem.finish_access(dev);
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@ -470,14 +493,13 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
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if (gpuobj->im_bound == 0)
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return -EINVAL;
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||||
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pte = (gpuobj->im_pramin->start >> 12) << 3;
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pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
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pte = (gpuobj->im_pramin->start >> 12) << 1;
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pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
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||||
|
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dev_priv->engine.instmem.prepare_access(dev, true);
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while (pte < pte_end) {
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nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009);
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nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
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pte += 8;
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nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
|
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nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
|
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}
|
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dev_priv->engine.instmem.finish_access(dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -182,25 +182,19 @@ static int vmw_cmd_present_check(struct vmw_private *dev_priv,
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return vmw_cmd_sid_check(dev_priv, sw_context, &cmd->body.sid);
|
||||
}
|
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|
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static int vmw_cmd_dma(struct vmw_private *dev_priv,
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struct vmw_sw_context *sw_context,
|
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SVGA3dCmdHeader *header)
|
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static int vmw_translate_guest_ptr(struct vmw_private *dev_priv,
|
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struct vmw_sw_context *sw_context,
|
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SVGAGuestPtr *ptr,
|
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struct vmw_dma_buffer **vmw_bo_p)
|
||||
{
|
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uint32_t handle;
|
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struct vmw_dma_buffer *vmw_bo = NULL;
|
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struct ttm_buffer_object *bo;
|
||||
struct vmw_surface *srf = NULL;
|
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struct vmw_dma_cmd {
|
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SVGA3dCmdHeader header;
|
||||
SVGA3dCmdSurfaceDMA dma;
|
||||
} *cmd;
|
||||
uint32_t handle = ptr->gmrId;
|
||||
struct vmw_relocation *reloc;
|
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int ret;
|
||||
uint32_t cur_validate_node;
|
||||
struct ttm_validate_buffer *val_buf;
|
||||
int ret;
|
||||
|
||||
cmd = container_of(header, struct vmw_dma_cmd, header);
|
||||
handle = cmd->dma.guest.ptr.gmrId;
|
||||
ret = vmw_user_dmabuf_lookup(sw_context->tfile, handle, &vmw_bo);
|
||||
if (unlikely(ret != 0)) {
|
||||
DRM_ERROR("Could not find or use GMR region.\n");
|
||||
|
|
@ -209,14 +203,14 @@ static int vmw_cmd_dma(struct vmw_private *dev_priv,
|
|||
bo = &vmw_bo->base;
|
||||
|
||||
if (unlikely(sw_context->cur_reloc >= VMWGFX_MAX_RELOCATIONS)) {
|
||||
DRM_ERROR("Max number of DMA commands per submission"
|
||||
DRM_ERROR("Max number relocations per submission"
|
||||
" exceeded\n");
|
||||
ret = -EINVAL;
|
||||
goto out_no_reloc;
|
||||
}
|
||||
|
||||
reloc = &sw_context->relocs[sw_context->cur_reloc++];
|
||||
reloc->location = &cmd->dma.guest.ptr;
|
||||
reloc->location = ptr;
|
||||
|
||||
cur_validate_node = vmw_dmabuf_validate_node(bo, sw_context->cur_val_buf);
|
||||
if (unlikely(cur_validate_node >= VMWGFX_MAX_GMRS)) {
|
||||
|
|
@ -234,7 +228,89 @@ static int vmw_cmd_dma(struct vmw_private *dev_priv,
|
|||
list_add_tail(&val_buf->head, &sw_context->validate_nodes);
|
||||
++sw_context->cur_val_buf;
|
||||
}
|
||||
*vmw_bo_p = vmw_bo;
|
||||
return 0;
|
||||
|
||||
out_no_reloc:
|
||||
vmw_dmabuf_unreference(&vmw_bo);
|
||||
vmw_bo_p = NULL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int vmw_cmd_end_query(struct vmw_private *dev_priv,
|
||||
struct vmw_sw_context *sw_context,
|
||||
SVGA3dCmdHeader *header)
|
||||
{
|
||||
struct vmw_dma_buffer *vmw_bo;
|
||||
struct vmw_query_cmd {
|
||||
SVGA3dCmdHeader header;
|
||||
SVGA3dCmdEndQuery q;
|
||||
} *cmd;
|
||||
int ret;
|
||||
|
||||
cmd = container_of(header, struct vmw_query_cmd, header);
|
||||
ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
|
||||
if (unlikely(ret != 0))
|
||||
return ret;
|
||||
|
||||
ret = vmw_translate_guest_ptr(dev_priv, sw_context,
|
||||
&cmd->q.guestResult,
|
||||
&vmw_bo);
|
||||
if (unlikely(ret != 0))
|
||||
return ret;
|
||||
|
||||
vmw_dmabuf_unreference(&vmw_bo);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vmw_cmd_wait_query(struct vmw_private *dev_priv,
|
||||
struct vmw_sw_context *sw_context,
|
||||
SVGA3dCmdHeader *header)
|
||||
{
|
||||
struct vmw_dma_buffer *vmw_bo;
|
||||
struct vmw_query_cmd {
|
||||
SVGA3dCmdHeader header;
|
||||
SVGA3dCmdWaitForQuery q;
|
||||
} *cmd;
|
||||
int ret;
|
||||
|
||||
cmd = container_of(header, struct vmw_query_cmd, header);
|
||||
ret = vmw_cmd_cid_check(dev_priv, sw_context, header);
|
||||
if (unlikely(ret != 0))
|
||||
return ret;
|
||||
|
||||
ret = vmw_translate_guest_ptr(dev_priv, sw_context,
|
||||
&cmd->q.guestResult,
|
||||
&vmw_bo);
|
||||
if (unlikely(ret != 0))
|
||||
return ret;
|
||||
|
||||
vmw_dmabuf_unreference(&vmw_bo);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int vmw_cmd_dma(struct vmw_private *dev_priv,
|
||||
struct vmw_sw_context *sw_context,
|
||||
SVGA3dCmdHeader *header)
|
||||
{
|
||||
struct vmw_dma_buffer *vmw_bo = NULL;
|
||||
struct ttm_buffer_object *bo;
|
||||
struct vmw_surface *srf = NULL;
|
||||
struct vmw_dma_cmd {
|
||||
SVGA3dCmdHeader header;
|
||||
SVGA3dCmdSurfaceDMA dma;
|
||||
} *cmd;
|
||||
int ret;
|
||||
|
||||
cmd = container_of(header, struct vmw_dma_cmd, header);
|
||||
ret = vmw_translate_guest_ptr(dev_priv, sw_context,
|
||||
&cmd->dma.guest.ptr,
|
||||
&vmw_bo);
|
||||
if (unlikely(ret != 0))
|
||||
return ret;
|
||||
|
||||
bo = &vmw_bo->base;
|
||||
ret = vmw_user_surface_lookup_handle(dev_priv, sw_context->tfile,
|
||||
cmd->dma.host.sid, &srf);
|
||||
if (ret) {
|
||||
|
|
@ -379,8 +455,8 @@ static vmw_cmd_func vmw_cmd_funcs[SVGA_3D_CMD_MAX] = {
|
|||
VMW_CMD_DEF(SVGA_3D_CMD_DRAW_PRIMITIVES, &vmw_cmd_draw),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_SETSCISSORRECT, &vmw_cmd_cid_check),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_BEGIN_QUERY, &vmw_cmd_cid_check),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_cid_check),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_QUERY, &vmw_cmd_cid_check),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_END_QUERY, &vmw_cmd_end_query),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_WAIT_FOR_QUERY, &vmw_cmd_wait_query),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_PRESENT_READBACK, &vmw_cmd_ok),
|
||||
VMW_CMD_DEF(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN,
|
||||
&vmw_cmd_blt_surf_screen_check)
|
||||
|
|
|
|||
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