ARM: imx51/53: add sdhc3/4 clock
Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Richard Zhu
Sascha Hauer
Родитель
a77dd2aa92
Коммит
359219025e
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@ -42,6 +42,9 @@ static struct clk usboh3_clk;
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static struct clk emi_fast_clk;
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static struct clk ipu_clk;
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static struct clk mipi_hsc1_clk;
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static struct clk esdhc1_clk;
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static struct clk esdhc2_clk;
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static struct clk esdhc3_mx53_clk;
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#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
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@ -1143,10 +1146,80 @@ CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
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CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
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CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
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/* mx51 specific */
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CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
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CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
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CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
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static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CSCMR1);
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if (parent == &esdhc1_clk)
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reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
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else if (parent == &esdhc2_clk)
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reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
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else
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return -EINVAL;
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__raw_writel(reg, MXC_CCM_CSCMR1);
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return 0;
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}
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static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CSCMR1);
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if (parent == &esdhc1_clk)
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reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
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else if (parent == &esdhc2_clk)
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reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
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else
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return -EINVAL;
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__raw_writel(reg, MXC_CCM_CSCMR1);
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return 0;
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}
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/* mx53 specific */
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static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CSCMR1);
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if (parent == &esdhc1_clk)
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reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
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else if (parent == &esdhc3_mx53_clk)
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reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
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else
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return -EINVAL;
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__raw_writel(reg, MXC_CCM_CSCMR1);
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return 0;
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}
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CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
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CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
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CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
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static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 reg;
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reg = __raw_readl(MXC_CCM_CSCMR1);
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if (parent == &esdhc1_clk)
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reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
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else if (parent == &esdhc3_mx53_clk)
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reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
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else
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return -EINVAL;
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__raw_writel(reg, MXC_CCM_CSCMR1);
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return 0;
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}
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#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
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static struct clk name = { \
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.id = i, \
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@ -1251,9 +1324,62 @@ DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
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clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
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DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
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NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
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DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
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NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
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DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
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NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
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/* mx51 specific */
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DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
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clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
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static struct clk esdhc3_clk = {
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.id = 2,
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.parent = &esdhc1_clk,
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.set_parent = clk_esdhc3_set_parent,
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.enable_reg = MXC_CCM_CCGR3,
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.enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
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.enable = _clk_max_enable,
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.disable = _clk_max_disable,
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.secondary = &esdhc3_ipg_clk,
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};
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static struct clk esdhc4_clk = {
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.id = 3,
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.parent = &esdhc1_clk,
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.set_parent = clk_esdhc4_set_parent,
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.enable_reg = MXC_CCM_CCGR3,
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.enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
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.enable = _clk_max_enable,
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.disable = _clk_max_disable,
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.secondary = &esdhc4_ipg_clk,
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};
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/* mx53 specific */
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static struct clk esdhc2_mx53_clk = {
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.id = 2,
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.parent = &esdhc1_clk,
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.set_parent = clk_esdhc2_mx53_set_parent,
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.enable_reg = MXC_CCM_CCGR3,
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.enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
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.enable = _clk_max_enable,
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.disable = _clk_max_disable,
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.secondary = &esdhc3_ipg_clk,
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};
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DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
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clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
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static struct clk esdhc4_mx53_clk = {
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.id = 3,
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.parent = &esdhc1_clk,
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.set_parent = clk_esdhc4_mx53_set_parent,
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.enable_reg = MXC_CCM_CCGR3,
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.enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
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.enable = _clk_max_enable,
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.disable = _clk_max_disable,
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.secondary = &esdhc4_ipg_clk,
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};
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DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
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DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
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DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
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@ -1312,6 +1438,8 @@ static struct clk_lookup mx51_lookups[] = {
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_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk)
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_REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
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_REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
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_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
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@ -1332,7 +1460,9 @@ static struct clk_lookup mx53_lookups[] = {
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_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
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_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
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_REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
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_REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
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_REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
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_REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
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@ -1425,6 +1555,14 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
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mx53_revision();
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clk_disable(&iim_clk);
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/* Set SDHC parents to be PLL2 */
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clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
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clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
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/* set SDHC root clock as 200MHZ*/
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clk_set_rate(&esdhc1_clk, 200000000);
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clk_set_rate(&esdhc3_mx53_clk, 200000000);
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/* System timer */
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mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
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MX53_INT_GPT);
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@ -217,9 +217,12 @@
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#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
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#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
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#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
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#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
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#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
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#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
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#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
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#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
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#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
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#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
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@ -271,6 +274,10 @@
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
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#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
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#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
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#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
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#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
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#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
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