brcmfmac: add support for CYW43012 SDIO chipset
CYW43012 is a 1x1 802.11a/b/g/n Dual-Band HT20, 256-QAM/Turbo QAM. It is an Ultra Low Power WLAN+BT combo chip. Reviewed-by: Arend van Spriel <arend.vanspriel@broadcom.com> Signed-off-by: Chi-Hsien Lin <chi-hsien.lin@cypress.com> Signed-off-by: Praveen Babu C <praveen.chandran@cypress.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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Родитель
58e4bbea0c
Коммит
35cb51b216
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@ -983,6 +983,7 @@ static const struct sdio_device_id brcmf_sdmmc_ids[] = {
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BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4354),
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BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4356),
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BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_CYPRESS_4373),
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BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_CYPRESS_43012),
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE(sdio, brcmf_sdmmc_ids);
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@ -165,6 +165,7 @@ struct sbconfig {
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#define SRCI_LSS_MASK 0x00f00000
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#define SRCI_LSS_SHIFT 20
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#define SRCI_SRNB_MASK 0xf0
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#define SRCI_SRNB_MASK_EXT 0x100
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#define SRCI_SRNB_SHIFT 4
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#define SRCI_SRBSZ_MASK 0xf
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#define SRCI_SRBSZ_SHIFT 0
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@ -592,7 +593,13 @@ static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
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if (lss != 0)
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*ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
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} else {
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nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
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/* length of SRAM Banks increased for corerev greater than 23 */
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if (sr->pub.rev >= 23) {
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nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT))
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>> SRCI_SRNB_SHIFT;
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} else {
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nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
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}
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for (i = 0; i < nb; i++) {
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retent = brcmf_chip_socram_banksize(sr, i, &banksize);
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*ramsize += banksize;
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@ -1356,6 +1363,11 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
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addr = CORE_CC_REG(base, sr_control1);
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reg = chip->ops->read32(chip->ctx, addr);
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return reg != 0;
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case CY_CC_43012_CHIP_ID:
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addr = CORE_CC_REG(pmu->base, retention_ctl);
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reg = chip->ops->read32(chip->ctx, addr);
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return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
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PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
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default:
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addr = CORE_CC_REG(pmu->base, pmucapabilities_ext);
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reg = chip->ops->read32(chip->ctx, addr);
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@ -624,6 +624,7 @@ BRCMF_FW_DEF(43455, "brcmfmac43455-sdio");
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BRCMF_FW_DEF(4354, "brcmfmac4354-sdio");
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BRCMF_FW_DEF(4356, "brcmfmac4356-sdio");
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BRCMF_FW_DEF(4373, "brcmfmac4373-sdio");
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BRCMF_FW_DEF(43012, "brcmfmac43012-sdio");
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static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
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BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
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@ -643,7 +644,8 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
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BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
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BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
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BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
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BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373)
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BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373),
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BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012)
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};
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static void pkt_align(struct sk_buff *p, int len, int align)
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@ -677,6 +679,14 @@ brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
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/* 1st KSO write goes to AOS wake up core if device is asleep */
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brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err);
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/* In case of 43012 chip, the chip could go down immediately after
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* KSO bit is cleared. So the further reads of KSO register could
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* fail. Thereby just bailing out immediately after clearing KSO
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* bit, to avoid polling of KSO bit.
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*/
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if (!on && bus->ci->chip == CY_CC_43012_CHIP_ID)
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return err;
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if (on) {
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/* device WAKEUP through KSO:
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* write bit 0 & read back until
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@ -2402,6 +2412,14 @@ static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
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return ret;
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}
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static bool brcmf_chip_is_ulp(struct brcmf_chip *ci)
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{
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if (ci->chip == CY_CC_43012_CHIP_ID)
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return true;
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else
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return false;
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}
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static void brcmf_sdio_bus_stop(struct device *dev)
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{
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struct brcmf_bus *bus_if = dev_get_drvdata(dev);
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@ -2409,7 +2427,7 @@ static void brcmf_sdio_bus_stop(struct device *dev)
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struct brcmf_sdio *bus = sdiodev->bus;
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struct brcmf_core *core = bus->sdio_core;
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u32 local_hostintmask;
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u8 saveclk;
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u8 saveclk, bpreq;
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int err;
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brcmf_dbg(TRACE, "Enter\n");
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@ -2436,9 +2454,14 @@ static void brcmf_sdio_bus_stop(struct device *dev)
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/* Force backplane clocks to assure F2 interrupt propagates */
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saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
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&err);
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if (!err)
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brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
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(saveclk | SBSDIO_FORCE_HT), &err);
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if (!err) {
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bpreq = saveclk;
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bpreq |= brcmf_chip_is_ulp(bus->ci) ?
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SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT;
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brcmf_sdiod_writeb(sdiodev,
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SBSDIO_FUNC1_CHIPCLKCSR,
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bpreq, &err);
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}
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if (err)
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brcmf_err("Failed to force clock for F2: err %d\n",
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err);
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@ -3328,20 +3351,45 @@ err:
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return bcmerror;
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}
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static bool brcmf_sdio_aos_no_decode(struct brcmf_sdio *bus)
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{
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if (bus->ci->chip == CY_CC_43012_CHIP_ID)
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return true;
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else
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return false;
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}
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static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
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{
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int err = 0;
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u8 val;
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u8 wakeupctrl;
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u8 cardcap;
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u8 chipclkcsr;
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brcmf_dbg(TRACE, "Enter\n");
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if (brcmf_chip_is_ulp(bus->ci)) {
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wakeupctrl = SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT;
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chipclkcsr = SBSDIO_HT_AVAIL_REQ;
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} else {
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wakeupctrl = SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
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chipclkcsr = SBSDIO_FORCE_HT;
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}
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if (brcmf_sdio_aos_no_decode(bus)) {
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cardcap = SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC;
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} else {
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cardcap = (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
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SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT);
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}
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val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
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if (err) {
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brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
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return;
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}
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val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
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val |= 1 << wakeupctrl;
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brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
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if (err) {
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brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
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@ -3350,8 +3398,7 @@ static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
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/* Add CMD14 Support */
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brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
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(SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
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SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
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cardcap,
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&err);
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if (err) {
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brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
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@ -3359,7 +3406,7 @@ static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
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}
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brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
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SBSDIO_FORCE_HT, &err);
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chipclkcsr, &err);
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if (err) {
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brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
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return;
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@ -4051,7 +4098,7 @@ static void brcmf_sdio_firmware_callback(struct device *dev, int err,
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const struct firmware *code;
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void *nvram;
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u32 nvram_len;
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u8 saveclk;
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u8 saveclk, bpreq;
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u8 devctl;
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brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err);
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@ -4085,8 +4132,11 @@ static void brcmf_sdio_firmware_callback(struct device *dev, int err,
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/* Force clocks on backplane to be sure F2 interrupt propagates */
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saveclk = brcmf_sdiod_readb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, &err);
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if (!err) {
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bpreq = saveclk;
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bpreq |= brcmf_chip_is_ulp(bus->ci) ?
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SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT;
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brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR,
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(saveclk | SBSDIO_FORCE_HT), &err);
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bpreq, &err);
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}
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if (err) {
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brcmf_err("Failed to force clock for F2: err %d\n", err);
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@ -60,6 +60,7 @@
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#define BRCM_CC_43664_CHIP_ID 43664
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#define BRCM_CC_4371_CHIP_ID 0x4371
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#define CY_CC_4373_CHIP_ID 0x4373
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#define CY_CC_43012_CHIP_ID 43012
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/* USB Device IDs */
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#define BRCM_USB_43143_DEVICE_ID 0xbd1e
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@ -42,6 +42,7 @@
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#define SDIO_DEVICE_ID_BROADCOM_4354 0x4354
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#define SDIO_DEVICE_ID_BROADCOM_4356 0x4356
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#define SDIO_DEVICE_ID_CYPRESS_4373 0x4373
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#define SDIO_DEVICE_ID_CYPRESS_43012 43012
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#define SDIO_VENDOR_ID_INTEL 0x0089
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#define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX 0x1402
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