tty/serial: atmel: fix fractional baud rate computation

The problem with previous code was it rounded values in wrong
place and produced wrong baud rate in some cases.

Signed-off-by: Alexey Starikovskiy <aystarik@gmail.com>
[nicolas.ferre@atmel.com: port to newer kernel and add commit log]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alexey Starikovskiy 2016-09-21 12:44:14 +02:00 коммит произвёл Greg Kroah-Hartman
Родитель e98d413703
Коммит 36131cdfef
2 изменённых файлов: 7 добавлений и 4 удалений

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@ -2170,13 +2170,15 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
* accurately. This feature is enabled only when using normal mode. * accurately. This feature is enabled only when using normal mode.
* baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8)) * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
* Currently, OVER is always set to 0 so we get * Currently, OVER is always set to 0 so we get
* baudrate = selected clock (16 * (CD + FP / 8)) * baudrate = selected clock / (16 * (CD + FP / 8))
* then
* 8 CD + FP = selected clock / (2 * baudrate)
*/ */
if (atmel_port->has_frac_baudrate && if (atmel_port->has_frac_baudrate &&
(mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_NORMAL) { (mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_NORMAL) {
div = DIV_ROUND_CLOSEST(port->uartclk, baud); div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
cd = div / 16; cd = div >> 3;
fp = DIV_ROUND_CLOSEST(div % 16, 2); fp = div & ATMEL_US_FP_MASK;
} else { } else {
cd = uart_get_divisor(port, baud); cd = uart_get_divisor(port, baud);
} }

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@ -119,6 +119,7 @@
#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */ #define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
#define ATMEL_US_CD GENMASK(15, 0) /* Clock Divider */ #define ATMEL_US_CD GENMASK(15, 0) /* Clock Divider */
#define ATMEL_US_FP_OFFSET 16 /* Fractional Part */ #define ATMEL_US_FP_OFFSET 16 /* Fractional Part */
#define ATMEL_US_FP_MASK 0x7
#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register for USART */ #define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register for USART */
#define ATMEL_UA_RTOR 0x28 /* Receiver Time-out Register for UART */ #define ATMEL_UA_RTOR 0x28 /* Receiver Time-out Register for UART */