drm/i915: Move per ring error state to ring_error
v2: Moved num_requests up (Chris) Rebased on new hws page capture which required a rename since it made two members named, 'hws' in the per ring error state. (Ben) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ben Widawsky
Daniel Vetter
Родитель
585b028871
Коммит
362b8af7ad
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@ -313,48 +313,50 @@ struct drm_i915_error_state {
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struct intel_overlay_error_state *overlay;
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struct intel_display_error_state *display;
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/* Per ring register state
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* TODO: Move these to per ring */
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u32 tail[I915_NUM_RINGS];
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u32 head[I915_NUM_RINGS];
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u32 ctl[I915_NUM_RINGS];
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u32 hws[I915_NUM_RINGS];
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u32 ipeir[I915_NUM_RINGS];
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u32 ipehr[I915_NUM_RINGS];
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u32 instdone[I915_NUM_RINGS];
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u32 acthd[I915_NUM_RINGS];
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u32 bbstate[I915_NUM_RINGS];
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u32 instpm[I915_NUM_RINGS];
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u32 instps[I915_NUM_RINGS];
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u32 seqno[I915_NUM_RINGS];
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u64 bbaddr[I915_NUM_RINGS];
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u32 fault_reg[I915_NUM_RINGS];
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u32 faddr[I915_NUM_RINGS];
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u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
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u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
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/* Software tracked state */
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bool waiting[I915_NUM_RINGS];
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int hangcheck_score[I915_NUM_RINGS];
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enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS];
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/* our own tracking of ring head and tail */
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u32 cpu_ring_head[I915_NUM_RINGS];
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u32 cpu_ring_tail[I915_NUM_RINGS];
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u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
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struct drm_i915_error_ring {
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bool valid;
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/* Software tracked state */
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bool waiting;
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int hangcheck_score;
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enum intel_ring_hangcheck_action hangcheck_action;
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int num_requests;
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/* our own tracking of ring head and tail */
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u32 cpu_ring_head;
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u32 cpu_ring_tail;
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u32 semaphore_seqno[I915_NUM_RINGS - 1];
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/* Register state */
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u32 tail;
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u32 head;
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u32 ctl;
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u32 hws;
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u32 ipeir;
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u32 ipehr;
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u32 instdone;
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u32 acthd;
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u32 bbstate;
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u32 instpm;
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u32 instps;
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u32 seqno;
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u64 bbaddr;
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u32 fault_reg;
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u32 faddr;
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u32 rc_psmi; /* sleep state */
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u32 semaphore_mboxes[I915_NUM_RINGS - 1];
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struct drm_i915_error_object {
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int page_count;
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u32 gtt_offset;
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u32 *pages[0];
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} *ringbuffer, *batchbuffer, *ctx, *hws;
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} *ringbuffer, *batchbuffer, *ctx, *hws_page;
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struct drm_i915_error_request {
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long jiffies;
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u32 seqno;
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u32 tail;
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} *requests;
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int num_requests;
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} ring[I915_NUM_RINGS];
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struct drm_i915_error_buffer {
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u32 size;
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@ -235,51 +235,48 @@ static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
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static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
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struct drm_device *dev,
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struct drm_i915_error_state *error,
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unsigned ring)
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struct drm_i915_error_ring *ring)
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{
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BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
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if (!error->ring[ring].valid)
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if (!ring->valid)
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return;
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err_printf(m, "%s command stream:\n", ring_str(ring));
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err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
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err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
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err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
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err_printf(m, " HWS: 0x%08x\n", error->hws[ring]);
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err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
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err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
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err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
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err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
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err_printf(m, " HEAD: 0x%08x\n", ring->head);
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err_printf(m, " TAIL: 0x%08x\n", ring->tail);
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err_printf(m, " CTL: 0x%08x\n", ring->ctl);
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err_printf(m, " HWS: 0x%08x\n", ring->hws);
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err_printf(m, " ACTHD: 0x%08x\n", ring->acthd);
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err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
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err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
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err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
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if (INTEL_INFO(dev)->gen >= 4) {
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err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr[ring]);
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err_printf(m, " BB_STATE: 0x%08x\n", error->bbstate[ring]);
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err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
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err_printf(m, " BBADDR: 0x%08llx\n", ring->bbaddr);
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err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
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err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
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}
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err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
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err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
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err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
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err_printf(m, " FADDR: 0x%08x\n", ring->faddr);
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if (INTEL_INFO(dev)->gen >= 6) {
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err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
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err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
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err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
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err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
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err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
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error->semaphore_mboxes[ring][0],
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error->semaphore_seqno[ring][0]);
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ring->semaphore_mboxes[0],
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ring->semaphore_seqno[0]);
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err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
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error->semaphore_mboxes[ring][1],
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error->semaphore_seqno[ring][1]);
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ring->semaphore_mboxes[1],
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ring->semaphore_seqno[1]);
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if (HAS_VEBOX(dev)) {
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err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
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error->semaphore_mboxes[ring][2],
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error->semaphore_seqno[ring][2]);
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ring->semaphore_mboxes[2],
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ring->semaphore_seqno[2]);
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}
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}
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err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
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err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
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err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
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err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
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err_printf(m, " seqno: 0x%08x\n", ring->seqno);
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err_printf(m, " waiting: %s\n", yesno(ring->waiting));
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err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
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err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
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err_printf(m, " hangcheck: %s [%d]\n",
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hangcheck_action_to_str(error->hangcheck_action[ring]),
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error->hangcheck_score[ring]);
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hangcheck_action_to_str(ring->hangcheck_action),
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ring->hangcheck_score);
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}
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void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
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@ -331,8 +328,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
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if (INTEL_INFO(dev)->gen == 7)
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err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
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for (i = 0; i < ARRAY_SIZE(error->ring); i++)
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i915_ring_error_state(m, dev, error, i);
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for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
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err_printf(m, "%s command stream:\n", ring_str(i));
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i915_ring_error_state(m, dev, &error->ring[i]);
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}
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if (error->active_bo)
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print_error_buffers(m, "Active",
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@ -388,7 +387,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
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}
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}
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if ((obj = error->ring[i].hws)) {
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if ((obj = error->ring[i].hws_page)) {
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err_printf(m, "%s --- HW Status = 0x%08x\n",
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dev_priv->ring[i].name,
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obj->gtt_offset);
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@ -486,7 +485,7 @@ static void i915_error_state_free(struct kref *error_ref)
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for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
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i915_error_object_free(error->ring[i].batchbuffer);
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i915_error_object_free(error->ring[i].ringbuffer);
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i915_error_object_free(error->ring[i].hws);
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i915_error_object_free(error->ring[i].hws_page);
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i915_error_object_free(error->ring[i].ctx);
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kfree(error->ring[i].requests);
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}
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@ -755,52 +754,52 @@ i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
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}
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static void i915_record_ring_state(struct drm_device *dev,
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struct drm_i915_error_state *error,
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struct intel_ring_buffer *ring)
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struct intel_ring_buffer *ring,
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struct drm_i915_error_ring *ering)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (INTEL_INFO(dev)->gen >= 6) {
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error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
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error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
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error->semaphore_mboxes[ring->id][0]
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ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
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ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
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ering->semaphore_mboxes[0]
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= I915_READ(RING_SYNC_0(ring->mmio_base));
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error->semaphore_mboxes[ring->id][1]
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ering->semaphore_mboxes[1]
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= I915_READ(RING_SYNC_1(ring->mmio_base));
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error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
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error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
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ering->semaphore_seqno[0] = ring->sync_seqno[0];
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ering->semaphore_seqno[1] = ring->sync_seqno[1];
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}
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if (HAS_VEBOX(dev)) {
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error->semaphore_mboxes[ring->id][2] =
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ering->semaphore_mboxes[2] =
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I915_READ(RING_SYNC_2(ring->mmio_base));
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error->semaphore_seqno[ring->id][2] = ring->sync_seqno[2];
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ering->semaphore_seqno[2] = ring->sync_seqno[2];
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}
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if (INTEL_INFO(dev)->gen >= 4) {
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error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
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error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
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error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
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error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
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error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
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error->bbaddr[ring->id] = I915_READ(RING_BBADDR(ring->mmio_base));
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ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
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ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
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ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
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ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
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ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
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ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
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if (INTEL_INFO(dev)->gen >= 8)
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error->bbaddr[ring->id] |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
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error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base));
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ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
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ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
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} else {
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error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
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error->ipeir[ring->id] = I915_READ(IPEIR);
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error->ipehr[ring->id] = I915_READ(IPEHR);
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error->instdone[ring->id] = I915_READ(INSTDONE);
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ering->faddr = I915_READ(DMA_FADD_I8XX);
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ering->ipeir = I915_READ(IPEIR);
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ering->ipehr = I915_READ(IPEHR);
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ering->instdone = I915_READ(INSTDONE);
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}
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error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
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error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
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error->seqno[ring->id] = ring->get_seqno(ring, false);
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error->acthd[ring->id] = intel_ring_get_active_head(ring);
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error->head[ring->id] = I915_READ_HEAD(ring);
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error->tail[ring->id] = I915_READ_TAIL(ring);
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error->ctl[ring->id] = I915_READ_CTL(ring);
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ering->waiting = waitqueue_active(&ring->irq_queue);
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ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
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ering->seqno = ring->get_seqno(ring, false);
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ering->acthd = intel_ring_get_active_head(ring);
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ering->head = I915_READ_HEAD(ring);
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ering->tail = I915_READ_TAIL(ring);
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ering->ctl = I915_READ_CTL(ring);
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if (I915_NEED_GFX_HWS(dev)) {
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int mmio;
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@ -828,14 +827,14 @@ static void i915_record_ring_state(struct drm_device *dev,
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mmio = RING_HWS_PGA(ring->mmio_base);
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}
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error->hws[ring->id] = I915_READ(mmio);
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ering->hws = I915_READ(mmio);
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}
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error->cpu_ring_head[ring->id] = ring->head;
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error->cpu_ring_tail[ring->id] = ring->tail;
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ering->cpu_ring_head = ring->head;
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ering->cpu_ring_tail = ring->tail;
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error->hangcheck_score[ring->id] = ring->hangcheck.score;
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error->hangcheck_action[ring->id] = ring->hangcheck.action;
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ering->hangcheck_score = ring->hangcheck.score;
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ering->hangcheck_action = ring->hangcheck.action;
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}
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@ -876,7 +875,7 @@ static void i915_gem_record_rings(struct drm_device *dev,
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error->ring[i].valid = true;
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i915_record_ring_state(dev, error, ring);
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i915_record_ring_state(dev, ring, &error->ring[i]);
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error->ring[i].batchbuffer =
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i915_error_first_batchbuffer(dev_priv, ring);
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@ -885,7 +884,7 @@ static void i915_gem_record_rings(struct drm_device *dev,
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i915_error_ggtt_object_create(dev_priv, ring->obj);
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if (ring->status_page.obj)
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error->ring[i].hws =
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error->ring[i].hws_page =
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i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
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i915_gem_record_active_context(ring, error, &error->ring[i]);
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