mmc: sdhci-of-arasan: Add support for Intel Keem Bay
Intel Keem Bay SoC eMMC/SD/SDIO controller is based on Arasan SD 3.0 / eMMC 5.1 host controller IP. However, it does not support 64-bit access as its AXI interface has 32-bit address ports. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200526062758.17642-3-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Wan Ahmad Zainie
Ulf Hansson
Родитель
ce3fefacfb
Коммит
36c6aadaae
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@ -75,6 +75,7 @@ struct sdhci_arasan_soc_ctl_field {
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*
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* @baseclkfreq: Where to find corecfg_baseclkfreq
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* @clockmultiplier: Where to find corecfg_clockmultiplier
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* @support64b: Where to find SUPPORT64B bit
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* @hiword_update: If true, use HIWORD_UPDATE to access the syscon
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*
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* It's up to the licensee of the Arsan IP block to make these available
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@ -84,6 +85,7 @@ struct sdhci_arasan_soc_ctl_field {
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struct sdhci_arasan_soc_ctl_map {
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struct sdhci_arasan_soc_ctl_field baseclkfreq;
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struct sdhci_arasan_soc_ctl_field clockmultiplier;
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struct sdhci_arasan_soc_ctl_field support64b;
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bool hiword_update;
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};
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@ -184,6 +186,13 @@ static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
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.hiword_update = false,
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};
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static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
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.baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
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.clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
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.support64b = { .reg = 0x4, .width = 1, .shift = 24 },
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.hiword_update = false,
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};
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/**
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* sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
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*
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@ -1113,6 +1122,50 @@ static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
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.clk_ops = &arasan_clk_ops,
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};
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static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
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.ops = &sdhci_arasan_cqe_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
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SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
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SDHCI_QUIRK_NO_LED |
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SDHCI_QUIRK_32BIT_DMA_ADDR |
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SDHCI_QUIRK_32BIT_DMA_SIZE |
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SDHCI_QUIRK_32BIT_ADMA_SIZE,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
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SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
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SDHCI_QUIRK2_STOP_WITH_TC |
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SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
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};
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static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
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.ops = &sdhci_arasan_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
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SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
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SDHCI_QUIRK_NO_LED |
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SDHCI_QUIRK_32BIT_DMA_ADDR |
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SDHCI_QUIRK_32BIT_DMA_SIZE |
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SDHCI_QUIRK_32BIT_ADMA_SIZE,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
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SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
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SDHCI_QUIRK2_STOP_WITH_TC |
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SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
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};
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static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
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.ops = &sdhci_arasan_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
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SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
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SDHCI_QUIRK_NO_LED |
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SDHCI_QUIRK_32BIT_DMA_ADDR |
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SDHCI_QUIRK_32BIT_DMA_SIZE |
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SDHCI_QUIRK_32BIT_ADMA_SIZE,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
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SDHCI_QUIRK2_HOST_OFF_CARD_ON |
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SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
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};
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static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
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.soc_ctl_map = &rk3399_soc_ctl_map,
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.pdata = &sdhci_arasan_cqe_pdata,
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@ -1158,6 +1211,21 @@ static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
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.clk_ops = &versal_clk_ops,
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};
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static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
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.soc_ctl_map = &intel_keembay_soc_ctl_map,
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.pdata = &sdhci_keembay_emmc_pdata,
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};
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static struct sdhci_arasan_of_data intel_keembay_sd_data = {
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.soc_ctl_map = &intel_keembay_soc_ctl_map,
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.pdata = &sdhci_keembay_sd_pdata,
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};
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static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
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.soc_ctl_map = &intel_keembay_soc_ctl_map,
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.pdata = &sdhci_keembay_sdio_pdata,
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};
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static const struct of_device_id sdhci_arasan_of_match[] = {
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/* SoC-specific compatible strings w/ soc_ctl_map */
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{
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@ -1172,6 +1240,18 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
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.compatible = "intel,lgm-sdhci-5.1-sdxc",
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.data = &intel_lgm_sdxc_data,
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},
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{
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.compatible = "intel,keembay-sdhci-5.1-emmc",
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.data = &intel_keembay_emmc_data,
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},
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{
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.compatible = "intel,keembay-sdhci-5.1-sd",
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.data = &intel_keembay_sd_data,
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},
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{
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.compatible = "intel,keembay-sdhci-5.1-sdio",
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.data = &intel_keembay_sdio_data,
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},
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/* Generic compatible below here */
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{
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.compatible = "arasan,sdhci-8.9a",
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@ -1315,6 +1395,40 @@ static void sdhci_arasan_unregister_sdclk(struct device *dev)
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of_clk_del_provider(dev->of_node);
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}
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/**
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* sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
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*
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* This should be set based on the System Address Bus.
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* 0: the Core supports only 32-bit System Address Bus.
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* 1: the Core supports 64-bit System Address Bus.
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*
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* NOTES:
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* - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
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* Keem Bay does not support 64-bit access.
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*
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* @host The sdhci_host
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*/
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static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
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sdhci_arasan->soc_ctl_map;
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/* Having a map is optional */
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if (!soc_ctl_map)
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return;
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/* If we have a map, we expect to have a syscon */
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if (!sdhci_arasan->soc_ctl_base) {
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pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
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mmc_hostname(host->mmc));
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return;
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}
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sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
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}
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/**
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* sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
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*
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@ -1487,6 +1601,15 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
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"rockchip,rk3399-sdhci-5.1"))
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sdhci_arasan_update_clockmultiplier(host, 0x0);
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if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
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of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
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of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
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sdhci_arasan_update_clockmultiplier(host, 0x0);
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sdhci_arasan_update_support64b(host, 0x0);
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host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
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}
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sdhci_arasan_update_baseclkfreq(host);
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ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
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