memory: tegra30-mc: Fix IRQ handler.
In Tegra30 any memory controller interrupt would cause an infinite loop in the IRQ handler. Additionally, a garbage pointer was used to read the MC status registers, which causes wrong values to be printed if a MC error occurred. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -218,7 +218,7 @@ static void tegra30_mc_decode(struct tegra30_mc *mc, int n)
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return;
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}
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err = readl(mc + MC_ERR_STATUS);
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err = mc_readl(mc, MC_ERR_STATUS);
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type = (err & MC_ERR_TYPE_MASK) >> MC_ERR_TYPE_SHIFT;
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perm = (err & MC_ERR_INVALID_SMMU_PAGE_MASK) >>
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@ -235,7 +235,7 @@ static void tegra30_mc_decode(struct tegra30_mc *mc, int n)
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if (cid < ARRAY_SIZE(tegra30_mc_client))
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client = tegra30_mc_client[cid];
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addr = readl(mc + MC_ERR_ADR);
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addr = mc_readl(mc, MC_ERR_ADR);
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dev_err_ratelimited(mc->dev, "%s (0x%08x): 0x%08x %s (%s %s %s %s)\n",
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mc_int_err[idx], err, addr, client,
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@ -313,8 +313,11 @@ static irqreturn_t tegra30_mc_isr(int irq, void *data)
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mask &= stat;
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if (!mask)
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return IRQ_NONE;
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while ((bit = ffs(mask)) != 0)
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while ((bit = ffs(mask)) != 0) {
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tegra30_mc_decode(mc, bit - 1);
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mask &= ~BIT(bit - 1);
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}
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mc_writel(mc, stat, MC_INTSTATUS);
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return IRQ_HANDLED;
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}
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