clk: meson: g12a: add cpu clocks
Add the Amlogic G12A Family CPU Clock tree in read/only for now. The CPU clock can either use the SYS_PLL for > 1GHz frequencies or use a couple of div+mux from 1GHz/667MHz/24MHz source with 2 non-glitch muxes. Proper DVFS support will come in a second time. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: fixed cpu clocks namings] Link: https://lkml.kernel.org/r/20190304131129.7762-3-narmstrong@baylibre.com
This commit is contained in:
Neil Armstrong
Родитель
77a725ff7a
Коммит
370294e266
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@ -150,6 +150,318 @@ static struct clk_regmap g12a_sys_pll = {
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},
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};
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static struct clk_regmap g12a_sys_pll_div16_en = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 24,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "sys_pll_div16_en",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "sys_pll" },
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.num_parents = 1,
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/*
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* This clock is used to debug the sys_pll range
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* Linux should not change it at runtime
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*/
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},
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};
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static struct clk_fixed_factor g12a_sys_pll_div16 = {
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.mult = 1,
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.div = 16,
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.hw.init = &(struct clk_init_data){
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.name = "sys_pll_div16",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "sys_pll_div16_en" },
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.num_parents = 1,
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},
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};
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/* Datasheet names this field as "premux0" */
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static struct clk_regmap g12a_cpu_clk_premux0 = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL0,
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.mask = 0x3,
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.shift = 0,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_dyn0_sel",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_names = (const char *[]){ IN_PREFIX "xtal",
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"fclk_div2",
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"fclk_div3" },
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.num_parents = 3,
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},
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};
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/* Datasheet names this field as "mux0_divn_tcnt" */
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static struct clk_regmap g12a_cpu_clk_mux0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SYS_CPU_CLK_CNTL0,
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.shift = 4,
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.width = 6,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_dyn0_div",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
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.num_parents = 1,
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},
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};
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/* Datasheet names this field as "postmux0" */
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static struct clk_regmap g12a_cpu_clk_postmux0 = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL0,
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.mask = 0x1,
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.shift = 2,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_dyn0",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
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"cpu_clk_dyn0_div" },
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.num_parents = 2,
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},
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};
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/* Datasheet names this field as "premux1" */
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static struct clk_regmap g12a_cpu_clk_premux1 = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL0,
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.mask = 0x3,
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.shift = 16,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_dyn1_sel",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_names = (const char *[]){ IN_PREFIX "xtal",
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"fclk_div2",
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"fclk_div3" },
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.num_parents = 3,
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},
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};
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/* Datasheet names this field as "Mux1_divn_tcnt" */
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static struct clk_regmap g12a_cpu_clk_mux1_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SYS_CPU_CLK_CNTL0,
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.shift = 20,
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.width = 6,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_dyn1_div",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
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.num_parents = 1,
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},
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};
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/* Datasheet names this field as "postmux1" */
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static struct clk_regmap g12a_cpu_clk_postmux1 = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL0,
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.mask = 0x1,
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.shift = 18,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_dyn1",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
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"cpu_clk_dyn1_div" },
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.num_parents = 2,
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},
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};
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/* Datasheet names this field as "Final_dyn_mux_sel" */
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static struct clk_regmap g12a_cpu_clk_dyn = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL0,
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.mask = 0x1,
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.shift = 10,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_dyn",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk_dyn0",
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"cpu_clk_dyn1" },
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.num_parents = 2,
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},
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};
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/* Datasheet names this field as "Final_mux_sel" */
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static struct clk_regmap g12a_cpu_clk = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL0,
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.mask = 0x1,
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.shift = 11,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk_dyn",
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"sys_pll" },
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.num_parents = 2,
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},
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};
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static struct clk_regmap g12a_cpu_clk_div16_en = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 1,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "cpu_clk_div16_en",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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/*
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* This clock is used to debug the cpu_clk range
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* Linux should not change it at runtime
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*/
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},
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};
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static struct clk_fixed_factor g12a_cpu_clk_div16 = {
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.mult = 1,
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.div = 16,
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_div16",
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.ops = &clk_fixed_factor_ops,
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.parent_names = (const char *[]){ "cpu_clk_div16_en" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_cpu_clk_apb_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.shift = 3,
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.width = 3,
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.flags = CLK_DIVIDER_POWER_OF_TWO,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_apb_div",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_cpu_clk_apb = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 1,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "cpu_clk_apb",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk_apb_div" },
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.num_parents = 1,
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/*
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* This clock is set by the ROM monitor code,
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* Linux should not change it at runtime
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*/
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},
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};
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static struct clk_regmap g12a_cpu_clk_atb_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.shift = 6,
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.width = 3,
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.flags = CLK_DIVIDER_POWER_OF_TWO,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_atb_div",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_cpu_clk_atb = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 17,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "cpu_clk_atb",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk_atb_div" },
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.num_parents = 1,
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/*
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* This clock is set by the ROM monitor code,
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* Linux should not change it at runtime
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*/
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},
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};
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static struct clk_regmap g12a_cpu_clk_axi_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.shift = 9,
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.width = 3,
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.flags = CLK_DIVIDER_POWER_OF_TWO,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_axi_div",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_cpu_clk_axi = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 18,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "cpu_clk_axi",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk_axi_div" },
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.num_parents = 1,
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/*
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* This clock is set by the ROM monitor code,
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* Linux should not change it at runtime
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*/
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},
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};
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static struct clk_regmap g12a_cpu_clk_trace_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.shift = 20,
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.width = 3,
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.flags = CLK_DIVIDER_POWER_OF_TWO,
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},
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.hw.init = &(struct clk_init_data){
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.name = "cpu_clk_trace_div",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk" },
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.num_parents = 1,
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},
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};
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static struct clk_regmap g12a_cpu_clk_trace = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 23,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "cpu_clk_trace",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ "cpu_clk_trace_div" },
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.num_parents = 1,
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/*
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* This clock is set by the ROM monitor code,
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* Linux should not change it at runtime
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*/
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},
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};
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static const struct pll_mult_range g12a_gp0_pll_mult_range = {
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.min = 55,
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.max = 255,
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@ -2167,6 +2479,26 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
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[CLKID_MALI] = &g12a_mali.hw,
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[CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,
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[CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,
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[CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
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[CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
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[CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
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[CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
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[CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
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[CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
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[CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
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[CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
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[CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
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[CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
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[CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
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[CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
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[CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
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[CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
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[CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
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[CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
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[CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
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[CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
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[CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
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[CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -2335,6 +2667,24 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
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&g12a_mali_1,
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&g12a_mali,
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&g12a_mpll_50m,
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&g12a_sys_pll_div16_en,
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&g12a_cpu_clk_premux0,
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&g12a_cpu_clk_mux0_div,
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&g12a_cpu_clk_postmux0,
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&g12a_cpu_clk_premux1,
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&g12a_cpu_clk_mux1_div,
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&g12a_cpu_clk_postmux1,
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&g12a_cpu_clk_dyn,
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&g12a_cpu_clk,
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&g12a_cpu_clk_div16_en,
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&g12a_cpu_clk_apb_div,
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&g12a_cpu_clk_apb,
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&g12a_cpu_clk_atb_div,
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&g12a_cpu_clk_atb,
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&g12a_cpu_clk_axi_div,
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&g12a_cpu_clk_axi,
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&g12a_cpu_clk_trace_div,
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&g12a_cpu_clk_trace,
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};
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static const struct meson_eeclkc_data g12a_clkc_data = {
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@ -50,6 +50,7 @@
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#define HHI_GCLK_MPEG2 0x148
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#define HHI_GCLK_OTHER 0x150
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#define HHI_GCLK_OTHER2 0x154
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#define HHI_SYS_CPU_CLK_CNTL1 0x15c
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#define HHI_VID_CLK_DIV 0x164
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#define HHI_MPEG_CLK_CNTL 0x174
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#define HHI_AUD_CLK_CNTL 0x178
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@ -166,8 +167,27 @@
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#define CLKID_MALI_0_DIV 170
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#define CLKID_MALI_1_DIV 173
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#define CLKID_MPLL_5OM_DIV 176
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#define CLKID_SYS_PLL_DIV16_EN 178
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#define CLKID_SYS_PLL_DIV16 179
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#define CLKID_CPU_CLK_DYN0_SEL 180
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#define CLKID_CPU_CLK_DYN0_DIV 181
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#define CLKID_CPU_CLK_DYN0 182
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#define CLKID_CPU_CLK_DYN1_SEL 183
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#define CLKID_CPU_CLK_DYN1_DIV 184
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#define CLKID_CPU_CLK_DYN1 185
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#define CLKID_CPU_CLK_DYN 186
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#define CLKID_CPU_CLK_DIV16_EN 188
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#define CLKID_CPU_CLK_DIV16 189
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#define CLKID_CPU_CLK_APB_DIV 190
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#define CLKID_CPU_CLK_APB 191
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#define CLKID_CPU_CLK_ATB_DIV 192
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#define CLKID_CPU_CLK_ATB 193
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#define CLKID_CPU_CLK_AXI_DIV 194
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#define CLKID_CPU_CLK_AXI 195
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#define CLKID_CPU_CLK_TRACE_DIV 196
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#define CLKID_CPU_CLK_TRACE 197
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#define NR_CLKS 178
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#define NR_CLKS 198
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/g12a-clkc.h>
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