Linux 4.17-rc5
-----BEGIN PGP SIGNATURE----- iQFSBAABCAA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAlr4xw8eHHRvcnZhbGRz QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGNYoH/1d5zyMpVJVUKZ0K LuEctCGby1PjSvSOhmMuxFVagFAqfBJXmwWTeohLfLG48r/Yk0AsZQ5HH13/8baj k/T8UgUvKZKustndCRp+joQ3Pa1ZpcIFaWRvB8pKFCefJ/F/Lj4B4X1HYI7vLq0K /ZBXUdy3ry0lcVuypnaARYAb2O7l/nyZIjZ3FhiuyymWe7Jpo+G7VK922LOMSX/y VYFZCWa8nxN+yFhO0ao9X5k7ggIiUrEBtbfNrk19VtAn0hx+OYKW2KfJK/eHNey/ CKrOT+KAxU8VU29AEIbYzlL3yrQmULcEoIDiqJ/6m5m6JwsEbP6EqQHs0TiuQFpq A0MO9rw= =yjUP -----END PGP SIGNATURE----- Merge tag 'v4.17-rc5' into locking/core, to pick up fixes Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
Коммит
371b326908
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@ -145,7 +145,7 @@ feature enabled.]
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||||
In this mode ``intel_pstate`` registers utilization update callbacks with the
|
||||
CPU scheduler in order to run a P-state selection algorithm, either
|
||||
``powersave`` or ``performance``, depending on the ``scaling_cur_freq`` policy
|
||||
``powersave`` or ``performance``, depending on the ``scaling_governor`` policy
|
||||
setting in ``sysfs``. The current CPU frequency information to be made
|
||||
available from the ``scaling_cur_freq`` policy attribute in ``sysfs`` is
|
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periodically updated by those utilization update callbacks too.
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@ -15,7 +15,7 @@ Sleep States That Can Be Supported
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==================================
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|
||||
Depending on its configuration and the capabilities of the platform it runs on,
|
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the Linux kernel can support up to four system sleep states, includig
|
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the Linux kernel can support up to four system sleep states, including
|
||||
hibernation and up to three variants of system suspend. The sleep states that
|
||||
can be supported by the kernel are listed below.
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||||
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@ -264,7 +264,10 @@ i) Constructor
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data device, but just remove the mapping.
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read_only: Don't allow any changes to be made to the pool
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metadata.
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metadata. This mode is only available after the
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thin-pool has been created and first used in full
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read/write mode. It cannot be specified on initial
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thin-pool creation.
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error_if_no_space: Error IOs, instead of queueing, if no space.
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@ -30,7 +30,6 @@ compatible:
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Optional properties:
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- dma-coherent : Present if dma operations are coherent
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- clocks : a list of phandle + clock specifier pairs
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- resets : a list of phandle + reset specifier pairs
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- target-supply : regulator for SATA target power
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- phys : reference to the SATA PHY node
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- phy-names : must be "sata-phy"
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@ -38,7 +38,7 @@ Display Timings
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require specific display timings. The panel-timing subnode expresses those
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timings as specified in the timing subnode section of the display timing
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bindings defined in
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Documentation/devicetree/bindings/display/display-timing.txt.
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Documentation/devicetree/bindings/display/panel/display-timing.txt.
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Connectivity
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@ -26,6 +26,7 @@ Required Properties:
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- "renesas,dmac-r8a7794" (R-Car E2)
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- "renesas,dmac-r8a7795" (R-Car H3)
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- "renesas,dmac-r8a7796" (R-Car M3-W)
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- "renesas,dmac-r8a77965" (R-Car M3-N)
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- "renesas,dmac-r8a77970" (R-Car V3M)
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- "renesas,dmac-r8a77980" (R-Car V3H)
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@ -5,7 +5,9 @@ Required properties:
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- compatible: Must contain one or more of the following:
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- "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
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- "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
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- "renesas,r8a7796-canfd" for R8A7796 (R-Car M3) compatible controller.
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- "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
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- "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller.
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- "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first, followed by the
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@ -18,6 +18,7 @@ Required properties:
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- "renesas,etheravb-r8a7795" for the R8A7795 SoC.
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- "renesas,etheravb-r8a7796" for the R8A7796 SoC.
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- "renesas,etheravb-r8a77965" for the R8A77965 SoC.
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- "renesas,etheravb-r8a77970" for the R8A77970 SoC.
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- "renesas,etheravb-r8a77980" for the R8A77980 SoC.
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- "renesas,etheravb-r8a77995" for the R8A77995 SoC.
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@ -56,9 +56,9 @@ pins it needs, and how they should be configured, with regard to muxer
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configuration, drive strength and pullups. If one of these options is
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not set, its actual value will be unspecified.
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This driver supports the generic pin multiplexing and configuration
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bindings. For details on each properties, you can refer to
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./pinctrl-bindings.txt.
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Allwinner A1X Pin Controller supports the generic pin multiplexing and
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configuration bindings. For details on each properties, you can refer to
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./pinctrl-bindings.txt.
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Required sub-node properties:
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- pins
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@ -43,6 +43,8 @@ Required properties:
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- "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
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- "renesas,scif-r8a7796" for R8A7796 (R-Car M3-W) SCIF compatible UART.
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- "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART.
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- "renesas,scif-r8a77965" for R8A77965 (R-Car M3-N) SCIF compatible UART.
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- "renesas,hscif-r8a77965" for R8A77965 (R-Car M3-N) HSCIF compatible UART.
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- "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART.
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- "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART.
|
||||
- "renesas,scif-r8a77980" for R8A77980 (R-Car V3H) SCIF compatible UART.
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@ -182,6 +182,7 @@ karo Ka-Ro electronics GmbH
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keithkoep Keith & Koep GmbH
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keymile Keymile GmbH
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khadas Khadas
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kiebackpeter Kieback & Peter GmbH
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kinetic Kinetic Technologies
|
||||
kingnovel Kingnovel Technology Co., Ltd.
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||||
kosagi Sutajio Ko-Usagi PTE Ltd.
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@ -98,6 +98,14 @@ Finally, if you need to remove all overlays in one-go, just call
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of_overlay_remove_all() which will remove every single one in the correct
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order.
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||||
|
||||
In addition, there is the option to register notifiers that get called on
|
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overlay operations. See of_overlay_notifier_register/unregister and
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enum of_overlay_notify_action for details.
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|
||||
Note that a notifier callback is not supposed to store pointers to a device
|
||||
tree node or its content beyond OF_OVERLAY_POST_REMOVE corresponding to the
|
||||
respective node it received.
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||||
Overlay DTS Format
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||||
------------------
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@ -177,14 +177,14 @@ BUGS
|
|||
****
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||||
|
||||
|
||||
Report bugs to Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
Report bugs to Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
|
||||
|
||||
COPYRIGHT
|
||||
*********
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||||
|
||||
|
||||
Copyright (c) 2016 by Mauro Carvalho Chehab <mchehab@s-opensource.com>.
|
||||
Copyright (c) 2016 by Mauro Carvalho Chehab <mchehab+samsung@kernel.org>.
|
||||
|
||||
License GPLv2: GNU GPL version 2 <http://gnu.org/licenses/gpl.html>.
|
||||
|
||||
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|
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@ -7,7 +7,7 @@ file: uapi/v4l/keytable.c
|
|||
|
||||
/* keytable.c - This program allows checking/replacing keys at IR
|
||||
|
||||
Copyright (C) 2006-2009 Mauro Carvalho Chehab <mchehab@infradead.org>
|
||||
Copyright (C) 2006-2009 Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
|
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|
|||
|
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@ -6,7 +6,7 @@ file: media/v4l/v4l2grab.c
|
|||
.. code-block:: c
|
||||
|
||||
/* V4L2 video picture grabber
|
||||
Copyright (C) 2009 Mauro Carvalho Chehab <mchehab@infradead.org>
|
||||
Copyright (C) 2009 Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
|
|
|
|||
|
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@ -387,11 +387,11 @@ tree for more details.
|
|||
|
||||
=head1 BUGS
|
||||
|
||||
Report bugs to Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
Report bugs to Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
|
||||
=head1 COPYRIGHT
|
||||
|
||||
Copyright (c) 2016 by Mauro Carvalho Chehab <mchehab@s-opensource.com>.
|
||||
Copyright (c) 2016 by Mauro Carvalho Chehab <mchehab+samsung@kernel.org>.
|
||||
|
||||
License GPLv2: GNU GPL version 2 <http://gnu.org/licenses/gpl.html>.
|
||||
|
||||
|
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|
|||
|
|
@ -6,7 +6,7 @@ communicating in English you can also ask the Chinese maintainer for
|
|||
help. Contact the Chinese maintainer if this translation is outdated
|
||||
or if there is a problem with the translation.
|
||||
|
||||
Maintainer: Mauro Carvalho Chehab <mchehab@infradead.org>
|
||||
Maintainer: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
Chinese maintainer: Fu Wei <tekkamanninja@gmail.com>
|
||||
---------------------------------------------------------------------
|
||||
Documentation/video4linux/v4l2-framework.txt 的中文翻译
|
||||
|
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@ -14,7 +14,7 @@ Documentation/video4linux/v4l2-framework.txt 的中文翻译
|
|||
如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文
|
||||
交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻
|
||||
译存在问题，请联系中文版维护者。
|
||||
英文版维护者： Mauro Carvalho Chehab <mchehab@infradead.org>
|
||||
英文版维护者： Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
中文版维护者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
|
||||
中文版翻译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
|
||||
中文版校译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
|
||||
|
|
|
|||
30
MAINTAINERS
30
MAINTAINERS
|
|
@ -137,9 +137,9 @@ Maintainers List (try to look for most precise areas first)
|
|||
-----------------------------------
|
||||
|
||||
3C59X NETWORK DRIVER
|
||||
M: Steffen Klassert <klassert@mathematik.tu-chemnitz.de>
|
||||
M: Steffen Klassert <klassert@kernel.org>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
S: Odd Fixes
|
||||
F: Documentation/networking/vortex.txt
|
||||
F: drivers/net/ethernet/3com/3c59x.c
|
||||
|
||||
|
|
@ -2554,7 +2554,6 @@ F: Documentation/devicetree/bindings/sound/axentia,*
|
|||
F: sound/soc/atmel/tse850-pcm5142.c
|
||||
|
||||
AZ6007 DVB DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
|
@ -3083,7 +3082,6 @@ F: include/linux/btrfs*
|
|||
F: include/uapi/linux/btrfs*
|
||||
|
||||
BTTV VIDEO4LINUX DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
|
@ -3693,7 +3691,6 @@ F: drivers/cpufreq/arm_big_little_dt.c
|
|||
|
||||
CPU POWER MONITORING SUBSYSTEM
|
||||
M: Thomas Renninger <trenn@suse.com>
|
||||
M: Shuah Khan <shuahkh@osg.samsung.com>
|
||||
M: Shuah Khan <shuah@kernel.org>
|
||||
L: linux-pm@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -3812,7 +3809,6 @@ S: Maintained
|
|||
F: drivers/media/dvb-frontends/cx24120*
|
||||
|
||||
CX88 VIDEO4LINUX DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
|
@ -5053,7 +5049,6 @@ F: drivers/edac/thunderx_edac*
|
|||
|
||||
EDAC-CORE
|
||||
M: Borislav Petkov <bp@alien8.de>
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git for-next
|
||||
|
|
@ -5082,7 +5077,6 @@ S: Maintained
|
|||
F: drivers/edac/fsl_ddr_edac.*
|
||||
|
||||
EDAC-GHES
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -5099,21 +5093,18 @@ S: Maintained
|
|||
F: drivers/edac/i5000_edac.c
|
||||
|
||||
EDAC-I5400
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/edac/i5400_edac.c
|
||||
|
||||
EDAC-I7300
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/edac/i7300_edac.c
|
||||
|
||||
EDAC-I7CORE
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -5163,7 +5154,6 @@ S: Maintained
|
|||
F: drivers/edac/r82600_edac.c
|
||||
|
||||
EDAC-SBRIDGE
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-edac@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -5222,7 +5212,6 @@ S: Maintained
|
|||
F: drivers/net/ethernet/ibm/ehea/
|
||||
|
||||
EM28XX VIDEO4LINUX DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
|
@ -7677,9 +7666,11 @@ L: linux-kbuild@vger.kernel.org
|
|||
S: Maintained
|
||||
F: Documentation/kbuild/
|
||||
F: Makefile
|
||||
F: scripts/Makefile.*
|
||||
F: scripts/Kbuild*
|
||||
F: scripts/Makefile*
|
||||
F: scripts/basic/
|
||||
F: scripts/mk*
|
||||
F: scripts/mod/
|
||||
F: scripts/package/
|
||||
|
||||
KERNEL JANITORS
|
||||
|
|
@ -7704,7 +7695,6 @@ F: include/linux/sunrpc/
|
|||
F: include/uapi/linux/sunrpc/
|
||||
|
||||
KERNEL SELFTEST FRAMEWORK
|
||||
M: Shuah Khan <shuahkh@osg.samsung.com>
|
||||
M: Shuah Khan <shuah@kernel.org>
|
||||
L: linux-kselftest@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git
|
||||
|
|
@ -8872,7 +8862,6 @@ F: Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
|
|||
F: drivers/staging/media/tegra-vde/
|
||||
|
||||
MEDIA INPUT INFRASTRUCTURE (V4L/DVB)
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
P: LinuxTV.org Project
|
||||
L: linux-media@vger.kernel.org
|
||||
|
|
@ -9883,7 +9872,7 @@ F: include/linux/platform_data/nxp-nci.h
|
|||
F: Documentation/devicetree/bindings/net/nfc/
|
||||
|
||||
NFS, SUNRPC, AND LOCKD CLIENTS
|
||||
M: Trond Myklebust <trond.myklebust@primarydata.com>
|
||||
M: Trond Myklebust <trond.myklebust@hammerspace.com>
|
||||
M: Anna Schumaker <anna.schumaker@netapp.com>
|
||||
L: linux-nfs@vger.kernel.org
|
||||
W: http://client.linux-nfs.org
|
||||
|
|
@ -12261,7 +12250,6 @@ S: Odd Fixes
|
|||
F: drivers/media/i2c/saa6588*
|
||||
|
||||
SAA7134 VIDEO4LINUX DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
|
@ -12766,7 +12754,6 @@ S: Maintained
|
|||
F: drivers/media/radio/si4713/radio-usb-si4713.c
|
||||
|
||||
SIANO DVB DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
|
@ -13757,7 +13744,6 @@ S: Maintained
|
|||
F: drivers/media/i2c/tda9840*
|
||||
|
||||
TEA5761 TUNER DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
|
@ -13766,7 +13752,6 @@ S: Odd fixes
|
|||
F: drivers/media/tuners/tea5761.*
|
||||
|
||||
TEA5767 TUNER DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
|
@ -14182,7 +14167,6 @@ F: Documentation/networking/tlan.txt
|
|||
F: drivers/net/ethernet/ti/tlan.*
|
||||
|
||||
TM6000 VIDEO4LINUX DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
|
@ -14665,7 +14649,6 @@ F: drivers/usb/common/usb-otg-fsm.c
|
|||
|
||||
USB OVER IP DRIVER
|
||||
M: Valentina Manea <valentina.manea.m@gmail.com>
|
||||
M: Shuah Khan <shuahkh@osg.samsung.com>
|
||||
M: Shuah Khan <shuah@kernel.org>
|
||||
L: linux-usb@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -15409,7 +15392,6 @@ S: Maintained
|
|||
F: arch/x86/entry/vdso/
|
||||
|
||||
XC2028/3028 TUNER DRIVER
|
||||
M: Mauro Carvalho Chehab <mchehab@s-opensource.com>
|
||||
M: Mauro Carvalho Chehab <mchehab@kernel.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
W: https://linuxtv.org
|
||||
|
|
|
|||
4
Makefile
4
Makefile
|
|
@ -2,8 +2,8 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 17
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc3
|
||||
NAME = Fearless Coyote
|
||||
EXTRAVERSION = -rc5
|
||||
NAME = Merciless Moray
|
||||
|
||||
# *DOCUMENTATION*
|
||||
# To see a list of typical targets execute "make help"
|
||||
|
|
|
|||
|
|
@ -464,6 +464,10 @@ config GCC_PLUGIN_LATENT_ENTROPY
|
|||
config GCC_PLUGIN_STRUCTLEAK
|
||||
bool "Force initialization of variables containing userspace addresses"
|
||||
depends on GCC_PLUGINS
|
||||
# Currently STRUCTLEAK inserts initialization out of live scope of
|
||||
# variables from KASAN point of view. This leads to KASAN false
|
||||
# positive reports. Prohibit this combination for now.
|
||||
depends on !KASAN_EXTRA
|
||||
help
|
||||
This plugin zero-initializes any structures containing a
|
||||
__user attribute. This can prevent some classes of information
|
||||
|
|
|
|||
|
|
@ -303,7 +303,7 @@
|
|||
};
|
||||
|
||||
can1: can@53fe4000 {
|
||||
compatible = "fsl,imx35-flexcan";
|
||||
compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan";
|
||||
reg = <0x53fe4000 0x1000>;
|
||||
clocks = <&clks 33>, <&clks 33>;
|
||||
clock-names = "ipg", "per";
|
||||
|
|
@ -312,7 +312,7 @@
|
|||
};
|
||||
|
||||
can2: can@53fe8000 {
|
||||
compatible = "fsl,imx35-flexcan";
|
||||
compatible = "fsl,imx35-flexcan", "fsl,imx25-flexcan";
|
||||
reg = <0x53fe8000 0x1000>;
|
||||
clocks = <&clks 34>, <&clks 34>;
|
||||
clock-names = "ipg", "per";
|
||||
|
|
|
|||
|
|
@ -551,7 +551,7 @@
|
|||
};
|
||||
|
||||
can1: can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan";
|
||||
compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
|
||||
|
|
@ -561,7 +561,7 @@
|
|||
};
|
||||
|
||||
can2: can@53fcc000 {
|
||||
compatible = "fsl,imx53-flexcan";
|
||||
compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
|
||||
reg = <0x53fcc000 0x4000>;
|
||||
interrupts = <83>;
|
||||
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
|
||||
|
|
|
|||
|
|
@ -75,6 +75,7 @@
|
|||
#define ARM_CPU_IMP_CAVIUM 0x43
|
||||
#define ARM_CPU_IMP_BRCM 0x42
|
||||
#define ARM_CPU_IMP_QCOM 0x51
|
||||
#define ARM_CPU_IMP_NVIDIA 0x4E
|
||||
|
||||
#define ARM_CPU_PART_AEM_V8 0xD0F
|
||||
#define ARM_CPU_PART_FOUNDATION 0xD00
|
||||
|
|
@ -99,6 +100,9 @@
|
|||
#define QCOM_CPU_PART_FALKOR 0xC00
|
||||
#define QCOM_CPU_PART_KRYO 0x200
|
||||
|
||||
#define NVIDIA_CPU_PART_DENVER 0x003
|
||||
#define NVIDIA_CPU_PART_CARMEL 0x004
|
||||
|
||||
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
|
||||
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
|
||||
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
|
||||
|
|
@ -114,6 +118,8 @@
|
|||
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
|
||||
#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
|
||||
#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
|
||||
#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
|
||||
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
|
|
|||
|
|
@ -333,7 +333,7 @@ static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
|
|||
} else {
|
||||
u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
|
||||
sctlr |= (1 << 25);
|
||||
vcpu_write_sys_reg(vcpu, SCTLR_EL1, sctlr);
|
||||
vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -316,6 +316,7 @@ static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
|
|||
MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
|
||||
MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
|
||||
MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
|
||||
MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER),
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -18,11 +18,20 @@
|
|||
#include <linux/compiler.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/kvm_host.h>
|
||||
#include <linux/swab.h>
|
||||
|
||||
#include <asm/kvm_emulate.h>
|
||||
#include <asm/kvm_hyp.h>
|
||||
#include <asm/kvm_mmu.h>
|
||||
|
||||
static bool __hyp_text __is_be(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
if (vcpu_mode_is_32bit(vcpu))
|
||||
return !!(read_sysreg_el2(spsr) & COMPAT_PSR_E_BIT);
|
||||
|
||||
return !!(read_sysreg(SCTLR_EL1) & SCTLR_ELx_EE);
|
||||
}
|
||||
|
||||
/*
|
||||
* __vgic_v2_perform_cpuif_access -- perform a GICV access on behalf of the
|
||||
* guest.
|
||||
|
|
@ -64,14 +73,19 @@ int __hyp_text __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu)
|
|||
addr += fault_ipa - vgic->vgic_cpu_base;
|
||||
|
||||
if (kvm_vcpu_dabt_iswrite(vcpu)) {
|
||||
u32 data = vcpu_data_guest_to_host(vcpu,
|
||||
vcpu_get_reg(vcpu, rd),
|
||||
sizeof(u32));
|
||||
u32 data = vcpu_get_reg(vcpu, rd);
|
||||
if (__is_be(vcpu)) {
|
||||
/* guest pre-swabbed data, undo this for writel() */
|
||||
data = swab32(data);
|
||||
}
|
||||
writel_relaxed(data, addr);
|
||||
} else {
|
||||
u32 data = readl_relaxed(addr);
|
||||
vcpu_set_reg(vcpu, rd, vcpu_data_host_to_guest(vcpu, data,
|
||||
sizeof(u32)));
|
||||
if (__is_be(vcpu)) {
|
||||
/* guest expects swabbed data */
|
||||
data = swab32(data);
|
||||
}
|
||||
vcpu_set_reg(vcpu, rd, data);
|
||||
}
|
||||
|
||||
return 1;
|
||||
|
|
|
|||
|
|
@ -646,8 +646,10 @@ static int keep_initrd __initdata;
|
|||
|
||||
void __init free_initrd_mem(unsigned long start, unsigned long end)
|
||||
{
|
||||
if (!keep_initrd)
|
||||
if (!keep_initrd) {
|
||||
free_reserved_area((void *)start, (void *)end, 0, "initrd");
|
||||
memblock_free(__virt_to_phys(start), end - start);
|
||||
}
|
||||
}
|
||||
|
||||
static int __init keepinitrd_setup(char *__unused)
|
||||
|
|
|
|||
|
|
@ -69,17 +69,30 @@ struct dyn_arch_ftrace {
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_FTRACE_SYSCALLS) && !defined(__ASSEMBLY__)
|
||||
#ifdef PPC64_ELF_ABI_v1
|
||||
/*
|
||||
* Some syscall entry functions on powerpc start with "ppc_" (fork and clone,
|
||||
* for instance) or ppc32_/ppc64_. We should also match the sys_ variant with
|
||||
* those.
|
||||
*/
|
||||
#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
|
||||
#ifdef PPC64_ELF_ABI_v1
|
||||
static inline bool arch_syscall_match_sym_name(const char *sym, const char *name)
|
||||
{
|
||||
/*
|
||||
* Compare the symbol name with the system call name. Skip the .sys or .SyS
|
||||
* prefix from the symbol name and the sys prefix from the system call name and
|
||||
* just match the rest. This is only needed on ppc64 since symbol names on
|
||||
* 32bit do not start with a period so the generic function will work.
|
||||
*/
|
||||
return !strcmp(sym + 4, name + 3);
|
||||
/* We need to skip past the initial dot, and the __se_sys alias */
|
||||
return !strcmp(sym + 1, name) ||
|
||||
(!strncmp(sym, ".__se_sys", 9) && !strcmp(sym + 6, name)) ||
|
||||
(!strncmp(sym, ".ppc_", 5) && !strcmp(sym + 5, name + 4)) ||
|
||||
(!strncmp(sym, ".ppc32_", 7) && !strcmp(sym + 7, name + 4)) ||
|
||||
(!strncmp(sym, ".ppc64_", 7) && !strcmp(sym + 7, name + 4));
|
||||
}
|
||||
#else
|
||||
static inline bool arch_syscall_match_sym_name(const char *sym, const char *name)
|
||||
{
|
||||
return !strcmp(sym, name) ||
|
||||
(!strncmp(sym, "__se_sys", 8) && !strcmp(sym + 5, name)) ||
|
||||
(!strncmp(sym, "ppc_", 4) && !strcmp(sym + 4, name + 4)) ||
|
||||
(!strncmp(sym, "ppc32_", 6) && !strcmp(sym + 6, name + 4)) ||
|
||||
(!strncmp(sym, "ppc64_", 6) && !strcmp(sym + 6, name + 4));
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_FTRACE_SYSCALLS && !__ASSEMBLY__ */
|
||||
|
|
|
|||
|
|
@ -165,7 +165,6 @@ struct paca_struct {
|
|||
u64 saved_msr; /* MSR saved here by enter_rtas */
|
||||
u16 trap_save; /* Used when bad stack is encountered */
|
||||
u8 irq_soft_mask; /* mask for irq soft masking */
|
||||
u8 soft_enabled; /* irq soft-enable flag */
|
||||
u8 irq_happened; /* irq happened while soft-disabled */
|
||||
u8 io_sync; /* writel() needs spin_unlock sync */
|
||||
u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
|
||||
|
|
|
|||
|
|
@ -91,6 +91,7 @@ extern int start_topology_update(void);
|
|||
extern int stop_topology_update(void);
|
||||
extern int prrn_is_enabled(void);
|
||||
extern int find_and_online_cpu_nid(int cpu);
|
||||
extern int timed_topology_update(int nsecs);
|
||||
#else
|
||||
static inline int start_topology_update(void)
|
||||
{
|
||||
|
|
@ -108,16 +109,12 @@ static inline int find_and_online_cpu_nid(int cpu)
|
|||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int timed_topology_update(int nsecs)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_NUMA && CONFIG_PPC_SPLPAR */
|
||||
|
||||
#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_NEED_MULTIPLE_NODES)
|
||||
#if defined(CONFIG_PPC_SPLPAR)
|
||||
extern int timed_topology_update(int nsecs);
|
||||
#else
|
||||
#define timed_topology_update(nsecs)
|
||||
#endif /* CONFIG_PPC_SPLPAR */
|
||||
#endif /* CONFIG_HOTPLUG_CPU || CONFIG_NEED_MULTIPLE_NODES */
|
||||
|
||||
#include <asm-generic/topology.h>
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ config SUPERH
|
|||
select HAVE_IDE if HAS_IOPORT_MAP
|
||||
select HAVE_MEMBLOCK
|
||||
select HAVE_MEMBLOCK_NODE_MAP
|
||||
select NO_BOOTMEM
|
||||
select ARCH_DISCARD_MEMBLOCK
|
||||
select HAVE_OPROFILE
|
||||
select HAVE_GENERIC_DMA_COHERENT
|
||||
|
|
|
|||
|
|
@ -43,7 +43,11 @@ void __ref cpu_probe(void)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_J2)
|
||||
#if defined(CONFIG_SMP)
|
||||
unsigned cpu = hard_smp_processor_id();
|
||||
#else
|
||||
unsigned cpu = 0;
|
||||
#endif
|
||||
if (cpu == 0) of_scan_flat_dt(scan_cache, NULL);
|
||||
if (j2_ccr_base) __raw_writel(0x80000303, j2_ccr_base + 4*cpu);
|
||||
if (cpu != 0) return;
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
#include <linux/ioport.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/initrd.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/console.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/utsname.h>
|
||||
|
|
|
|||
|
|
@ -59,7 +59,9 @@ void *dma_generic_alloc_coherent(struct device *dev, size_t size,
|
|||
|
||||
split_page(pfn_to_page(virt_to_phys(ret) >> PAGE_SHIFT), order);
|
||||
|
||||
*dma_handle = virt_to_phys(ret) - PFN_PHYS(dev->dma_pfn_offset);
|
||||
*dma_handle = virt_to_phys(ret);
|
||||
if (!WARN_ON(!dev))
|
||||
*dma_handle -= PFN_PHYS(dev->dma_pfn_offset);
|
||||
|
||||
return ret_nocache;
|
||||
}
|
||||
|
|
@ -69,9 +71,12 @@ void dma_generic_free_coherent(struct device *dev, size_t size,
|
|||
unsigned long attrs)
|
||||
{
|
||||
int order = get_order(size);
|
||||
unsigned long pfn = (dma_handle >> PAGE_SHIFT) + dev->dma_pfn_offset;
|
||||
unsigned long pfn = dma_handle >> PAGE_SHIFT;
|
||||
int k;
|
||||
|
||||
if (!WARN_ON(!dev))
|
||||
pfn += dev->dma_pfn_offset;
|
||||
|
||||
for (k = 0; k < (1 << order); k++)
|
||||
__free_pages(pfn_to_page(pfn + k), 0);
|
||||
|
||||
|
|
@ -143,7 +148,7 @@ int __init platform_resource_setup_memory(struct platform_device *pdev,
|
|||
if (!memsize)
|
||||
return 0;
|
||||
|
||||
buf = dma_alloc_coherent(NULL, memsize, &dma_handle, GFP_KERNEL);
|
||||
buf = dma_alloc_coherent(&pdev->dev, memsize, &dma_handle, GFP_KERNEL);
|
||||
if (!buf) {
|
||||
pr_warning("%s: unable to allocate memory\n", name);
|
||||
return -ENOMEM;
|
||||
|
|
|
|||
|
|
@ -211,59 +211,15 @@ void __init allocate_pgdat(unsigned int nid)
|
|||
|
||||
NODE_DATA(nid) = __va(phys);
|
||||
memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
|
||||
|
||||
NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
|
||||
#endif
|
||||
|
||||
NODE_DATA(nid)->node_start_pfn = start_pfn;
|
||||
NODE_DATA(nid)->node_spanned_pages = end_pfn - start_pfn;
|
||||
}
|
||||
|
||||
static void __init bootmem_init_one_node(unsigned int nid)
|
||||
{
|
||||
unsigned long total_pages, paddr;
|
||||
unsigned long end_pfn;
|
||||
struct pglist_data *p;
|
||||
|
||||
p = NODE_DATA(nid);
|
||||
|
||||
/* Nothing to do.. */
|
||||
if (!p->node_spanned_pages)
|
||||
return;
|
||||
|
||||
end_pfn = pgdat_end_pfn(p);
|
||||
|
||||
total_pages = bootmem_bootmap_pages(p->node_spanned_pages);
|
||||
|
||||
paddr = memblock_alloc(total_pages << PAGE_SHIFT, PAGE_SIZE);
|
||||
if (!paddr)
|
||||
panic("Can't allocate bootmap for nid[%d]\n", nid);
|
||||
|
||||
init_bootmem_node(p, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
|
||||
|
||||
free_bootmem_with_active_regions(nid, end_pfn);
|
||||
|
||||
/*
|
||||
* XXX Handle initial reservations for the system memory node
|
||||
* only for the moment, we'll refactor this later for handling
|
||||
* reservations in other nodes.
|
||||
*/
|
||||
if (nid == 0) {
|
||||
struct memblock_region *reg;
|
||||
|
||||
/* Reserve the sections we're already using. */
|
||||
for_each_memblock(reserved, reg) {
|
||||
reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
|
||||
}
|
||||
}
|
||||
|
||||
sparse_memory_present_with_active_regions(nid);
|
||||
}
|
||||
|
||||
static void __init do_init_bootmem(void)
|
||||
{
|
||||
struct memblock_region *reg;
|
||||
int i;
|
||||
|
||||
/* Add active regions with valid PFNs. */
|
||||
for_each_memblock(memory, reg) {
|
||||
|
|
@ -279,9 +235,12 @@ static void __init do_init_bootmem(void)
|
|||
|
||||
plat_mem_setup();
|
||||
|
||||
for_each_online_node(i)
|
||||
bootmem_init_one_node(i);
|
||||
for_each_memblock(memory, reg) {
|
||||
int nid = memblock_get_region_node(reg);
|
||||
|
||||
memory_present(nid, memblock_region_memory_base_pfn(reg),
|
||||
memblock_region_memory_end_pfn(reg));
|
||||
}
|
||||
sparse_init();
|
||||
}
|
||||
|
||||
|
|
@ -322,7 +281,6 @@ void __init paging_init(void)
|
|||
{
|
||||
unsigned long max_zone_pfns[MAX_NR_ZONES];
|
||||
unsigned long vaddr, end;
|
||||
int nid;
|
||||
|
||||
sh_mv.mv_mem_init();
|
||||
|
||||
|
|
@ -377,21 +335,7 @@ void __init paging_init(void)
|
|||
kmap_coherent_init();
|
||||
|
||||
memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
|
||||
|
||||
for_each_online_node(nid) {
|
||||
pg_data_t *pgdat = NODE_DATA(nid);
|
||||
unsigned long low, start_pfn;
|
||||
|
||||
start_pfn = pgdat->bdata->node_min_pfn;
|
||||
low = pgdat->bdata->node_low_pfn;
|
||||
|
||||
if (max_zone_pfns[ZONE_NORMAL] < low)
|
||||
max_zone_pfns[ZONE_NORMAL] = low;
|
||||
|
||||
printk("Node %u: start_pfn = 0x%lx, low = 0x%lx\n",
|
||||
nid, start_pfn, low);
|
||||
}
|
||||
|
||||
max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
|
||||
free_area_init_nodes(max_zone_pfns);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@
|
|||
* for more details.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/numa.h>
|
||||
|
|
@ -26,9 +25,7 @@ EXPORT_SYMBOL_GPL(node_data);
|
|||
*/
|
||||
void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end)
|
||||
{
|
||||
unsigned long bootmap_pages;
|
||||
unsigned long start_pfn, end_pfn;
|
||||
unsigned long bootmem_paddr;
|
||||
|
||||
/* Don't allow bogus node assignment */
|
||||
BUG_ON(nid >= MAX_NUMNODES || nid <= 0);
|
||||
|
|
@ -48,25 +45,9 @@ void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end)
|
|||
SMP_CACHE_BYTES, end));
|
||||
memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
|
||||
|
||||
NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
|
||||
NODE_DATA(nid)->node_start_pfn = start_pfn;
|
||||
NODE_DATA(nid)->node_spanned_pages = end_pfn - start_pfn;
|
||||
|
||||
/* Node-local bootmap */
|
||||
bootmap_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
|
||||
bootmem_paddr = memblock_alloc_base(bootmap_pages << PAGE_SHIFT,
|
||||
PAGE_SIZE, end);
|
||||
init_bootmem_node(NODE_DATA(nid), bootmem_paddr >> PAGE_SHIFT,
|
||||
start_pfn, end_pfn);
|
||||
|
||||
free_bootmem_with_active_regions(nid, end_pfn);
|
||||
|
||||
/* Reserve the pgdat and bootmap space with the bootmem allocator */
|
||||
reserve_bootmem_node(NODE_DATA(nid), start_pfn << PAGE_SHIFT,
|
||||
sizeof(struct pglist_data), BOOTMEM_DEFAULT);
|
||||
reserve_bootmem_node(NODE_DATA(nid), bootmem_paddr,
|
||||
bootmap_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
|
||||
|
||||
/* It's up */
|
||||
node_set_online(nid);
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
#include "../vdso-fakesections.c"
|
||||
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/cpu.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/nospec.h>
|
||||
|
||||
#include <asm/apic.h>
|
||||
#include <asm/stacktrace.h>
|
||||
|
|
@ -304,17 +305,20 @@ set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
|
|||
|
||||
config = attr->config;
|
||||
|
||||
cache_type = (config >> 0) & 0xff;
|
||||
cache_type = (config >> 0) & 0xff;
|
||||
if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
|
||||
return -EINVAL;
|
||||
cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
|
||||
|
||||
cache_op = (config >> 8) & 0xff;
|
||||
if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
|
||||
return -EINVAL;
|
||||
cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
|
||||
|
||||
cache_result = (config >> 16) & 0xff;
|
||||
if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
|
||||
return -EINVAL;
|
||||
cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
|
||||
|
||||
val = hw_cache_event_ids[cache_type][cache_op][cache_result];
|
||||
|
||||
|
|
@ -421,6 +425,8 @@ int x86_setup_perfctr(struct perf_event *event)
|
|||
if (attr->config >= x86_pmu.max_events)
|
||||
return -EINVAL;
|
||||
|
||||
attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
|
||||
|
||||
/*
|
||||
* The generic map:
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -92,6 +92,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/perf_event.h>
|
||||
#include <linux/nospec.h>
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/intel-family.h>
|
||||
#include "../perf_event.h"
|
||||
|
|
@ -302,6 +303,7 @@ static int cstate_pmu_event_init(struct perf_event *event)
|
|||
} else if (event->pmu == &cstate_pkg_pmu) {
|
||||
if (cfg >= PERF_CSTATE_PKG_EVENT_MAX)
|
||||
return -EINVAL;
|
||||
cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_PKG_EVENT_MAX);
|
||||
if (!pkg_msr[cfg].attr)
|
||||
return -EINVAL;
|
||||
event->hw.event_base = pkg_msr[cfg].msr;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include <linux/perf_event.h>
|
||||
#include <linux/nospec.h>
|
||||
#include <asm/intel-family.h>
|
||||
|
||||
enum perf_msr_id {
|
||||
|
|
@ -158,9 +159,6 @@ static int msr_event_init(struct perf_event *event)
|
|||
if (event->attr.type != event->pmu->type)
|
||||
return -ENOENT;
|
||||
|
||||
if (cfg >= PERF_MSR_EVENT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
/* unsupported modes and filters */
|
||||
if (event->attr.exclude_user ||
|
||||
event->attr.exclude_kernel ||
|
||||
|
|
@ -171,6 +169,11 @@ static int msr_event_init(struct perf_event *event)
|
|||
event->attr.sample_period) /* no sampling */
|
||||
return -EINVAL;
|
||||
|
||||
if (cfg >= PERF_MSR_EVENT_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
|
||||
|
||||
if (!msr[cfg].attr)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
|||
|
|
@ -848,6 +848,11 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
|
|||
c->x86_power = edx;
|
||||
}
|
||||
|
||||
if (c->extended_cpuid_level >= 0x80000008) {
|
||||
cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
|
||||
c->x86_capability[CPUID_8000_0008_EBX] = ebx;
|
||||
}
|
||||
|
||||
if (c->extended_cpuid_level >= 0x8000000a)
|
||||
c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
|
||||
|
||||
|
|
@ -871,7 +876,6 @@ static void get_cpu_address_sizes(struct cpuinfo_x86 *c)
|
|||
|
||||
c->x86_virt_bits = (eax >> 8) & 0xff;
|
||||
c->x86_phys_bits = eax & 0xff;
|
||||
c->x86_capability[CPUID_8000_0008_EBX] = ebx;
|
||||
}
|
||||
#ifdef CONFIG_X86_32
|
||||
else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
|
||||
|
|
|
|||
|
|
@ -1067,6 +1067,7 @@ static struct clocksource clocksource_tsc_early = {
|
|||
.resume = tsc_resume,
|
||||
.mark_unstable = tsc_cs_mark_unstable,
|
||||
.tick_stable = tsc_cs_tick_stable,
|
||||
.list = LIST_HEAD_INIT(clocksource_tsc_early.list),
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -1086,6 +1087,7 @@ static struct clocksource clocksource_tsc = {
|
|||
.resume = tsc_resume,
|
||||
.mark_unstable = tsc_cs_mark_unstable,
|
||||
.tick_stable = tsc_cs_tick_stable,
|
||||
.list = LIST_HEAD_INIT(clocksource_tsc.list),
|
||||
};
|
||||
|
||||
void mark_tsc_unstable(char *reason)
|
||||
|
|
@ -1098,13 +1100,9 @@ void mark_tsc_unstable(char *reason)
|
|||
clear_sched_clock_stable();
|
||||
disable_sched_clock_irqtime();
|
||||
pr_info("Marking TSC unstable due to %s\n", reason);
|
||||
/* Change only the rating, when not registered */
|
||||
if (clocksource_tsc.mult) {
|
||||
clocksource_mark_unstable(&clocksource_tsc);
|
||||
} else {
|
||||
clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
|
||||
clocksource_tsc.rating = 0;
|
||||
}
|
||||
|
||||
clocksource_mark_unstable(&clocksource_tsc_early);
|
||||
clocksource_mark_unstable(&clocksource_tsc);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL_GPL(mark_tsc_unstable);
|
||||
|
|
@ -1244,7 +1242,7 @@ static void tsc_refine_calibration_work(struct work_struct *work)
|
|||
|
||||
/* Don't bother refining TSC on unstable systems */
|
||||
if (tsc_unstable)
|
||||
return;
|
||||
goto unreg;
|
||||
|
||||
/*
|
||||
* Since the work is started early in boot, we may be
|
||||
|
|
@ -1297,11 +1295,12 @@ static void tsc_refine_calibration_work(struct work_struct *work)
|
|||
|
||||
out:
|
||||
if (tsc_unstable)
|
||||
return;
|
||||
goto unreg;
|
||||
|
||||
if (boot_cpu_has(X86_FEATURE_ART))
|
||||
art_related_clocksource = &clocksource_tsc;
|
||||
clocksource_register_khz(&clocksource_tsc, tsc_khz);
|
||||
unreg:
|
||||
clocksource_unregister(&clocksource_tsc_early);
|
||||
}
|
||||
|
||||
|
|
@ -1311,8 +1310,8 @@ static int __init init_tsc_clocksource(void)
|
|||
if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz)
|
||||
return 0;
|
||||
|
||||
if (check_tsc_unstable())
|
||||
return 0;
|
||||
if (tsc_unstable)
|
||||
goto unreg;
|
||||
|
||||
if (tsc_clocksource_reliable)
|
||||
clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
|
||||
|
|
@ -1328,6 +1327,7 @@ static int __init init_tsc_clocksource(void)
|
|||
if (boot_cpu_has(X86_FEATURE_ART))
|
||||
art_related_clocksource = &clocksource_tsc;
|
||||
clocksource_register_khz(&clocksource_tsc, tsc_khz);
|
||||
unreg:
|
||||
clocksource_unregister(&clocksource_tsc_early);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1463,23 +1463,6 @@ static void start_sw_tscdeadline(struct kvm_lapic *apic)
|
|||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void start_sw_period(struct kvm_lapic *apic)
|
||||
{
|
||||
if (!apic->lapic_timer.period)
|
||||
return;
|
||||
|
||||
if (apic_lvtt_oneshot(apic) &&
|
||||
ktime_after(ktime_get(),
|
||||
apic->lapic_timer.target_expiration)) {
|
||||
apic_timer_expired(apic);
|
||||
return;
|
||||
}
|
||||
|
||||
hrtimer_start(&apic->lapic_timer.timer,
|
||||
apic->lapic_timer.target_expiration,
|
||||
HRTIMER_MODE_ABS_PINNED);
|
||||
}
|
||||
|
||||
static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
|
||||
{
|
||||
ktime_t now, remaining;
|
||||
|
|
@ -1546,6 +1529,26 @@ static void advance_periodic_target_expiration(struct kvm_lapic *apic)
|
|||
apic->lapic_timer.period);
|
||||
}
|
||||
|
||||
static void start_sw_period(struct kvm_lapic *apic)
|
||||
{
|
||||
if (!apic->lapic_timer.period)
|
||||
return;
|
||||
|
||||
if (ktime_after(ktime_get(),
|
||||
apic->lapic_timer.target_expiration)) {
|
||||
apic_timer_expired(apic);
|
||||
|
||||
if (apic_lvtt_oneshot(apic))
|
||||
return;
|
||||
|
||||
advance_periodic_target_expiration(apic);
|
||||
}
|
||||
|
||||
hrtimer_start(&apic->lapic_timer.timer,
|
||||
apic->lapic_timer.target_expiration,
|
||||
HRTIMER_MODE_ABS_PINNED);
|
||||
}
|
||||
|
||||
bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
if (!lapic_in_kernel(vcpu))
|
||||
|
|
|
|||
|
|
@ -65,6 +65,19 @@ static void __init xen_hvm_init_mem_mapping(void)
|
|||
{
|
||||
early_memunmap(HYPERVISOR_shared_info, PAGE_SIZE);
|
||||
HYPERVISOR_shared_info = __va(PFN_PHYS(shared_info_pfn));
|
||||
|
||||
/*
|
||||
* The virtual address of the shared_info page has changed, so
|
||||
* the vcpu_info pointer for VCPU 0 is now stale.
|
||||
*
|
||||
* The prepare_boot_cpu callback will re-initialize it via
|
||||
* xen_vcpu_setup, but we can't rely on that to be called for
|
||||
* old Xen versions (xen_have_vector_callback == 0).
|
||||
*
|
||||
* It is, in any case, bad to have a stale vcpu_info pointer
|
||||
* so reset it now.
|
||||
*/
|
||||
xen_vcpu_info_reset(0);
|
||||
}
|
||||
|
||||
static void __init init_hvm_pv_info(void)
|
||||
|
|
|
|||
|
|
@ -421,45 +421,33 @@ static void xen_load_gdt(const struct desc_ptr *dtr)
|
|||
{
|
||||
unsigned long va = dtr->address;
|
||||
unsigned int size = dtr->size + 1;
|
||||
unsigned pages = DIV_ROUND_UP(size, PAGE_SIZE);
|
||||
unsigned long frames[pages];
|
||||
int f;
|
||||
unsigned long pfn, mfn;
|
||||
int level;
|
||||
pte_t *ptep;
|
||||
void *virt;
|
||||
|
||||
/*
|
||||
* A GDT can be up to 64k in size, which corresponds to 8192
|
||||
* 8-byte entries, or 16 4k pages..
|
||||
*/
|
||||
|
||||
BUG_ON(size > 65536);
|
||||
/* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */
|
||||
BUG_ON(size > PAGE_SIZE);
|
||||
BUG_ON(va & ~PAGE_MASK);
|
||||
|
||||
for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) {
|
||||
int level;
|
||||
pte_t *ptep;
|
||||
unsigned long pfn, mfn;
|
||||
void *virt;
|
||||
/*
|
||||
* The GDT is per-cpu and is in the percpu data area.
|
||||
* That can be virtually mapped, so we need to do a
|
||||
* page-walk to get the underlying MFN for the
|
||||
* hypercall. The page can also be in the kernel's
|
||||
* linear range, so we need to RO that mapping too.
|
||||
*/
|
||||
ptep = lookup_address(va, &level);
|
||||
BUG_ON(ptep == NULL);
|
||||
|
||||
/*
|
||||
* The GDT is per-cpu and is in the percpu data area.
|
||||
* That can be virtually mapped, so we need to do a
|
||||
* page-walk to get the underlying MFN for the
|
||||
* hypercall. The page can also be in the kernel's
|
||||
* linear range, so we need to RO that mapping too.
|
||||
*/
|
||||
ptep = lookup_address(va, &level);
|
||||
BUG_ON(ptep == NULL);
|
||||
pfn = pte_pfn(*ptep);
|
||||
mfn = pfn_to_mfn(pfn);
|
||||
virt = __va(PFN_PHYS(pfn));
|
||||
|
||||
pfn = pte_pfn(*ptep);
|
||||
mfn = pfn_to_mfn(pfn);
|
||||
virt = __va(PFN_PHYS(pfn));
|
||||
make_lowmem_page_readonly((void *)va);
|
||||
make_lowmem_page_readonly(virt);
|
||||
|
||||
frames[f] = mfn;
|
||||
|
||||
make_lowmem_page_readonly((void *)va);
|
||||
make_lowmem_page_readonly(virt);
|
||||
}
|
||||
|
||||
if (HYPERVISOR_set_gdt(frames, size / sizeof(struct desc_struct)))
|
||||
if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct)))
|
||||
BUG();
|
||||
}
|
||||
|
||||
|
|
@ -470,34 +458,22 @@ static void __init xen_load_gdt_boot(const struct desc_ptr *dtr)
|
|||
{
|
||||
unsigned long va = dtr->address;
|
||||
unsigned int size = dtr->size + 1;
|
||||
unsigned pages = DIV_ROUND_UP(size, PAGE_SIZE);
|
||||
unsigned long frames[pages];
|
||||
int f;
|
||||
unsigned long pfn, mfn;
|
||||
pte_t pte;
|
||||
|
||||
/*
|
||||
* A GDT can be up to 64k in size, which corresponds to 8192
|
||||
* 8-byte entries, or 16 4k pages..
|
||||
*/
|
||||
|
||||
BUG_ON(size > 65536);
|
||||
/* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */
|
||||
BUG_ON(size > PAGE_SIZE);
|
||||
BUG_ON(va & ~PAGE_MASK);
|
||||
|
||||
for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) {
|
||||
pte_t pte;
|
||||
unsigned long pfn, mfn;
|
||||
pfn = virt_to_pfn(va);
|
||||
mfn = pfn_to_mfn(pfn);
|
||||
|
||||
pfn = virt_to_pfn(va);
|
||||
mfn = pfn_to_mfn(pfn);
|
||||
pte = pfn_pte(pfn, PAGE_KERNEL_RO);
|
||||
|
||||
pte = pfn_pte(pfn, PAGE_KERNEL_RO);
|
||||
if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
|
||||
BUG();
|
||||
|
||||
if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
|
||||
BUG();
|
||||
|
||||
frames[f] = mfn;
|
||||
}
|
||||
|
||||
if (HYPERVISOR_set_gdt(frames, size / sizeof(struct desc_struct)))
|
||||
if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct)))
|
||||
BUG();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -95,18 +95,15 @@ static void blk_mq_check_inflight(struct blk_mq_hw_ctx *hctx,
|
|||
{
|
||||
struct mq_inflight *mi = priv;
|
||||
|
||||
if (blk_mq_rq_state(rq) == MQ_RQ_IN_FLIGHT) {
|
||||
/*
|
||||
* index[0] counts the specific partition that was asked
|
||||
* for. index[1] counts the ones that are active on the
|
||||
* whole device, so increment that if mi->part is indeed
|
||||
* a partition, and not a whole device.
|
||||
*/
|
||||
if (rq->part == mi->part)
|
||||
mi->inflight[0]++;
|
||||
if (mi->part->partno)
|
||||
mi->inflight[1]++;
|
||||
}
|
||||
/*
|
||||
* index[0] counts the specific partition that was asked for. index[1]
|
||||
* counts the ones that are active on the whole device, so increment
|
||||
* that if mi->part is indeed a partition, and not a whole device.
|
||||
*/
|
||||
if (rq->part == mi->part)
|
||||
mi->inflight[0]++;
|
||||
if (mi->part->partno)
|
||||
mi->inflight[1]++;
|
||||
}
|
||||
|
||||
void blk_mq_in_flight(struct request_queue *q, struct hd_struct *part,
|
||||
|
|
@ -118,6 +115,25 @@ void blk_mq_in_flight(struct request_queue *q, struct hd_struct *part,
|
|||
blk_mq_queue_tag_busy_iter(q, blk_mq_check_inflight, &mi);
|
||||
}
|
||||
|
||||
static void blk_mq_check_inflight_rw(struct blk_mq_hw_ctx *hctx,
|
||||
struct request *rq, void *priv,
|
||||
bool reserved)
|
||||
{
|
||||
struct mq_inflight *mi = priv;
|
||||
|
||||
if (rq->part == mi->part)
|
||||
mi->inflight[rq_data_dir(rq)]++;
|
||||
}
|
||||
|
||||
void blk_mq_in_flight_rw(struct request_queue *q, struct hd_struct *part,
|
||||
unsigned int inflight[2])
|
||||
{
|
||||
struct mq_inflight mi = { .part = part, .inflight = inflight, };
|
||||
|
||||
inflight[0] = inflight[1] = 0;
|
||||
blk_mq_queue_tag_busy_iter(q, blk_mq_check_inflight_rw, &mi);
|
||||
}
|
||||
|
||||
void blk_freeze_queue_start(struct request_queue *q)
|
||||
{
|
||||
int freeze_depth;
|
||||
|
|
|
|||
|
|
@ -188,7 +188,9 @@ static inline bool blk_mq_hw_queue_mapped(struct blk_mq_hw_ctx *hctx)
|
|||
}
|
||||
|
||||
void blk_mq_in_flight(struct request_queue *q, struct hd_struct *part,
|
||||
unsigned int inflight[2]);
|
||||
unsigned int inflight[2]);
|
||||
void blk_mq_in_flight_rw(struct request_queue *q, struct hd_struct *part,
|
||||
unsigned int inflight[2]);
|
||||
|
||||
static inline void blk_mq_put_dispatch_budget(struct blk_mq_hw_ctx *hctx)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -82,6 +82,18 @@ void part_in_flight(struct request_queue *q, struct hd_struct *part,
|
|||
}
|
||||
}
|
||||
|
||||
void part_in_flight_rw(struct request_queue *q, struct hd_struct *part,
|
||||
unsigned int inflight[2])
|
||||
{
|
||||
if (q->mq_ops) {
|
||||
blk_mq_in_flight_rw(q, part, inflight);
|
||||
return;
|
||||
}
|
||||
|
||||
inflight[0] = atomic_read(&part->in_flight[0]);
|
||||
inflight[1] = atomic_read(&part->in_flight[1]);
|
||||
}
|
||||
|
||||
struct hd_struct *__disk_get_part(struct gendisk *disk, int partno)
|
||||
{
|
||||
struct disk_part_tbl *ptbl = rcu_dereference(disk->part_tbl);
|
||||
|
|
|
|||
|
|
@ -145,13 +145,15 @@ ssize_t part_stat_show(struct device *dev,
|
|||
jiffies_to_msecs(part_stat_read(p, time_in_queue)));
|
||||
}
|
||||
|
||||
ssize_t part_inflight_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
ssize_t part_inflight_show(struct device *dev, struct device_attribute *attr,
|
||||
char *buf)
|
||||
{
|
||||
struct hd_struct *p = dev_to_part(dev);
|
||||
struct request_queue *q = part_to_disk(p)->queue;
|
||||
unsigned int inflight[2];
|
||||
|
||||
return sprintf(buf, "%8u %8u\n", atomic_read(&p->in_flight[0]),
|
||||
atomic_read(&p->in_flight[1]));
|
||||
part_in_flight_rw(q, p, inflight);
|
||||
return sprintf(buf, "%8u %8u\n", inflight[0], inflight[1]);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FAIL_MAKE_REQUEST
|
||||
|
|
|
|||
|
|
@ -698,7 +698,7 @@ static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
|
|||
|
||||
DPRINTK("ENTER\n");
|
||||
|
||||
ahci_stop_engine(ap);
|
||||
hpriv->stop_engine(ap);
|
||||
|
||||
rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
|
||||
deadline, &online, NULL);
|
||||
|
|
@ -724,7 +724,7 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
|
|||
bool online;
|
||||
int rc;
|
||||
|
||||
ahci_stop_engine(ap);
|
||||
hpriv->stop_engine(ap);
|
||||
|
||||
/* clear D2H reception area to properly wait for D2H FIS */
|
||||
ata_tf_init(link->device, &tf);
|
||||
|
|
@ -788,7 +788,7 @@ static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
|
|||
|
||||
DPRINTK("ENTER\n");
|
||||
|
||||
ahci_stop_engine(ap);
|
||||
hpriv->stop_engine(ap);
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
u16 val;
|
||||
|
|
|
|||
|
|
@ -350,7 +350,6 @@ struct ahci_host_priv {
|
|||
u32 em_msg_type; /* EM message type */
|
||||
bool got_runtime_pm; /* Did we do pm_runtime_get? */
|
||||
struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
|
||||
struct reset_control *rsts; /* Optional */
|
||||
struct regulator **target_pwrs; /* Optional */
|
||||
/*
|
||||
* If platform uses PHYs. There is a 1:1 relation between the port number and
|
||||
|
|
@ -366,6 +365,13 @@ struct ahci_host_priv {
|
|||
* be overridden anytime before the host is activated.
|
||||
*/
|
||||
void (*start_engine)(struct ata_port *ap);
|
||||
/*
|
||||
* Optional ahci_stop_engine override, if not set this gets set to the
|
||||
* default ahci_stop_engine during ahci_save_initial_config, this can
|
||||
* be overridden anytime before the host is activated.
|
||||
*/
|
||||
int (*stop_engine)(struct ata_port *ap);
|
||||
|
||||
irqreturn_t (*irq_handler)(int irq, void *dev_instance);
|
||||
|
||||
/* only required for per-port MSI(-X) support */
|
||||
|
|
|
|||
|
|
@ -62,6 +62,60 @@ static void ahci_mvebu_regret_option(struct ahci_host_priv *hpriv)
|
|||
writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
|
||||
}
|
||||
|
||||
/**
|
||||
* ahci_mvebu_stop_engine
|
||||
*
|
||||
* @ap: Target ata port
|
||||
*
|
||||
* Errata Ref#226 - SATA Disk HOT swap issue when connected through
|
||||
* Port Multiplier in FIS-based Switching mode.
|
||||
*
|
||||
* To avoid the issue, according to design, the bits[11:8, 0] of
|
||||
* register PxFBS are cleared when Port Command and Status (0x18) bit[0]
|
||||
* changes its value from 1 to 0, i.e. falling edge of Port
|
||||
* Command and Status bit[0] sends PULSE that resets PxFBS
|
||||
* bits[11:8; 0].
|
||||
*
|
||||
* This function is used to override function of "ahci_stop_engine"
|
||||
* from libahci.c by adding the mvebu work around(WA) to save PxFBS
|
||||
* value before the PxCMD ST write of 0, then restore PxFBS value.
|
||||
*
|
||||
* Return: 0 on success; Error code otherwise.
|
||||
*/
|
||||
int ahci_mvebu_stop_engine(struct ata_port *ap)
|
||||
{
|
||||
void __iomem *port_mmio = ahci_port_base(ap);
|
||||
u32 tmp, port_fbs;
|
||||
|
||||
tmp = readl(port_mmio + PORT_CMD);
|
||||
|
||||
/* check if the HBA is idle */
|
||||
if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
|
||||
return 0;
|
||||
|
||||
/* save the port PxFBS register for later restore */
|
||||
port_fbs = readl(port_mmio + PORT_FBS);
|
||||
|
||||
/* setting HBA to idle */
|
||||
tmp &= ~PORT_CMD_START;
|
||||
writel(tmp, port_mmio + PORT_CMD);
|
||||
|
||||
/*
|
||||
* bit #15 PxCMD signal doesn't clear PxFBS,
|
||||
* restore the PxFBS register right after clearing the PxCMD ST,
|
||||
* no need to wait for the PxCMD bit #15.
|
||||
*/
|
||||
writel(port_fbs, port_mmio + PORT_FBS);
|
||||
|
||||
/* wait for engine to stop. This could be as long as 500 msec */
|
||||
tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
|
||||
PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
|
||||
if (tmp & PORT_CMD_LIST_ON)
|
||||
return -EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int ahci_mvebu_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
{
|
||||
|
|
@ -112,6 +166,8 @@ static int ahci_mvebu_probe(struct platform_device *pdev)
|
|||
if (rc)
|
||||
return rc;
|
||||
|
||||
hpriv->stop_engine = ahci_mvebu_stop_engine;
|
||||
|
||||
if (of_device_is_compatible(pdev->dev.of_node,
|
||||
"marvell,armada-380-ahci")) {
|
||||
dram = mv_mbus_dram_info();
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@ static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
|
|||
|
||||
DPRINTK("ENTER\n");
|
||||
|
||||
ahci_stop_engine(ap);
|
||||
hpriv->stop_engine(ap);
|
||||
|
||||
/*
|
||||
* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
|
||||
|
|
|
|||
|
|
@ -165,7 +165,7 @@ static int xgene_ahci_restart_engine(struct ata_port *ap)
|
|||
PORT_CMD_ISSUE, 0x0, 1, 100))
|
||||
return -EBUSY;
|
||||
|
||||
ahci_stop_engine(ap);
|
||||
hpriv->stop_engine(ap);
|
||||
ahci_start_fis_rx(ap);
|
||||
|
||||
/*
|
||||
|
|
@ -421,7 +421,7 @@ static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
|
|||
portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
|
||||
portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
|
||||
|
||||
ahci_stop_engine(ap);
|
||||
hpriv->stop_engine(ap);
|
||||
|
||||
rc = xgene_ahci_do_hardreset(link, deadline, &online);
|
||||
|
||||
|
|
|
|||
|
|
@ -560,6 +560,9 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
|
|||
if (!hpriv->start_engine)
|
||||
hpriv->start_engine = ahci_start_engine;
|
||||
|
||||
if (!hpriv->stop_engine)
|
||||
hpriv->stop_engine = ahci_stop_engine;
|
||||
|
||||
if (!hpriv->irq_handler)
|
||||
hpriv->irq_handler = ahci_single_level_irq_intr;
|
||||
}
|
||||
|
|
@ -897,9 +900,10 @@ static void ahci_start_port(struct ata_port *ap)
|
|||
static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
|
||||
{
|
||||
int rc;
|
||||
struct ahci_host_priv *hpriv = ap->host->private_data;
|
||||
|
||||
/* disable DMA */
|
||||
rc = ahci_stop_engine(ap);
|
||||
rc = hpriv->stop_engine(ap);
|
||||
if (rc) {
|
||||
*emsg = "failed to stop engine";
|
||||
return rc;
|
||||
|
|
@ -1310,7 +1314,7 @@ int ahci_kick_engine(struct ata_port *ap)
|
|||
int busy, rc;
|
||||
|
||||
/* stop engine */
|
||||
rc = ahci_stop_engine(ap);
|
||||
rc = hpriv->stop_engine(ap);
|
||||
if (rc)
|
||||
goto out_restart;
|
||||
|
||||
|
|
@ -1549,7 +1553,7 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
|
|||
|
||||
DPRINTK("ENTER\n");
|
||||
|
||||
ahci_stop_engine(ap);
|
||||
hpriv->stop_engine(ap);
|
||||
|
||||
/* clear D2H reception area to properly wait for D2H FIS */
|
||||
ata_tf_init(link->device, &tf);
|
||||
|
|
@ -2075,14 +2079,14 @@ void ahci_error_handler(struct ata_port *ap)
|
|||
|
||||
if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
|
||||
/* restart engine */
|
||||
ahci_stop_engine(ap);
|
||||
hpriv->stop_engine(ap);
|
||||
hpriv->start_engine(ap);
|
||||
}
|
||||
|
||||
sata_pmp_error_handler(ap);
|
||||
|
||||
if (!ata_dev_enabled(ap->link.device))
|
||||
ahci_stop_engine(ap);
|
||||
hpriv->stop_engine(ap);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ahci_error_handler);
|
||||
|
||||
|
|
@ -2129,7 +2133,7 @@ static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
|
|||
return;
|
||||
|
||||
/* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
|
||||
rc = ahci_stop_engine(ap);
|
||||
rc = hpriv->stop_engine(ap);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
|
|
@ -2189,7 +2193,7 @@ static void ahci_enable_fbs(struct ata_port *ap)
|
|||
return;
|
||||
}
|
||||
|
||||
rc = ahci_stop_engine(ap);
|
||||
rc = hpriv->stop_engine(ap);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
|
|
@ -2222,7 +2226,7 @@ static void ahci_disable_fbs(struct ata_port *ap)
|
|||
return;
|
||||
}
|
||||
|
||||
rc = ahci_stop_engine(ap);
|
||||
rc = hpriv->stop_engine(ap);
|
||||
if (rc)
|
||||
return;
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@
|
|||
#include <linux/phy/phy.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/reset.h>
|
||||
#include "ahci.h"
|
||||
|
||||
static void ahci_host_stop(struct ata_host *host);
|
||||
|
|
@ -196,8 +195,7 @@ EXPORT_SYMBOL_GPL(ahci_platform_disable_regulators);
|
|||
* following order:
|
||||
* 1) Regulator
|
||||
* 2) Clocks (through ahci_platform_enable_clks)
|
||||
* 3) Resets
|
||||
* 4) Phys
|
||||
* 3) Phys
|
||||
*
|
||||
* If resource enabling fails at any point the previous enabled resources
|
||||
* are disabled in reverse order.
|
||||
|
|
@ -217,19 +215,12 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
|
|||
if (rc)
|
||||
goto disable_regulator;
|
||||
|
||||
rc = reset_control_deassert(hpriv->rsts);
|
||||
rc = ahci_platform_enable_phys(hpriv);
|
||||
if (rc)
|
||||
goto disable_clks;
|
||||
|
||||
rc = ahci_platform_enable_phys(hpriv);
|
||||
if (rc)
|
||||
goto disable_resets;
|
||||
|
||||
return 0;
|
||||
|
||||
disable_resets:
|
||||
reset_control_assert(hpriv->rsts);
|
||||
|
||||
disable_clks:
|
||||
ahci_platform_disable_clks(hpriv);
|
||||
|
||||
|
|
@ -248,15 +239,12 @@ EXPORT_SYMBOL_GPL(ahci_platform_enable_resources);
|
|||
* following order:
|
||||
* 1) Phys
|
||||
* 2) Clocks (through ahci_platform_disable_clks)
|
||||
* 3) Resets
|
||||
* 4) Regulator
|
||||
* 3) Regulator
|
||||
*/
|
||||
void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
|
||||
{
|
||||
ahci_platform_disable_phys(hpriv);
|
||||
|
||||
reset_control_assert(hpriv->rsts);
|
||||
|
||||
ahci_platform_disable_clks(hpriv);
|
||||
|
||||
ahci_platform_disable_regulators(hpriv);
|
||||
|
|
@ -405,12 +393,6 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev)
|
|||
hpriv->clks[i] = clk;
|
||||
}
|
||||
|
||||
hpriv->rsts = devm_reset_control_array_get_optional_shared(dev);
|
||||
if (IS_ERR(hpriv->rsts)) {
|
||||
rc = PTR_ERR(hpriv->rsts);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
hpriv->nports = child_nodes = of_get_child_count(dev->of_node);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -4549,6 +4549,12 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
|
|||
ATA_HORKAGE_ZERO_AFTER_TRIM |
|
||||
ATA_HORKAGE_NOLPM, },
|
||||
|
||||
/* This specific Samsung model/firmware-rev does not handle LPM well */
|
||||
{ "SAMSUNG MZMPC128HBFU-000MV", "CXM14M1Q", ATA_HORKAGE_NOLPM, },
|
||||
|
||||
/* Sandisk devices which are known to not handle LPM well */
|
||||
{ "SanDisk SD7UB3Q*G1001", NULL, ATA_HORKAGE_NOLPM, },
|
||||
|
||||
/* devices that don't properly handle queued TRIM commands */
|
||||
{ "Micron_M500_*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||
|
|
|
|||
|
|
@ -175,8 +175,8 @@ static void ata_eh_handle_port_resume(struct ata_port *ap)
|
|||
{ }
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
static void __ata_ehi_pushv_desc(struct ata_eh_info *ehi, const char *fmt,
|
||||
va_list args)
|
||||
static __printf(2, 0) void __ata_ehi_pushv_desc(struct ata_eh_info *ehi,
|
||||
const char *fmt, va_list args)
|
||||
{
|
||||
ehi->desc_len += vscnprintf(ehi->desc + ehi->desc_len,
|
||||
ATA_EH_DESC_LEN - ehi->desc_len,
|
||||
|
|
|
|||
|
|
@ -410,7 +410,7 @@ static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
|
|||
int rc;
|
||||
int retry = 100;
|
||||
|
||||
ahci_stop_engine(ap);
|
||||
hpriv->stop_engine(ap);
|
||||
|
||||
/* clear D2H reception area to properly wait for D2H FIS */
|
||||
ata_tf_init(link->device, &tf);
|
||||
|
|
|
|||
|
|
@ -285,13 +285,13 @@ static const struct sil24_cerr_info {
|
|||
[PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
|
||||
"protocol mismatch" },
|
||||
[PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
|
||||
"data directon mismatch" },
|
||||
"data direction mismatch" },
|
||||
[PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
|
||||
"ran out of SGEs while writing" },
|
||||
[PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
|
||||
"ran out of SGEs while reading" },
|
||||
[PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
|
||||
"invalid data directon for ATAPI CDB" },
|
||||
"invalid data direction for ATAPI CDB" },
|
||||
[PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
|
||||
"SGT not on qword boundary" },
|
||||
[PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
|
||||
|
|
|
|||
|
|
@ -191,7 +191,7 @@ static char *res_strings[] = {
|
|||
"reserved 37",
|
||||
"reserved 38",
|
||||
"reserved 39",
|
||||
"reseverd 40",
|
||||
"reserved 40",
|
||||
"reserved 41",
|
||||
"reserved 42",
|
||||
"reserved 43",
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/nospec.h>
|
||||
|
||||
#include "uPD98401.h"
|
||||
#include "uPD98402.h"
|
||||
|
|
@ -1458,6 +1459,8 @@ static int zatm_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
|
|||
return -EFAULT;
|
||||
if (pool < 0 || pool > ZATM_LAST_POOL)
|
||||
return -EINVAL;
|
||||
pool = array_index_nospec(pool,
|
||||
ZATM_LAST_POOL + 1);
|
||||
spin_lock_irqsave(&zatm_dev->lock, flags);
|
||||
info = zatm_dev->pool_info[pool];
|
||||
if (cmd == ZATM_GETPOOLZ) {
|
||||
|
|
|
|||
|
|
@ -2366,7 +2366,9 @@ static int rbd_obj_issue_copyup(struct rbd_obj_request *obj_req, u32 bytes)
|
|||
osd_req_op_cls_init(obj_req->osd_req, 0, CEPH_OSD_OP_CALL, "rbd",
|
||||
"copyup");
|
||||
osd_req_op_cls_request_data_bvecs(obj_req->osd_req, 0,
|
||||
obj_req->copyup_bvecs, bytes);
|
||||
obj_req->copyup_bvecs,
|
||||
obj_req->copyup_bvec_count,
|
||||
bytes);
|
||||
|
||||
switch (obj_req->img_request->op_type) {
|
||||
case OBJ_OP_WRITE:
|
||||
|
|
|
|||
|
|
@ -231,6 +231,7 @@ static const struct usb_device_id blacklist_table[] = {
|
|||
{ USB_DEVICE(0x0930, 0x0227), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0b05, 0x17d0), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x0036), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x3004), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x3008), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x311d), .driver_info = BTUSB_ATH3012 },
|
||||
{ USB_DEVICE(0x0cf3, 0x311e), .driver_info = BTUSB_ATH3012 },
|
||||
|
|
@ -263,7 +264,6 @@ static const struct usb_device_id blacklist_table[] = {
|
|||
{ USB_DEVICE(0x0489, 0xe03c), .driver_info = BTUSB_ATH3012 },
|
||||
|
||||
/* QCA ROME chipset */
|
||||
{ USB_DEVICE(0x0cf3, 0x3004), .driver_info = BTUSB_QCA_ROME },
|
||||
{ USB_DEVICE(0x0cf3, 0xe007), .driver_info = BTUSB_QCA_ROME },
|
||||
{ USB_DEVICE(0x0cf3, 0xe009), .driver_info = BTUSB_QCA_ROME },
|
||||
{ USB_DEVICE(0x0cf3, 0xe010), .driver_info = BTUSB_QCA_ROME },
|
||||
|
|
@ -399,6 +399,13 @@ static const struct dmi_system_id btusb_needs_reset_resume_table[] = {
|
|||
DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex 3060"),
|
||||
},
|
||||
},
|
||||
{
|
||||
/* Dell XPS 9360 (QCA ROME device 0cf3:e300) */
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9360"),
|
||||
},
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
@ -2852,6 +2859,12 @@ static int btusb_config_oob_wake(struct hci_dev *hdev)
|
|||
}
|
||||
#endif
|
||||
|
||||
static void btusb_check_needs_reset_resume(struct usb_interface *intf)
|
||||
{
|
||||
if (dmi_check_system(btusb_needs_reset_resume_table))
|
||||
interface_to_usbdev(intf)->quirks |= USB_QUIRK_RESET_RESUME;
|
||||
}
|
||||
|
||||
static int btusb_probe(struct usb_interface *intf,
|
||||
const struct usb_device_id *id)
|
||||
{
|
||||
|
|
@ -2974,9 +2987,6 @@ static int btusb_probe(struct usb_interface *intf,
|
|||
hdev->send = btusb_send_frame;
|
||||
hdev->notify = btusb_notify;
|
||||
|
||||
if (dmi_check_system(btusb_needs_reset_resume_table))
|
||||
interface_to_usbdev(intf)->quirks |= USB_QUIRK_RESET_RESUME;
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
err = btusb_config_oob_wake(hdev);
|
||||
if (err)
|
||||
|
|
@ -3064,6 +3074,7 @@ static int btusb_probe(struct usb_interface *intf,
|
|||
data->setup_on_usb = btusb_setup_qca;
|
||||
hdev->set_bdaddr = btusb_set_bdaddr_ath3012;
|
||||
set_bit(HCI_QUIRK_SIMULTANEOUS_DISCOVERY, &hdev->quirks);
|
||||
btusb_check_needs_reset_resume(intf);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BT_HCIBTUSB_RTL
|
||||
|
|
|
|||
|
|
@ -195,7 +195,7 @@ static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int ty
|
|||
return 0;
|
||||
}
|
||||
|
||||
int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
|
||||
static int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
|
||||
{
|
||||
size_t i;
|
||||
u32 *gp;
|
||||
|
|
@ -470,7 +470,7 @@ static int uninorth_free_gatt_table(struct agp_bridge_data *bridge)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void null_cache_flush(void)
|
||||
static void null_cache_flush(void)
|
||||
{
|
||||
mb();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -541,7 +541,7 @@ probe_err:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int cs2000_resume(struct device *dev)
|
||||
static int __maybe_unused cs2000_resume(struct device *dev)
|
||||
{
|
||||
struct cs2000_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -112,10 +112,18 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int clk_mux_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
|
||||
return clk_mux_determine_rate_flags(hw, req, mux->flags);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_mux_ops = {
|
||||
.get_parent = clk_mux_get_parent,
|
||||
.set_parent = clk_mux_set_parent,
|
||||
.determine_rate = __clk_mux_determine_rate,
|
||||
.determine_rate = clk_mux_determine_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_mux_ops);
|
||||
|
||||
|
|
|
|||
|
|
@ -216,7 +216,7 @@ static const char * const usart1_src[] = {
|
|||
"pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
|
||||
};
|
||||
|
||||
const char * const usart234578_src[] = {
|
||||
static const char * const usart234578_src[] = {
|
||||
"pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
|
||||
};
|
||||
|
||||
|
|
@ -224,10 +224,6 @@ static const char * const usart6_src[] = {
|
|||
"pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
|
||||
};
|
||||
|
||||
static const char * const dfsdm_src[] = {
|
||||
"pclk2", "ck_mcu"
|
||||
};
|
||||
|
||||
static const char * const fdcan_src[] = {
|
||||
"ck_hse", "pll3_q", "pll4_q"
|
||||
};
|
||||
|
|
@ -316,10 +312,8 @@ struct stm32_clk_mgate {
|
|||
struct clock_config {
|
||||
u32 id;
|
||||
const char *name;
|
||||
union {
|
||||
const char *parent_name;
|
||||
const char * const *parent_names;
|
||||
};
|
||||
const char *parent_name;
|
||||
const char * const *parent_names;
|
||||
int num_parents;
|
||||
unsigned long flags;
|
||||
void *cfg;
|
||||
|
|
@ -469,7 +463,7 @@ static void mp1_gate_clk_disable(struct clk_hw *hw)
|
|||
}
|
||||
}
|
||||
|
||||
const struct clk_ops mp1_gate_clk_ops = {
|
||||
static const struct clk_ops mp1_gate_clk_ops = {
|
||||
.enable = mp1_gate_clk_enable,
|
||||
.disable = mp1_gate_clk_disable,
|
||||
.is_enabled = clk_gate_is_enabled,
|
||||
|
|
@ -698,7 +692,7 @@ static void mp1_mgate_clk_disable(struct clk_hw *hw)
|
|||
mp1_gate_clk_disable(hw);
|
||||
}
|
||||
|
||||
const struct clk_ops mp1_mgate_clk_ops = {
|
||||
static const struct clk_ops mp1_mgate_clk_ops = {
|
||||
.enable = mp1_mgate_clk_enable,
|
||||
.disable = mp1_mgate_clk_disable,
|
||||
.is_enabled = clk_gate_is_enabled,
|
||||
|
|
@ -732,7 +726,7 @@ static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
|
|||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops clk_mmux_ops = {
|
||||
static const struct clk_ops clk_mmux_ops = {
|
||||
.get_parent = clk_mmux_get_parent,
|
||||
.set_parent = clk_mmux_set_parent,
|
||||
.determine_rate = __clk_mux_determine_rate,
|
||||
|
|
@ -1048,10 +1042,10 @@ struct stm32_pll_cfg {
|
|||
u32 offset;
|
||||
};
|
||||
|
||||
struct clk_hw *_clk_register_pll(struct device *dev,
|
||||
struct clk_hw_onecell_data *clk_data,
|
||||
void __iomem *base, spinlock_t *lock,
|
||||
const struct clock_config *cfg)
|
||||
static struct clk_hw *_clk_register_pll(struct device *dev,
|
||||
struct clk_hw_onecell_data *clk_data,
|
||||
void __iomem *base, spinlock_t *lock,
|
||||
const struct clock_config *cfg)
|
||||
{
|
||||
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
|
||||
|
||||
|
|
@ -1405,7 +1399,8 @@ enum {
|
|||
G_USBH,
|
||||
G_ETHSTP,
|
||||
G_RTCAPB,
|
||||
G_TZC,
|
||||
G_TZC1,
|
||||
G_TZC2,
|
||||
G_TZPC,
|
||||
G_IWDG1,
|
||||
G_BSEC,
|
||||
|
|
@ -1417,7 +1412,7 @@ enum {
|
|||
G_LAST
|
||||
};
|
||||
|
||||
struct stm32_mgate mp1_mgate[G_LAST];
|
||||
static struct stm32_mgate mp1_mgate[G_LAST];
|
||||
|
||||
#define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
|
||||
_mgate, _ops)\
|
||||
|
|
@ -1440,7 +1435,7 @@ struct stm32_mgate mp1_mgate[G_LAST];
|
|||
&mp1_mgate[_id], &mp1_mgate_clk_ops)
|
||||
|
||||
/* Peripheral gates */
|
||||
struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
|
||||
static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
|
||||
/* Multi gates */
|
||||
K_GATE(G_MDIO, RCC_APB1ENSETR, 31, 0),
|
||||
K_MGATE(G_DAC12, RCC_APB1ENSETR, 29, 0),
|
||||
|
|
@ -1506,7 +1501,8 @@ struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
|
|||
K_GATE(G_BSEC, RCC_APB5ENSETR, 16, 0),
|
||||
K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
|
||||
K_GATE(G_TZPC, RCC_APB5ENSETR, 13, 0),
|
||||
K_GATE(G_TZC, RCC_APB5ENSETR, 12, 0),
|
||||
K_GATE(G_TZC2, RCC_APB5ENSETR, 12, 0),
|
||||
K_GATE(G_TZC1, RCC_APB5ENSETR, 11, 0),
|
||||
K_GATE(G_RTCAPB, RCC_APB5ENSETR, 8, 0),
|
||||
K_MGATE(G_USART1, RCC_APB5ENSETR, 4, 0),
|
||||
K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
|
||||
|
|
@ -1600,7 +1596,7 @@ enum {
|
|||
M_LAST
|
||||
};
|
||||
|
||||
struct stm32_mmux ker_mux[M_LAST];
|
||||
static struct stm32_mmux ker_mux[M_LAST];
|
||||
|
||||
#define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
|
||||
[_id] = {\
|
||||
|
|
@ -1623,7 +1619,7 @@ struct stm32_mmux ker_mux[M_LAST];
|
|||
_K_MUX(_id, _offset, _shift, _width, _mux_flags,\
|
||||
&ker_mux[_id], &clk_mmux_ops)
|
||||
|
||||
const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
|
||||
static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
|
||||
/* Kernel multi mux */
|
||||
K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
|
||||
K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
|
||||
|
|
@ -1860,7 +1856,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
|
|||
PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
|
||||
PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
|
||||
CLK_IS_CRITICAL, G_RTCAPB),
|
||||
PCLK(TZC, "tzc", "pclk5", CLK_IGNORE_UNUSED, G_TZC),
|
||||
PCLK(TZC1, "tzc1", "ck_axi", CLK_IGNORE_UNUSED, G_TZC1),
|
||||
PCLK(TZC2, "tzc2", "ck_axi", CLK_IGNORE_UNUSED, G_TZC2),
|
||||
PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
|
||||
PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
|
||||
PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
|
||||
|
|
@ -1916,8 +1913,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
|
|||
KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
|
||||
KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
|
||||
KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
|
||||
KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IGNORE_UNUSED,
|
||||
G_STGEN, M_STGEN),
|
||||
KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IS_CRITICAL, G_STGEN, M_STGEN),
|
||||
KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
|
||||
KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
|
||||
KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
|
||||
|
|
@ -1948,8 +1944,8 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
|
|||
KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
|
||||
KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
|
||||
KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
|
||||
KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI2, M_SAI3),
|
||||
KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI2, M_SAI4),
|
||||
KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI3, M_SAI3),
|
||||
KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI4, M_SAI4),
|
||||
KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
|
||||
KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
|
||||
KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
|
||||
|
|
@ -1992,10 +1988,6 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
|
|||
_DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
|
||||
|
||||
/* Debug clocks */
|
||||
FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
|
||||
|
||||
GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
|
||||
|
||||
GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
|
||||
|
||||
COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
|
||||
|
|
|
|||
|
|
@ -426,9 +426,9 @@ static bool mux_is_better_rate(unsigned long rate, unsigned long now,
|
|||
return now <= rate && now > best;
|
||||
}
|
||||
|
||||
static int
|
||||
clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
|
||||
unsigned long flags)
|
||||
int clk_mux_determine_rate_flags(struct clk_hw *hw,
|
||||
struct clk_rate_request *req,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct clk_core *core = hw->core, *parent, *best_parent = NULL;
|
||||
int i, num_parents, ret;
|
||||
|
|
@ -488,6 +488,7 @@ out:
|
|||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
|
||||
|
||||
struct clk *__clk_lookup(const char *name)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -153,10 +153,19 @@ static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
val << mux->shift);
|
||||
}
|
||||
|
||||
static int clk_regmap_mux_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct clk_regmap *clk = to_clk_regmap(hw);
|
||||
struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk);
|
||||
|
||||
return clk_mux_determine_rate_flags(hw, req, mux->flags);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_regmap_mux_ops = {
|
||||
.get_parent = clk_regmap_mux_get_parent,
|
||||
.set_parent = clk_regmap_mux_set_parent,
|
||||
.determine_rate = __clk_mux_determine_rate,
|
||||
.determine_rate = clk_regmap_mux_determine_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_regmap_mux_ops);
|
||||
|
||||
|
|
|
|||
|
|
@ -17,8 +17,6 @@
|
|||
#define AO_RTC_ALT_CLK_CNTL0 0x94
|
||||
#define AO_RTC_ALT_CLK_CNTL1 0x98
|
||||
|
||||
extern const struct clk_ops meson_aoclk_gate_regmap_ops;
|
||||
|
||||
struct aoclk_cec_32k {
|
||||
struct clk_hw hw;
|
||||
struct regmap *regmap;
|
||||
|
|
|
|||
|
|
@ -253,7 +253,7 @@ static struct clk_fixed_factor meson8b_fclk_div3_div = {
|
|||
.mult = 1,
|
||||
.div = 3,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "fclk_div_div3",
|
||||
.name = "fclk_div3_div",
|
||||
.ops = &clk_fixed_factor_ops,
|
||||
.parent_names = (const char *[]){ "fixed_pll" },
|
||||
.num_parents = 1,
|
||||
|
|
@ -632,7 +632,8 @@ static struct clk_regmap meson8b_cpu_clk = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.parent_names = (const char *[]){ "xtal", "cpu_out_sel" },
|
||||
.parent_names = (const char *[]){ "xtal",
|
||||
"cpu_scale_out_sel" },
|
||||
.num_parents = 2,
|
||||
.flags = (CLK_SET_RATE_PARENT |
|
||||
CLK_SET_RATE_NO_REPARENT),
|
||||
|
|
|
|||
|
|
@ -126,6 +126,49 @@ static void cppc_cpufreq_stop_cpu(struct cpufreq_policy *policy)
|
|||
cpu->perf_caps.lowest_perf, cpu_num, ret);
|
||||
}
|
||||
|
||||
/*
|
||||
* The PCC subspace describes the rate at which platform can accept commands
|
||||
* on the shared PCC channel (including READs which do not count towards freq
|
||||
* trasition requests), so ideally we need to use the PCC values as a fallback
|
||||
* if we don't have a platform specific transition_delay_us
|
||||
*/
|
||||
#ifdef CONFIG_ARM64
|
||||
#include <asm/cputype.h>
|
||||
|
||||
static unsigned int cppc_cpufreq_get_transition_delay_us(int cpu)
|
||||
{
|
||||
unsigned long implementor = read_cpuid_implementor();
|
||||
unsigned long part_num = read_cpuid_part_number();
|
||||
unsigned int delay_us = 0;
|
||||
|
||||
switch (implementor) {
|
||||
case ARM_CPU_IMP_QCOM:
|
||||
switch (part_num) {
|
||||
case QCOM_CPU_PART_FALKOR_V1:
|
||||
case QCOM_CPU_PART_FALKOR:
|
||||
delay_us = 10000;
|
||||
break;
|
||||
default:
|
||||
delay_us = cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
delay_us = cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
|
||||
break;
|
||||
}
|
||||
|
||||
return delay_us;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static unsigned int cppc_cpufreq_get_transition_delay_us(int cpu)
|
||||
{
|
||||
return cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
struct cppc_cpudata *cpu;
|
||||
|
|
@ -162,8 +205,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
|
|||
cpu->perf_caps.highest_perf;
|
||||
policy->cpuinfo.max_freq = cppc_dmi_max_khz;
|
||||
|
||||
policy->transition_delay_us = cppc_get_transition_latency(cpu_num) /
|
||||
NSEC_PER_USEC;
|
||||
policy->transition_delay_us = cppc_cpufreq_get_transition_delay_us(cpu_num);
|
||||
policy->shared_type = cpu->shared_type;
|
||||
|
||||
if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
|
||||
|
|
|
|||
|
|
@ -384,7 +384,7 @@ static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
|
|||
if (set)
|
||||
reg |= bit;
|
||||
else
|
||||
reg &= bit;
|
||||
reg &= ~bit;
|
||||
iowrite32(reg, addr);
|
||||
|
||||
spin_unlock_irqrestore(&gpio->lock, flags);
|
||||
|
|
|
|||
|
|
@ -116,9 +116,9 @@ static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
|
|||
unsigned long word_mask;
|
||||
const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
|
||||
unsigned long port_state;
|
||||
u8 __iomem ports[] = {
|
||||
idio16gpio->reg->out0_7, idio16gpio->reg->out8_15,
|
||||
idio16gpio->reg->in0_7, idio16gpio->reg->in8_15,
|
||||
void __iomem *ports[] = {
|
||||
&idio16gpio->reg->out0_7, &idio16gpio->reg->out8_15,
|
||||
&idio16gpio->reg->in0_7, &idio16gpio->reg->in8_15,
|
||||
};
|
||||
|
||||
/* clear bits array to a clean slate */
|
||||
|
|
@ -143,7 +143,7 @@ static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
|
|||
}
|
||||
|
||||
/* read bits from current gpio port */
|
||||
port_state = ioread8(ports + i);
|
||||
port_state = ioread8(ports[i]);
|
||||
|
||||
/* store acquired bits at respective bits array offset */
|
||||
bits[word_index] |= port_state << word_offset;
|
||||
|
|
|
|||
|
|
@ -206,10 +206,10 @@ static int idio_24_gpio_get_multiple(struct gpio_chip *chip,
|
|||
unsigned long word_mask;
|
||||
const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
|
||||
unsigned long port_state;
|
||||
u8 __iomem ports[] = {
|
||||
idio24gpio->reg->out0_7, idio24gpio->reg->out8_15,
|
||||
idio24gpio->reg->out16_23, idio24gpio->reg->in0_7,
|
||||
idio24gpio->reg->in8_15, idio24gpio->reg->in16_23,
|
||||
void __iomem *ports[] = {
|
||||
&idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
|
||||
&idio24gpio->reg->out16_23, &idio24gpio->reg->in0_7,
|
||||
&idio24gpio->reg->in8_15, &idio24gpio->reg->in16_23,
|
||||
};
|
||||
const unsigned long out_mode_mask = BIT(1);
|
||||
|
||||
|
|
@ -217,7 +217,7 @@ static int idio_24_gpio_get_multiple(struct gpio_chip *chip,
|
|||
bitmap_zero(bits, chip->ngpio);
|
||||
|
||||
/* get bits are evaluated a gpio port register at a time */
|
||||
for (i = 0; i < ARRAY_SIZE(ports); i++) {
|
||||
for (i = 0; i < ARRAY_SIZE(ports) + 1; i++) {
|
||||
/* gpio offset in bits array */
|
||||
bits_offset = i * gpio_reg_size;
|
||||
|
||||
|
|
@ -236,7 +236,7 @@ static int idio_24_gpio_get_multiple(struct gpio_chip *chip,
|
|||
|
||||
/* read bits from current gpio port (port 6 is TTL GPIO) */
|
||||
if (i < 6)
|
||||
port_state = ioread8(ports + i);
|
||||
port_state = ioread8(ports[i]);
|
||||
else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
|
||||
port_state = ioread8(&idio24gpio->reg->ttl_out0_7);
|
||||
else
|
||||
|
|
@ -301,9 +301,9 @@ static void idio_24_gpio_set_multiple(struct gpio_chip *chip,
|
|||
const unsigned long port_mask = GENMASK(gpio_reg_size, 0);
|
||||
unsigned long flags;
|
||||
unsigned int out_state;
|
||||
u8 __iomem ports[] = {
|
||||
idio24gpio->reg->out0_7, idio24gpio->reg->out8_15,
|
||||
idio24gpio->reg->out16_23
|
||||
void __iomem *ports[] = {
|
||||
&idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
|
||||
&idio24gpio->reg->out16_23
|
||||
};
|
||||
const unsigned long out_mode_mask = BIT(1);
|
||||
const unsigned int ttl_offset = 48;
|
||||
|
|
@ -327,9 +327,9 @@ static void idio_24_gpio_set_multiple(struct gpio_chip *chip,
|
|||
raw_spin_lock_irqsave(&idio24gpio->lock, flags);
|
||||
|
||||
/* process output lines */
|
||||
out_state = ioread8(ports + i) & ~gpio_mask;
|
||||
out_state = ioread8(ports[i]) & ~gpio_mask;
|
||||
out_state |= (*bits >> bits_offset) & gpio_mask;
|
||||
iowrite8(out_state, ports + i);
|
||||
iowrite8(out_state, ports[i]);
|
||||
|
||||
raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -497,7 +497,7 @@ static int linehandle_create(struct gpio_device *gdev, void __user *ip)
|
|||
struct gpiohandle_request handlereq;
|
||||
struct linehandle_state *lh;
|
||||
struct file *file;
|
||||
int fd, i, ret;
|
||||
int fd, i, count = 0, ret;
|
||||
u32 lflags;
|
||||
|
||||
if (copy_from_user(&handlereq, ip, sizeof(handlereq)))
|
||||
|
|
@ -558,6 +558,7 @@ static int linehandle_create(struct gpio_device *gdev, void __user *ip)
|
|||
if (ret)
|
||||
goto out_free_descs;
|
||||
lh->descs[i] = desc;
|
||||
count = i;
|
||||
|
||||
if (lflags & GPIOHANDLE_REQUEST_ACTIVE_LOW)
|
||||
set_bit(FLAG_ACTIVE_LOW, &desc->flags);
|
||||
|
|
@ -628,7 +629,7 @@ static int linehandle_create(struct gpio_device *gdev, void __user *ip)
|
|||
out_put_unused_fd:
|
||||
put_unused_fd(fd);
|
||||
out_free_descs:
|
||||
for (; i >= 0; i--)
|
||||
for (i = 0; i < count; i++)
|
||||
gpiod_free(lh->descs[i]);
|
||||
kfree(lh->label);
|
||||
out_free_lh:
|
||||
|
|
@ -902,7 +903,7 @@ static int lineevent_create(struct gpio_device *gdev, void __user *ip)
|
|||
desc = &gdev->descs[offset];
|
||||
ret = gpiod_request(desc, le->label);
|
||||
if (ret)
|
||||
goto out_free_desc;
|
||||
goto out_free_label;
|
||||
le->desc = desc;
|
||||
le->eflags = eflags;
|
||||
|
||||
|
|
|
|||
|
|
@ -419,9 +419,11 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id)
|
|||
|
||||
if (other) {
|
||||
signed long r;
|
||||
r = dma_fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
|
||||
r = dma_fence_wait(other, true);
|
||||
if (r < 0) {
|
||||
DRM_ERROR("Error (%ld) waiting for fence!\n", r);
|
||||
if (r != -ERESTARTSYS)
|
||||
DRM_ERROR("Error (%ld) waiting for fence!\n", r);
|
||||
|
||||
return r;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -83,21 +83,22 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
|
|||
enum i2c_mot_mode mot = (msg->request & DP_AUX_I2C_MOT) ?
|
||||
I2C_MOT_TRUE : I2C_MOT_FALSE;
|
||||
enum ddc_result res;
|
||||
ssize_t read_bytes;
|
||||
uint32_t read_bytes = msg->size;
|
||||
|
||||
if (WARN_ON(msg->size > 16))
|
||||
return -E2BIG;
|
||||
|
||||
switch (msg->request & ~DP_AUX_I2C_MOT) {
|
||||
case DP_AUX_NATIVE_READ:
|
||||
read_bytes = dal_ddc_service_read_dpcd_data(
|
||||
res = dal_ddc_service_read_dpcd_data(
|
||||
TO_DM_AUX(aux)->ddc_service,
|
||||
false,
|
||||
I2C_MOT_UNDEF,
|
||||
msg->address,
|
||||
msg->buffer,
|
||||
msg->size);
|
||||
return read_bytes;
|
||||
msg->size,
|
||||
&read_bytes);
|
||||
break;
|
||||
case DP_AUX_NATIVE_WRITE:
|
||||
res = dal_ddc_service_write_dpcd_data(
|
||||
TO_DM_AUX(aux)->ddc_service,
|
||||
|
|
@ -108,14 +109,15 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
|
|||
msg->size);
|
||||
break;
|
||||
case DP_AUX_I2C_READ:
|
||||
read_bytes = dal_ddc_service_read_dpcd_data(
|
||||
res = dal_ddc_service_read_dpcd_data(
|
||||
TO_DM_AUX(aux)->ddc_service,
|
||||
true,
|
||||
mot,
|
||||
msg->address,
|
||||
msg->buffer,
|
||||
msg->size);
|
||||
return read_bytes;
|
||||
msg->size,
|
||||
&read_bytes);
|
||||
break;
|
||||
case DP_AUX_I2C_WRITE:
|
||||
res = dal_ddc_service_write_dpcd_data(
|
||||
TO_DM_AUX(aux)->ddc_service,
|
||||
|
|
@ -137,7 +139,9 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
|
|||
r == DDC_RESULT_SUCESSFULL);
|
||||
#endif
|
||||
|
||||
return msg->size;
|
||||
if (res != DDC_RESULT_SUCESSFULL)
|
||||
return -EIO;
|
||||
return read_bytes;
|
||||
}
|
||||
|
||||
static enum drm_connector_status
|
||||
|
|
|
|||
|
|
@ -70,6 +70,10 @@ static enum bp_result get_firmware_info_v3_1(
|
|||
struct bios_parser *bp,
|
||||
struct dc_firmware_info *info);
|
||||
|
||||
static enum bp_result get_firmware_info_v3_2(
|
||||
struct bios_parser *bp,
|
||||
struct dc_firmware_info *info);
|
||||
|
||||
static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
|
||||
struct atom_display_object_path_v2 *object);
|
||||
|
||||
|
|
@ -1321,9 +1325,11 @@ static enum bp_result bios_parser_get_firmware_info(
|
|||
case 3:
|
||||
switch (revision.minor) {
|
||||
case 1:
|
||||
case 2:
|
||||
result = get_firmware_info_v3_1(bp, info);
|
||||
break;
|
||||
case 2:
|
||||
result = get_firmware_info_v3_2(bp, info);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -1383,6 +1389,84 @@ static enum bp_result get_firmware_info_v3_1(
|
|||
return BP_RESULT_OK;
|
||||
}
|
||||
|
||||
static enum bp_result get_firmware_info_v3_2(
|
||||
struct bios_parser *bp,
|
||||
struct dc_firmware_info *info)
|
||||
{
|
||||
struct atom_firmware_info_v3_2 *firmware_info;
|
||||
struct atom_display_controller_info_v4_1 *dce_info = NULL;
|
||||
struct atom_common_table_header *header;
|
||||
struct atom_data_revision revision;
|
||||
struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
|
||||
struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
|
||||
|
||||
if (!info)
|
||||
return BP_RESULT_BADINPUT;
|
||||
|
||||
firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
|
||||
DATA_TABLES(firmwareinfo));
|
||||
|
||||
dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
|
||||
DATA_TABLES(dce_info));
|
||||
|
||||
if (!firmware_info || !dce_info)
|
||||
return BP_RESULT_BADBIOSTABLE;
|
||||
|
||||
memset(info, 0, sizeof(*info));
|
||||
|
||||
header = GET_IMAGE(struct atom_common_table_header,
|
||||
DATA_TABLES(smu_info));
|
||||
get_atom_data_table_revision(header, &revision);
|
||||
|
||||
if (revision.minor == 2) {
|
||||
/* Vega12 */
|
||||
smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
|
||||
DATA_TABLES(smu_info));
|
||||
|
||||
if (!smu_info_v3_2)
|
||||
return BP_RESULT_BADBIOSTABLE;
|
||||
|
||||
info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
|
||||
} else if (revision.minor == 3) {
|
||||
/* Vega20 */
|
||||
smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
|
||||
DATA_TABLES(smu_info));
|
||||
|
||||
if (!smu_info_v3_3)
|
||||
return BP_RESULT_BADBIOSTABLE;
|
||||
|
||||
info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
|
||||
}
|
||||
|
||||
// We need to convert from 10KHz units into KHz units.
|
||||
info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
|
||||
|
||||
/* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
|
||||
info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
|
||||
/* Hardcode frequency if BIOS gives no DCE Ref Clk */
|
||||
if (info->pll_info.crystal_frequency == 0) {
|
||||
if (revision.minor == 2)
|
||||
info->pll_info.crystal_frequency = 27000;
|
||||
else if (revision.minor == 3)
|
||||
info->pll_info.crystal_frequency = 100000;
|
||||
}
|
||||
/*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
|
||||
info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
|
||||
info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
|
||||
|
||||
/* Get GPU PLL VCO Clock */
|
||||
if (bp->cmd_tbl.get_smu_clock_info != NULL) {
|
||||
if (revision.minor == 2)
|
||||
info->smu_gpu_pll_output_freq =
|
||||
bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
|
||||
else if (revision.minor == 3)
|
||||
info->smu_gpu_pll_output_freq =
|
||||
bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
|
||||
}
|
||||
|
||||
return BP_RESULT_OK;
|
||||
}
|
||||
|
||||
static enum bp_result bios_parser_get_encoder_cap_info(
|
||||
struct dc_bios *dcb,
|
||||
struct graphics_object_id object_id,
|
||||
|
|
|
|||
|
|
@ -629,13 +629,14 @@ bool dal_ddc_service_query_ddc_data(
|
|||
return ret;
|
||||
}
|
||||
|
||||
ssize_t dal_ddc_service_read_dpcd_data(
|
||||
enum ddc_result dal_ddc_service_read_dpcd_data(
|
||||
struct ddc_service *ddc,
|
||||
bool i2c,
|
||||
enum i2c_mot_mode mot,
|
||||
uint32_t address,
|
||||
uint8_t *data,
|
||||
uint32_t len)
|
||||
uint32_t len,
|
||||
uint32_t *read)
|
||||
{
|
||||
struct aux_payload read_payload = {
|
||||
.i2c_over_aux = i2c,
|
||||
|
|
@ -652,6 +653,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
|
|||
.mot = mot
|
||||
};
|
||||
|
||||
*read = 0;
|
||||
|
||||
if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
|
||||
BREAK_TO_DEBUGGER();
|
||||
return DDC_RESULT_FAILED_INVALID_OPERATION;
|
||||
|
|
@ -661,7 +664,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
|
|||
ddc->ctx->i2caux,
|
||||
ddc->ddc_pin,
|
||||
&command)) {
|
||||
return (ssize_t)command.payloads->length;
|
||||
*read = command.payloads->length;
|
||||
return DDC_RESULT_SUCESSFULL;
|
||||
}
|
||||
|
||||
return DDC_RESULT_FAILED_OPERATION;
|
||||
|
|
|
|||
|
|
@ -66,8 +66,8 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
|
|||
{
|
||||
struct dc *core_dc = dc;
|
||||
|
||||
struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state),
|
||||
GFP_KERNEL);
|
||||
struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
|
||||
GFP_KERNEL);
|
||||
|
||||
if (NULL == plane_state)
|
||||
return NULL;
|
||||
|
|
@ -120,7 +120,7 @@ static void dc_plane_state_free(struct kref *kref)
|
|||
{
|
||||
struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
|
||||
destruct(plane_state);
|
||||
kfree(plane_state);
|
||||
kvfree(plane_state);
|
||||
}
|
||||
|
||||
void dc_plane_state_release(struct dc_plane_state *plane_state)
|
||||
|
|
@ -136,7 +136,7 @@ void dc_gamma_retain(struct dc_gamma *gamma)
|
|||
static void dc_gamma_free(struct kref *kref)
|
||||
{
|
||||
struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);
|
||||
kfree(gamma);
|
||||
kvfree(gamma);
|
||||
}
|
||||
|
||||
void dc_gamma_release(struct dc_gamma **gamma)
|
||||
|
|
@ -147,7 +147,7 @@ void dc_gamma_release(struct dc_gamma **gamma)
|
|||
|
||||
struct dc_gamma *dc_create_gamma(void)
|
||||
{
|
||||
struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL);
|
||||
struct dc_gamma *gamma = kvzalloc(sizeof(*gamma), GFP_KERNEL);
|
||||
|
||||
if (gamma == NULL)
|
||||
goto alloc_fail;
|
||||
|
|
@ -167,7 +167,7 @@ void dc_transfer_func_retain(struct dc_transfer_func *tf)
|
|||
static void dc_transfer_func_free(struct kref *kref)
|
||||
{
|
||||
struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);
|
||||
kfree(tf);
|
||||
kvfree(tf);
|
||||
}
|
||||
|
||||
void dc_transfer_func_release(struct dc_transfer_func *tf)
|
||||
|
|
@ -177,7 +177,7 @@ void dc_transfer_func_release(struct dc_transfer_func *tf)
|
|||
|
||||
struct dc_transfer_func *dc_create_transfer_func(void)
|
||||
{
|
||||
struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL);
|
||||
struct dc_transfer_func *tf = kvzalloc(sizeof(*tf), GFP_KERNEL);
|
||||
|
||||
if (tf == NULL)
|
||||
goto alloc_fail;
|
||||
|
|
|
|||
|
|
@ -102,13 +102,14 @@ bool dal_ddc_service_query_ddc_data(
|
|||
uint8_t *read_buf,
|
||||
uint32_t read_size);
|
||||
|
||||
ssize_t dal_ddc_service_read_dpcd_data(
|
||||
enum ddc_result dal_ddc_service_read_dpcd_data(
|
||||
struct ddc_service *ddc,
|
||||
bool i2c,
|
||||
enum i2c_mot_mode mot,
|
||||
uint32_t address,
|
||||
uint8_t *data,
|
||||
uint32_t len);
|
||||
uint32_t len,
|
||||
uint32_t *read);
|
||||
|
||||
enum ddc_result dal_ddc_service_write_dpcd_data(
|
||||
struct ddc_service *ddc,
|
||||
|
|
|
|||
|
|
@ -113,9 +113,14 @@
|
|||
|
||||
#define AI_GREENLAND_P_A0 1
|
||||
#define AI_GREENLAND_P_A1 2
|
||||
#define AI_UNKNOWN 0xFF
|
||||
|
||||
#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_UNKNOWN)
|
||||
#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_UNKNOWN)
|
||||
#define AI_VEGA12_P_A0 20
|
||||
#define ASICREV_IS_GREENLAND_M(eChipRev) (eChipRev < AI_VEGA12_P_A0)
|
||||
#define ASICREV_IS_GREENLAND_P(eChipRev) (eChipRev < AI_VEGA12_P_A0)
|
||||
|
||||
#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
|
||||
#define ASICREV_IS_VEGA12_p(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
|
||||
|
||||
/* DCN1_0 */
|
||||
#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
|
||||
|
|
|
|||
|
|
@ -1093,19 +1093,19 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
|
|||
|
||||
output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
|
||||
|
||||
rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
if (!rgb_user)
|
||||
goto rgb_user_alloc_fail;
|
||||
rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
rgb_regamma = kvzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
if (!rgb_regamma)
|
||||
goto rgb_regamma_alloc_fail;
|
||||
axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + 3),
|
||||
GFP_KERNEL);
|
||||
axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + 3),
|
||||
GFP_KERNEL);
|
||||
if (!axix_x)
|
||||
goto axix_x_alloc_fail;
|
||||
coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
|
||||
coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
|
||||
if (!coeff)
|
||||
goto coeff_alloc_fail;
|
||||
|
||||
|
|
@ -1157,13 +1157,13 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
|
|||
|
||||
ret = true;
|
||||
|
||||
kfree(coeff);
|
||||
kvfree(coeff);
|
||||
coeff_alloc_fail:
|
||||
kfree(axix_x);
|
||||
kvfree(axix_x);
|
||||
axix_x_alloc_fail:
|
||||
kfree(rgb_regamma);
|
||||
kvfree(rgb_regamma);
|
||||
rgb_regamma_alloc_fail:
|
||||
kfree(rgb_user);
|
||||
kvfree(rgb_user);
|
||||
rgb_user_alloc_fail:
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1192,19 +1192,19 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
|
|||
|
||||
input_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
|
||||
|
||||
rgb_user = kzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
rgb_user = kvzalloc(sizeof(*rgb_user) * (ramp->num_entries + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
if (!rgb_user)
|
||||
goto rgb_user_alloc_fail;
|
||||
curve = kzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
curve = kvzalloc(sizeof(*curve) * (MAX_HW_POINTS + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
if (!curve)
|
||||
goto curve_alloc_fail;
|
||||
axix_x = kzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
axix_x = kvzalloc(sizeof(*axix_x) * (ramp->num_entries + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
if (!axix_x)
|
||||
goto axix_x_alloc_fail;
|
||||
coeff = kzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
|
||||
coeff = kvzalloc(sizeof(*coeff) * (MAX_HW_POINTS + _EXTRA_POINTS), GFP_KERNEL);
|
||||
if (!coeff)
|
||||
goto coeff_alloc_fail;
|
||||
|
||||
|
|
@ -1246,13 +1246,13 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
|
|||
|
||||
ret = true;
|
||||
|
||||
kfree(coeff);
|
||||
kvfree(coeff);
|
||||
coeff_alloc_fail:
|
||||
kfree(axix_x);
|
||||
kvfree(axix_x);
|
||||
axix_x_alloc_fail:
|
||||
kfree(curve);
|
||||
kvfree(curve);
|
||||
curve_alloc_fail:
|
||||
kfree(rgb_user);
|
||||
kvfree(rgb_user);
|
||||
rgb_user_alloc_fail:
|
||||
|
||||
return ret;
|
||||
|
|
@ -1281,8 +1281,9 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
|
|||
}
|
||||
ret = true;
|
||||
} else if (trans == TRANSFER_FUNCTION_PQ) {
|
||||
rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS +
|
||||
_EXTRA_POINTS), GFP_KERNEL);
|
||||
rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
|
||||
(MAX_HW_POINTS + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
if (!rgb_regamma)
|
||||
goto rgb_regamma_alloc_fail;
|
||||
points->end_exponent = 7;
|
||||
|
|
@ -1302,11 +1303,12 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
|
|||
}
|
||||
ret = true;
|
||||
|
||||
kfree(rgb_regamma);
|
||||
kvfree(rgb_regamma);
|
||||
} else if (trans == TRANSFER_FUNCTION_SRGB ||
|
||||
trans == TRANSFER_FUNCTION_BT709) {
|
||||
rgb_regamma = kzalloc(sizeof(*rgb_regamma) * (MAX_HW_POINTS +
|
||||
_EXTRA_POINTS), GFP_KERNEL);
|
||||
rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
|
||||
(MAX_HW_POINTS + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
if (!rgb_regamma)
|
||||
goto rgb_regamma_alloc_fail;
|
||||
points->end_exponent = 0;
|
||||
|
|
@ -1324,7 +1326,7 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
|
|||
}
|
||||
ret = true;
|
||||
|
||||
kfree(rgb_regamma);
|
||||
kvfree(rgb_regamma);
|
||||
}
|
||||
rgb_regamma_alloc_fail:
|
||||
return ret;
|
||||
|
|
@ -1348,8 +1350,9 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
|
|||
}
|
||||
ret = true;
|
||||
} else if (trans == TRANSFER_FUNCTION_PQ) {
|
||||
rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS +
|
||||
_EXTRA_POINTS), GFP_KERNEL);
|
||||
rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
|
||||
(MAX_HW_POINTS + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
if (!rgb_degamma)
|
||||
goto rgb_degamma_alloc_fail;
|
||||
|
||||
|
|
@ -1364,11 +1367,12 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
|
|||
}
|
||||
ret = true;
|
||||
|
||||
kfree(rgb_degamma);
|
||||
kvfree(rgb_degamma);
|
||||
} else if (trans == TRANSFER_FUNCTION_SRGB ||
|
||||
trans == TRANSFER_FUNCTION_BT709) {
|
||||
rgb_degamma = kzalloc(sizeof(*rgb_degamma) * (MAX_HW_POINTS +
|
||||
_EXTRA_POINTS), GFP_KERNEL);
|
||||
rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
|
||||
(MAX_HW_POINTS + _EXTRA_POINTS),
|
||||
GFP_KERNEL);
|
||||
if (!rgb_degamma)
|
||||
goto rgb_degamma_alloc_fail;
|
||||
|
||||
|
|
@ -1382,7 +1386,7 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
|
|||
}
|
||||
ret = true;
|
||||
|
||||
kfree(rgb_degamma);
|
||||
kvfree(rgb_degamma);
|
||||
}
|
||||
points->end_exponent = 0;
|
||||
points->x_point_at_y1_red = 1;
|
||||
|
|
|
|||
|
|
@ -501,6 +501,32 @@ enum atom_cooling_solution_id{
|
|||
LIQUID_COOLING = 0x01
|
||||
};
|
||||
|
||||
struct atom_firmware_info_v3_2 {
|
||||
struct atom_common_table_header table_header;
|
||||
uint32_t firmware_revision;
|
||||
uint32_t bootup_sclk_in10khz;
|
||||
uint32_t bootup_mclk_in10khz;
|
||||
uint32_t firmware_capability; // enum atombios_firmware_capability
|
||||
uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
|
||||
uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
|
||||
uint16_t bootup_vddc_mv;
|
||||
uint16_t bootup_vddci_mv;
|
||||
uint16_t bootup_mvddc_mv;
|
||||
uint16_t bootup_vddgfx_mv;
|
||||
uint8_t mem_module_id;
|
||||
uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
|
||||
uint8_t reserved1[2];
|
||||
uint32_t mc_baseaddr_high;
|
||||
uint32_t mc_baseaddr_low;
|
||||
uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
|
||||
uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
|
||||
uint8_t board_i2c_feature_slave_addr;
|
||||
uint8_t reserved3;
|
||||
uint16_t bootup_mvddq_mv;
|
||||
uint16_t bootup_mvpp_mv;
|
||||
uint32_t zfbstartaddrin16mb;
|
||||
uint32_t reserved2[3];
|
||||
};
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
|
|
@ -1169,7 +1195,29 @@ struct atom_gfx_info_v2_2
|
|||
uint32_t rlc_gpu_timer_refclk;
|
||||
};
|
||||
|
||||
|
||||
struct atom_gfx_info_v2_3 {
|
||||
struct atom_common_table_header table_header;
|
||||
uint8_t gfxip_min_ver;
|
||||
uint8_t gfxip_max_ver;
|
||||
uint8_t max_shader_engines;
|
||||
uint8_t max_tile_pipes;
|
||||
uint8_t max_cu_per_sh;
|
||||
uint8_t max_sh_per_se;
|
||||
uint8_t max_backends_per_se;
|
||||
uint8_t max_texture_channel_caches;
|
||||
uint32_t regaddr_cp_dma_src_addr;
|
||||
uint32_t regaddr_cp_dma_src_addr_hi;
|
||||
uint32_t regaddr_cp_dma_dst_addr;
|
||||
uint32_t regaddr_cp_dma_dst_addr_hi;
|
||||
uint32_t regaddr_cp_dma_command;
|
||||
uint32_t regaddr_cp_status;
|
||||
uint32_t regaddr_rlc_gpu_clock_32;
|
||||
uint32_t rlc_gpu_timer_refclk;
|
||||
uint8_t active_cu_per_sh;
|
||||
uint8_t active_rb_per_se;
|
||||
uint16_t gcgoldenoffset;
|
||||
uint32_t rm21_sram_vmin_value;
|
||||
};
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
|
|
@ -1198,6 +1246,76 @@ struct atom_smu_info_v3_1
|
|||
uint8_t fw_ctf_polarity; // GPIO polarity for CTF
|
||||
};
|
||||
|
||||
struct atom_smu_info_v3_2 {
|
||||
struct atom_common_table_header table_header;
|
||||
uint8_t smuip_min_ver;
|
||||
uint8_t smuip_max_ver;
|
||||
uint8_t smu_rsd1;
|
||||
uint8_t gpuclk_ss_mode;
|
||||
uint16_t sclk_ss_percentage;
|
||||
uint16_t sclk_ss_rate_10hz;
|
||||
uint16_t gpuclk_ss_percentage; // in unit of 0.001%
|
||||
uint16_t gpuclk_ss_rate_10hz;
|
||||
uint32_t core_refclk_10khz;
|
||||
uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
|
||||
uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
|
||||
uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
|
||||
uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
|
||||
uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
|
||||
uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
|
||||
uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
|
||||
uint8_t fw_ctf_polarity; // GPIO polarity for CTF
|
||||
uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
|
||||
uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
|
||||
uint16_t smugoldenoffset;
|
||||
uint32_t gpupll_vco_freq_10khz;
|
||||
uint32_t bootup_smnclk_10khz;
|
||||
uint32_t bootup_socclk_10khz;
|
||||
uint32_t bootup_mp0clk_10khz;
|
||||
uint32_t bootup_mp1clk_10khz;
|
||||
uint32_t bootup_lclk_10khz;
|
||||
uint32_t bootup_dcefclk_10khz;
|
||||
uint32_t ctf_threshold_override_value;
|
||||
uint32_t reserved[5];
|
||||
};
|
||||
|
||||
struct atom_smu_info_v3_3 {
|
||||
struct atom_common_table_header table_header;
|
||||
uint8_t smuip_min_ver;
|
||||
uint8_t smuip_max_ver;
|
||||
uint8_t smu_rsd1;
|
||||
uint8_t gpuclk_ss_mode;
|
||||
uint16_t sclk_ss_percentage;
|
||||
uint16_t sclk_ss_rate_10hz;
|
||||
uint16_t gpuclk_ss_percentage; // in unit of 0.001%
|
||||
uint16_t gpuclk_ss_rate_10hz;
|
||||
uint32_t core_refclk_10khz;
|
||||
uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
|
||||
uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
|
||||
uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
|
||||
uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
|
||||
uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
|
||||
uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
|
||||
uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
|
||||
uint8_t fw_ctf_polarity; // GPIO polarity for CTF
|
||||
uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
|
||||
uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
|
||||
uint16_t smugoldenoffset;
|
||||
uint32_t gpupll_vco_freq_10khz;
|
||||
uint32_t bootup_smnclk_10khz;
|
||||
uint32_t bootup_socclk_10khz;
|
||||
uint32_t bootup_mp0clk_10khz;
|
||||
uint32_t bootup_mp1clk_10khz;
|
||||
uint32_t bootup_lclk_10khz;
|
||||
uint32_t bootup_dcefclk_10khz;
|
||||
uint32_t ctf_threshold_override_value;
|
||||
uint32_t syspll3_0_vco_freq_10khz;
|
||||
uint32_t syspll3_1_vco_freq_10khz;
|
||||
uint32_t bootup_fclk_10khz;
|
||||
uint32_t bootup_waflclk_10khz;
|
||||
uint32_t reserved[3];
|
||||
};
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
Data Table smc_dpm_info structure
|
||||
|
|
@ -1283,7 +1401,6 @@ struct atom_smc_dpm_info_v4_1
|
|||
uint32_t boardreserved[10];
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
***************************************************************************
|
||||
Data Table asic_profiling_info structure
|
||||
|
|
@ -1864,6 +1981,55 @@ enum atom_smu9_syspll0_clock_id
|
|||
SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
|
||||
};
|
||||
|
||||
enum atom_smu11_syspll_id {
|
||||
SMU11_SYSPLL0_ID = 0,
|
||||
SMU11_SYSPLL1_0_ID = 1,
|
||||
SMU11_SYSPLL1_1_ID = 2,
|
||||
SMU11_SYSPLL1_2_ID = 3,
|
||||
SMU11_SYSPLL2_ID = 4,
|
||||
SMU11_SYSPLL3_0_ID = 5,
|
||||
SMU11_SYSPLL3_1_ID = 6,
|
||||
};
|
||||
|
||||
|
||||
enum atom_smu11_syspll0_clock_id {
|
||||
SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK
|
||||
SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK
|
||||
SMU11_SYSPLL0_DCLK_ID = 2, // DCLK
|
||||
SMU11_SYSPLL0_VCLK_ID = 3, // VCLK
|
||||
SMU11_SYSPLL0_ECLK_ID = 4, // ECLK
|
||||
SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
|
||||
};
|
||||
|
||||
|
||||
enum atom_smu11_syspll1_0_clock_id {
|
||||
SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
|
||||
};
|
||||
|
||||
enum atom_smu11_syspll1_1_clock_id {
|
||||
SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
|
||||
};
|
||||
|
||||
enum atom_smu11_syspll1_2_clock_id {
|
||||
SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
|
||||
};
|
||||
|
||||
enum atom_smu11_syspll2_clock_id {
|
||||
SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
|
||||
};
|
||||
|
||||
enum atom_smu11_syspll3_0_clock_id {
|
||||
SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
|
||||
SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
|
||||
SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
|
||||
};
|
||||
|
||||
enum atom_smu11_syspll3_1_clock_id {
|
||||
SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
|
||||
SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
|
||||
SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
|
||||
};
|
||||
|
||||
struct atom_get_smu_clock_info_output_parameters_v3_1
|
||||
{
|
||||
union {
|
||||
|
|
|
|||
|
|
@ -79,12 +79,13 @@
|
|||
#define PCIE_BUS_CLK 10000
|
||||
#define TCLK (PCIE_BUS_CLK / 10)
|
||||
|
||||
static const struct profile_mode_setting smu7_profiling[5] =
|
||||
static const struct profile_mode_setting smu7_profiling[6] =
|
||||
{{1, 0, 100, 30, 1, 0, 100, 10},
|
||||
{1, 10, 0, 30, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 1, 10, 16, 31},
|
||||
{1, 0, 11, 50, 1, 0, 100, 10},
|
||||
{1, 0, 5, 30, 0, 0, 0, 0},
|
||||
{0, 0, 0, 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
|
||||
|
|
@ -4864,6 +4865,17 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
|
|||
len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (i == hwmgr->power_profile_mode) {
|
||||
size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
|
||||
i, profile_name[i], "*",
|
||||
data->current_profile_setting.sclk_up_hyst,
|
||||
data->current_profile_setting.sclk_down_hyst,
|
||||
data->current_profile_setting.sclk_activity,
|
||||
data->current_profile_setting.mclk_up_hyst,
|
||||
data->current_profile_setting.mclk_down_hyst,
|
||||
data->current_profile_setting.mclk_activity);
|
||||
continue;
|
||||
}
|
||||
if (smu7_profiling[i].bupdate_sclk)
|
||||
size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
|
||||
i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
|
||||
|
|
@ -4883,24 +4895,6 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
|
|||
"-", "-", "-");
|
||||
}
|
||||
|
||||
size += sprintf(buf + size, "%3d %16s: %8d %16d %16d %16d %16d %16d\n",
|
||||
i, profile_name[i],
|
||||
data->custom_profile_setting.sclk_up_hyst,
|
||||
data->custom_profile_setting.sclk_down_hyst,
|
||||
data->custom_profile_setting.sclk_activity,
|
||||
data->custom_profile_setting.mclk_up_hyst,
|
||||
data->custom_profile_setting.mclk_down_hyst,
|
||||
data->custom_profile_setting.mclk_activity);
|
||||
|
||||
size += sprintf(buf + size, "%3s %16s: %8d %16d %16d %16d %16d %16d\n",
|
||||
"*", "CURRENT",
|
||||
data->current_profile_setting.sclk_up_hyst,
|
||||
data->current_profile_setting.sclk_down_hyst,
|
||||
data->current_profile_setting.sclk_activity,
|
||||
data->current_profile_setting.mclk_up_hyst,
|
||||
data->current_profile_setting.mclk_down_hyst,
|
||||
data->current_profile_setting.mclk_activity);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
|
|
@ -4939,16 +4933,16 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
|
|||
if (size < 8)
|
||||
return -EINVAL;
|
||||
|
||||
data->custom_profile_setting.bupdate_sclk = input[0];
|
||||
data->custom_profile_setting.sclk_up_hyst = input[1];
|
||||
data->custom_profile_setting.sclk_down_hyst = input[2];
|
||||
data->custom_profile_setting.sclk_activity = input[3];
|
||||
data->custom_profile_setting.bupdate_mclk = input[4];
|
||||
data->custom_profile_setting.mclk_up_hyst = input[5];
|
||||
data->custom_profile_setting.mclk_down_hyst = input[6];
|
||||
data->custom_profile_setting.mclk_activity = input[7];
|
||||
if (!smum_update_dpm_settings(hwmgr, &data->custom_profile_setting)) {
|
||||
memcpy(&data->current_profile_setting, &data->custom_profile_setting, sizeof(struct profile_mode_setting));
|
||||
tmp.bupdate_sclk = input[0];
|
||||
tmp.sclk_up_hyst = input[1];
|
||||
tmp.sclk_down_hyst = input[2];
|
||||
tmp.sclk_activity = input[3];
|
||||
tmp.bupdate_mclk = input[4];
|
||||
tmp.mclk_up_hyst = input[5];
|
||||
tmp.mclk_down_hyst = input[6];
|
||||
tmp.mclk_activity = input[7];
|
||||
if (!smum_update_dpm_settings(hwmgr, &tmp)) {
|
||||
memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
|
||||
hwmgr->power_profile_mode = mode;
|
||||
}
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -325,7 +325,6 @@ struct smu7_hwmgr {
|
|||
uint16_t mem_latency_high;
|
||||
uint16_t mem_latency_low;
|
||||
uint32_t vr_config;
|
||||
struct profile_mode_setting custom_profile_setting;
|
||||
struct profile_mode_setting current_profile_setting;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -852,12 +852,10 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
|
|||
{
|
||||
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
|
||||
|
||||
n = (n & 0xff) << 8;
|
||||
|
||||
if (data->power_containment_features &
|
||||
POWERCONTAINMENT_FEATURE_PkgPwrLimit)
|
||||
return smum_send_msg_to_smc_with_parameter(hwmgr,
|
||||
PPSMC_MSG_PkgPwrSetLimit, n);
|
||||
PPSMC_MSG_PkgPwrSetLimit, n<<8);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ config DRM_SIL_SII8620
|
|||
tristate "Silicon Image SII8620 HDMI/MHL bridge"
|
||||
depends on OF && RC_CORE
|
||||
select DRM_KMS_HELPER
|
||||
imply EXTCON
|
||||
help
|
||||
Silicon Image SII8620 HDMI/MHL bridge chip driver.
|
||||
|
||||
|
|
|
|||
|
|
@ -56,7 +56,9 @@ static int dumb_vga_get_modes(struct drm_connector *connector)
|
|||
}
|
||||
|
||||
drm_mode_connector_update_edid_property(connector, edid);
|
||||
return drm_add_edid_modes(connector, edid);
|
||||
ret = drm_add_edid_modes(connector, edid);
|
||||
kfree(edid);
|
||||
return ret;
|
||||
|
||||
fallback:
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -155,6 +155,8 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state)
|
|||
state->connectors[i].state);
|
||||
state->connectors[i].ptr = NULL;
|
||||
state->connectors[i].state = NULL;
|
||||
state->connectors[i].old_state = NULL;
|
||||
state->connectors[i].new_state = NULL;
|
||||
drm_connector_put(connector);
|
||||
}
|
||||
|
||||
|
|
@ -169,6 +171,8 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state)
|
|||
|
||||
state->crtcs[i].ptr = NULL;
|
||||
state->crtcs[i].state = NULL;
|
||||
state->crtcs[i].old_state = NULL;
|
||||
state->crtcs[i].new_state = NULL;
|
||||
}
|
||||
|
||||
for (i = 0; i < config->num_total_plane; i++) {
|
||||
|
|
@ -181,6 +185,8 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state)
|
|||
state->planes[i].state);
|
||||
state->planes[i].ptr = NULL;
|
||||
state->planes[i].state = NULL;
|
||||
state->planes[i].old_state = NULL;
|
||||
state->planes[i].new_state = NULL;
|
||||
}
|
||||
|
||||
for (i = 0; i < state->num_private_objs; i++) {
|
||||
|
|
@ -190,6 +196,8 @@ void drm_atomic_state_default_clear(struct drm_atomic_state *state)
|
|||
state->private_objs[i].state);
|
||||
state->private_objs[i].ptr = NULL;
|
||||
state->private_objs[i].state = NULL;
|
||||
state->private_objs[i].old_state = NULL;
|
||||
state->private_objs[i].new_state = NULL;
|
||||
}
|
||||
state->num_private_objs = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -954,8 +954,6 @@ static int hdmi_create_connector(struct drm_encoder *encoder)
|
|||
drm_mode_connector_attach_encoder(connector, encoder);
|
||||
|
||||
if (hdata->bridge) {
|
||||
encoder->bridge = hdata->bridge;
|
||||
hdata->bridge->encoder = encoder;
|
||||
ret = drm_bridge_attach(encoder, hdata->bridge, NULL);
|
||||
if (ret)
|
||||
DRM_ERROR("Failed to attach bridge\n");
|
||||
|
|
|
|||
|
|
@ -473,7 +473,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
|
|||
chroma_addr[1] = chroma_addr[0] + 0x40;
|
||||
} else {
|
||||
luma_addr[1] = luma_addr[0] + fb->pitches[0];
|
||||
chroma_addr[1] = chroma_addr[0] + fb->pitches[0];
|
||||
chroma_addr[1] = chroma_addr[0] + fb->pitches[1];
|
||||
}
|
||||
} else {
|
||||
luma_addr[1] = 0;
|
||||
|
|
@ -482,6 +482,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
|
|||
|
||||
spin_lock_irqsave(&ctx->reg_slock, flags);
|
||||
|
||||
vp_reg_write(ctx, VP_SHADOW_UPDATE, 1);
|
||||
/* interlace or progressive scan mode */
|
||||
val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0);
|
||||
vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP);
|
||||
|
|
@ -495,21 +496,23 @@ static void vp_video_buffer(struct mixer_context *ctx,
|
|||
vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
|
||||
VP_IMG_VSIZE(fb->height));
|
||||
/* chroma plane for NV12/NV21 is half the height of the luma plane */
|
||||
vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) |
|
||||
vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[1]) |
|
||||
VP_IMG_VSIZE(fb->height / 2));
|
||||
|
||||
vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w);
|
||||
vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
|
||||
vp_reg_write(ctx, VP_SRC_H_POSITION,
|
||||
VP_SRC_H_POSITION_VAL(state->src.x));
|
||||
vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
|
||||
|
||||
vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w);
|
||||
vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x);
|
||||
|
||||
if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
|
||||
vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h / 2);
|
||||
vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y / 2);
|
||||
vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2);
|
||||
vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2);
|
||||
} else {
|
||||
vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
|
||||
vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
|
||||
vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h);
|
||||
vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y);
|
||||
}
|
||||
|
|
@ -699,6 +702,15 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
|
|||
|
||||
/* interlace scan need to check shadow register */
|
||||
if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
|
||||
if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags) &&
|
||||
vp_reg_read(ctx, VP_SHADOW_UPDATE))
|
||||
goto out;
|
||||
|
||||
base = mixer_reg_read(ctx, MXR_CFG);
|
||||
shadow = mixer_reg_read(ctx, MXR_CFG_S);
|
||||
if (base != shadow)
|
||||
goto out;
|
||||
|
||||
base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0));
|
||||
shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0));
|
||||
if (base != shadow)
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@
|
|||
#define MXR_MO 0x0304
|
||||
#define MXR_RESOLUTION 0x0310
|
||||
|
||||
#define MXR_CFG_S 0x2004
|
||||
#define MXR_GRAPHIC0_BASE_S 0x2024
|
||||
#define MXR_GRAPHIC1_BASE_S 0x2044
|
||||
|
||||
|
|
|
|||
|
|
@ -2302,9 +2302,44 @@ static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
|
||||
struct intel_crtc *crtc;
|
||||
struct intel_crtc_state *crtc_state;
|
||||
int vco, i;
|
||||
|
||||
vco = intel_state->cdclk.logical.vco;
|
||||
if (!vco)
|
||||
vco = dev_priv->skl_preferred_vco_freq;
|
||||
|
||||
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
|
||||
if (!crtc_state->base.enable)
|
||||
continue;
|
||||
|
||||
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
|
||||
continue;
|
||||
|
||||
/*
|
||||
* DPLL0 VCO may need to be adjusted to get the correct
|
||||
* clock for eDP. This will affect cdclk as well.
|
||||
*/
|
||||
switch (crtc_state->port_clock / 2) {
|
||||
case 108000:
|
||||
case 216000:
|
||||
vco = 8640000;
|
||||
break;
|
||||
default:
|
||||
vco = 8100000;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return vco;
|
||||
}
|
||||
|
||||
static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->dev);
|
||||
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
||||
int min_cdclk, cdclk, vco;
|
||||
|
||||
|
|
@ -2312,9 +2347,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
|
|||
if (min_cdclk < 0)
|
||||
return min_cdclk;
|
||||
|
||||
vco = intel_state->cdclk.logical.vco;
|
||||
if (!vco)
|
||||
vco = dev_priv->skl_preferred_vco_freq;
|
||||
vco = skl_dpll0_vco(intel_state);
|
||||
|
||||
/*
|
||||
* FIXME should also account for plane ratio
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
*/
|
||||
|
||||
#define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
|
||||
MODULE_FIRMWARE(I915_CSR_GLK);
|
||||
#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
|
||||
|
||||
#define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin"
|
||||
|
|
|
|||
|
|
@ -15178,6 +15178,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
|||
memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
|
||||
if (crtc_state->base.active) {
|
||||
intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
|
||||
crtc->base.mode.hdisplay = crtc_state->pipe_src_w;
|
||||
crtc->base.mode.vdisplay = crtc_state->pipe_src_h;
|
||||
intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
|
||||
WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
|
||||
|
||||
|
|
|
|||
|
|
@ -1881,26 +1881,6 @@ found:
|
|||
reduce_m_n);
|
||||
}
|
||||
|
||||
/*
|
||||
* DPLL0 VCO may need to be adjusted to get the correct
|
||||
* clock for eDP. This will affect cdclk as well.
|
||||
*/
|
||||
if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
|
||||
int vco;
|
||||
|
||||
switch (pipe_config->port_clock / 2) {
|
||||
case 108000:
|
||||
case 216000:
|
||||
vco = 8640000;
|
||||
break;
|
||||
default:
|
||||
vco = 8100000;
|
||||
break;
|
||||
}
|
||||
|
||||
to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
|
||||
}
|
||||
|
||||
if (!HAS_DDI(dev_priv))
|
||||
intel_dp_set_clock(encoder, pipe_config);
|
||||
|
||||
|
|
|
|||
|
|
@ -326,7 +326,8 @@ static void intel_enable_lvds(struct intel_encoder *encoder,
|
|||
|
||||
I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
|
||||
POSTING_READ(lvds_encoder->reg);
|
||||
if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000))
|
||||
|
||||
if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 5000))
|
||||
DRM_ERROR("timed out waiting for panel to power on\n");
|
||||
|
||||
intel_panel_enable_backlight(pipe_config, conn_state);
|
||||
|
|
|
|||
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