drm/amdgpu: remove gfxhub ip
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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13052be59a
Коммит
373f592325
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@ -1862,7 +1862,6 @@ static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
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static enum amd_ip_block_type ip_order[] = {
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AMD_IP_BLOCK_TYPE_GMC,
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AMD_IP_BLOCK_TYPE_COMMON,
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AMD_IP_BLOCK_TYPE_GFXHUB,
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AMD_IP_BLOCK_TYPE_MMHUB,
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AMD_IP_BLOCK_TYPE_IH,
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};
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@ -358,96 +358,3 @@ void gfxhub_v1_0_init(struct amdgpu_device *adev)
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hub->vm_l2_pro_fault_cntl =
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SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
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}
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static int gfxhub_v1_0_early_init(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_late_init(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_sw_init(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_sw_fini(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_hw_init(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_hw_fini(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_suspend(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_resume(void *handle)
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{
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return 0;
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}
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static bool gfxhub_v1_0_is_idle(void *handle)
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{
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return true;
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}
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static int gfxhub_v1_0_wait_for_idle(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_soft_reset(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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return 0;
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}
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static int gfxhub_v1_0_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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return 0;
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}
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const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = {
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.name = "gfxhub_v1_0",
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.early_init = gfxhub_v1_0_early_init,
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.late_init = gfxhub_v1_0_late_init,
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.sw_init = gfxhub_v1_0_sw_init,
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.sw_fini = gfxhub_v1_0_sw_fini,
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.hw_init = gfxhub_v1_0_hw_init,
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.hw_fini = gfxhub_v1_0_hw_fini,
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.suspend = gfxhub_v1_0_suspend,
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.resume = gfxhub_v1_0_resume,
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.is_idle = gfxhub_v1_0_is_idle,
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.wait_for_idle = gfxhub_v1_0_wait_for_idle,
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.soft_reset = gfxhub_v1_0_soft_reset,
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.set_clockgating_state = gfxhub_v1_0_set_clockgating_state,
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.set_powergating_state = gfxhub_v1_0_set_powergating_state,
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};
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const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block =
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{
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.type = AMD_IP_BLOCK_TYPE_GFXHUB,
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.major = 1,
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.minor = 0,
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.rev = 0,
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.funcs = &gfxhub_v1_0_ip_funcs,
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};
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@ -484,7 +484,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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amdgpu_ip_block_add(adev, &vega10_common_ip_block);
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amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
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amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
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amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
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amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
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@ -501,7 +500,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
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break;
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case CHIP_RAVEN:
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amdgpu_ip_block_add(adev, &vega10_common_ip_block);
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amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
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amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
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amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
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amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
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@ -76,7 +76,6 @@ enum amd_ip_block_type {
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_IP_BLOCK_TYPE_ACP,
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AMD_IP_BLOCK_TYPE_GFXHUB,
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AMD_IP_BLOCK_TYPE_MMHUB,
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AMD_IP_BLOCK_TYPE_VCN
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};
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