intel-pinctrl for v5.19-2
* Fix immutable IRQ chip examples in the GPIO documentation * Make use of immutable IRQ chip in Intel pin control drivers * Add module alias for Intel Apollo Lake The following is an automated git shortlog grouped by driver: baytrail: - make irq_chip immutable broxton: - Add module alias for Intel Apollo Lake cherryview: - Use GPIO chip pointer in chv_gpio_irq_mask_unmask() - make irq_chip immutable Documentation: - gpio: Advertise irqd_to_hwirq() helper in the examples - gpio: Fix IRQ mask and unmask examples intel: - Fix kernel doc format, i.e. add return sections - Drop unused irqchip member in struct intel_pinctrl - make irq_chip immutable lynxpoint: - make irq_chip immutable -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSu93Raj3rZDNXzGZv7cr9lmVa5zAUCYoe2dQAKCRD7cr9lmVa5 zOdhAQCRJVUM4CegYK0d3xFyFjePUYACxY9YJuZrNtM0Tqh+iAEAzFD1tTPTxn5X 1FLWz9MAHyMfbZijxU67HyATbGJyAg0= =9j0f -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v5.19-2' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.19-2 * Fix immutable IRQ chip examples in the GPIO documentation * Make use of immutable IRQ chip in Intel pin control drivers * Add module alias for Intel Apollo Lake The following is an automated git shortlog grouped by driver: baytrail: - make irq_chip immutable broxton: - Add module alias for Intel Apollo Lake cherryview: - Use GPIO chip pointer in chv_gpio_irq_mask_unmask() - make irq_chip immutable Documentation: - gpio: Advertise irqd_to_hwirq() helper in the examples - gpio: Fix IRQ mask and unmask examples intel: - Fix kernel doc format, i.e. add return sections - Drop unused irqchip member in struct intel_pinctrl - make irq_chip immutable lynxpoint: - make irq_chip immutable
This commit is contained in:
Linus Walleij
Коммит
374e72d721
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@ -429,7 +429,8 @@ call into the core gpiolib code:
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static void my_gpio_mask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(d);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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/*
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* Perform any necessary action to mask the interrupt,
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@ -437,14 +438,15 @@ call into the core gpiolib code:
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* state.
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*/
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gpiochip_disable_irq(gc, d->hwirq);
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gpiochip_disable_irq(gc, hwirq);
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}
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static void my_gpio_unmask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(d);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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gpiochip_enable_irq(gc, d->hwirq);
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gpiochip_enable_irq(gc, hwirq);
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/*
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* Perform any necessary action to unmask the interrupt,
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@ -501,7 +503,8 @@ the interrupt separately and go with it:
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static void my_gpio_mask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(d);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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/*
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* Perform any necessary action to mask the interrupt,
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@ -509,14 +512,15 @@ the interrupt separately and go with it:
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* state.
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*/
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gpiochip_disable_irq(gc, d->hwirq);
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gpiochip_disable_irq(gc, hwirq);
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}
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static void my_gpio_unmask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(d);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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gpiochip_enable_irq(gc, d->hwirq);
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gpiochip_enable_irq(gc, hwirq);
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/*
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* Perform any necessary action to unmask the interrupt,
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@ -576,7 +580,8 @@ In this case the typical set-up will look like this:
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static void my_gpio_mask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(d);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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/*
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* Perform any necessary action to mask the interrupt,
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@ -584,15 +589,16 @@ In this case the typical set-up will look like this:
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* state.
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*/
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gpiochip_disable_irq(gc, d->hwirq);
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gpiochip_disable_irq(gc, hwirq);
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irq_mask_mask_parent(d);
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}
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static void my_gpio_unmask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(d);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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gpiochip_enable_irq(gc, d->hwirq);
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gpiochip_enable_irq(gc, hwirq);
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/*
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* Perform any necessary action to unmask the interrupt,
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@ -1350,15 +1350,15 @@ static void byt_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *vg = gpiochip_get_data(gc);
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unsigned int offset = irqd_to_hwirq(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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void __iomem *reg;
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reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
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reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG);
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if (!reg)
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return;
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raw_spin_lock(&byt_lock);
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writel(BIT(offset % 32), reg);
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writel(BIT(hwirq % 32), reg);
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raw_spin_unlock(&byt_lock);
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}
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@ -1366,20 +1366,24 @@ static void byt_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *vg = gpiochip_get_data(gc);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
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byt_gpio_clear_triggering(vg, hwirq);
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gpiochip_disable_irq(gc, hwirq);
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}
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static void byt_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *vg = gpiochip_get_data(gc);
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unsigned int offset = irqd_to_hwirq(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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void __iomem *reg;
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u32 value;
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reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
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gpiochip_enable_irq(gc, hwirq);
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reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
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if (!reg)
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return;
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@ -1412,12 +1416,13 @@ static void byt_irq_unmask(struct irq_data *d)
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static int byt_irq_type(struct irq_data *d, unsigned int type)
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{
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struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
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u32 offset = irqd_to_hwirq(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 value;
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unsigned long flags;
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void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
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void __iomem *reg;
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if (!reg || offset >= vg->chip.ngpio)
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reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
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if (!reg)
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return -EINVAL;
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raw_spin_lock_irqsave(&byt_lock, flags);
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@ -1447,6 +1452,16 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
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return 0;
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}
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static const struct irq_chip byt_gpio_irq_chip = {
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.name = "BYT-GPIO",
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.irq_ack = byt_irq_ack,
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.irq_mask = byt_irq_mask,
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.irq_unmask = byt_irq_unmask,
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.irq_set_type = byt_irq_type,
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.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static void byt_gpio_irq_handler(struct irq_desc *desc)
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{
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struct irq_data *data = irq_desc_get_irq_data(desc);
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@ -1633,15 +1648,8 @@ static int byt_gpio_probe(struct intel_pinctrl *vg)
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if (irq > 0) {
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struct gpio_irq_chip *girq;
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vg->irqchip.name = "BYT-GPIO",
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vg->irqchip.irq_ack = byt_irq_ack,
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vg->irqchip.irq_mask = byt_irq_mask,
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vg->irqchip.irq_unmask = byt_irq_unmask,
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vg->irqchip.irq_set_type = byt_irq_type,
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vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED,
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girq = &gc->irq;
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girq->chip = &vg->irqchip;
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gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip);
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girq->init_hw = byt_gpio_irq_init_hw;
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girq->init_valid_mask = byt_init_irq_valid_mask;
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girq->parent_handler = byt_gpio_irq_handler;
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@ -1035,4 +1035,5 @@ module_exit(bxt_pinctrl_exit);
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MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
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MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:apollolake-pinctrl");
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MODULE_ALIAS("platform:broxton-pinctrl");
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@ -1242,12 +1242,12 @@ static void chv_gpio_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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int pin = irqd_to_hwirq(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 intr_line;
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raw_spin_lock(&chv_lock);
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intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
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intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
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intr_line &= CHV_PADCTRL0_INTSEL_MASK;
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intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
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chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
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@ -1255,17 +1255,15 @@ static void chv_gpio_irq_ack(struct irq_data *d)
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raw_spin_unlock(&chv_lock);
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}
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static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
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static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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int pin = irqd_to_hwirq(d);
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u32 value, intr_line;
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unsigned long flags;
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raw_spin_lock_irqsave(&chv_lock, flags);
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intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
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intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
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intr_line &= CHV_PADCTRL0_INTSEL_MASK;
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intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
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@ -1281,12 +1279,20 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
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static void chv_gpio_irq_mask(struct irq_data *d)
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{
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chv_gpio_irq_mask_unmask(d, true);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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chv_gpio_irq_mask_unmask(gc, hwirq, true);
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gpiochip_disable_irq(gc, hwirq);
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}
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static void chv_gpio_irq_unmask(struct irq_data *d)
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{
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chv_gpio_irq_mask_unmask(d, false);
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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gpiochip_enable_irq(gc, hwirq);
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chv_gpio_irq_mask_unmask(gc, hwirq, false);
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}
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static unsigned chv_gpio_irq_startup(struct irq_data *d)
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@ -1306,17 +1312,17 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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struct device *dev = pctrl->dev;
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struct intel_community_context *cctx = &pctrl->context.communities[0];
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unsigned int pin = irqd_to_hwirq(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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irq_flow_handler_t handler;
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unsigned long flags;
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u32 intsel, value;
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raw_spin_lock_irqsave(&chv_lock, flags);
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intsel = chv_readl(pctrl, pin, CHV_PADCTRL0);
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intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
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intsel &= CHV_PADCTRL0_INTSEL_MASK;
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intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
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value = chv_readl(pctrl, pin, CHV_PADCTRL1);
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value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
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if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
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handler = handle_level_irq;
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else
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@ -1324,9 +1330,9 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
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if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
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irq_set_handler_locked(d, handler);
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dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %u\n",
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intsel, pin);
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cctx->intr_lines[intsel] = pin;
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dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n",
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intsel, hwirq);
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cctx->intr_lines[intsel] = hwirq;
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}
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raw_spin_unlock_irqrestore(&chv_lock, flags);
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}
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@ -1392,14 +1398,14 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
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unsigned int pin = irqd_to_hwirq(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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unsigned long flags;
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u32 value;
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int ret;
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raw_spin_lock_irqsave(&chv_lock, flags);
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ret = chv_gpio_set_intr_line(pctrl, pin);
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ret = chv_gpio_set_intr_line(pctrl, hwirq);
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if (ret)
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goto out_unlock;
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@ -1416,8 +1422,8 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
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* 2. If the pin cfg is not locked in BIOS:
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* Driver programs the IntWakeCfg bits and save the mapping.
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*/
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if (!chv_pad_locked(pctrl, pin)) {
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value = chv_readl(pctrl, pin, CHV_PADCTRL1);
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if (!chv_pad_locked(pctrl, hwirq)) {
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value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
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value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
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value &= ~CHV_PADCTRL1_INVRXTX_MASK;
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@ -1434,7 +1440,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
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value |= CHV_PADCTRL1_INVRXTX_RXDATA;
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}
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chv_writel(pctrl, pin, CHV_PADCTRL1, value);
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chv_writel(pctrl, hwirq, CHV_PADCTRL1, value);
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}
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if (type & IRQ_TYPE_EDGE_BOTH)
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@ -1448,6 +1454,17 @@ out_unlock:
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return ret;
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}
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|
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static const struct irq_chip chv_gpio_irq_chip = {
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.name = "chv-gpio",
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.irq_startup = chv_gpio_irq_startup,
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.irq_ack = chv_gpio_irq_ack,
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.irq_mask = chv_gpio_irq_mask,
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.irq_unmask = chv_gpio_irq_unmask,
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.irq_set_type = chv_gpio_irq_type,
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.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
|
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|
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static void chv_gpio_irq_handler(struct irq_desc *desc)
|
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{
|
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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|
|
@ -1611,15 +1628,8 @@ static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
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chip->base = -1;
|
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|
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pctrl->irq = irq;
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pctrl->irqchip.name = "chv-gpio";
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pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
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pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
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pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
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pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
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pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
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pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
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|
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chip->irq.chip = &pctrl->irqchip;
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||||
gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip);
|
||||
chip->irq.init_hw = chv_gpio_irq_init_hw;
|
||||
chip->irq.parent_handler = chv_gpio_irq_handler;
|
||||
chip->irq.num_parents = 1;
|
||||
|
|
|
|||
|
|
@ -858,6 +858,9 @@ static const struct pinctrl_desc intel_pinctrl_desc = {
|
|||
* When coming through gpiolib irqchip, the GPIO offset is not
|
||||
* automatically translated to pinctrl pin number. This function can be
|
||||
* used to find out the corresponding pinctrl pin.
|
||||
*
|
||||
* Return: a pin number and pointers to the community and pad group, which
|
||||
* the pin belongs to, or negative error code if translation can't be done.
|
||||
*/
|
||||
static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
|
||||
const struct intel_community **community,
|
||||
|
|
@ -899,6 +902,8 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
|
|||
* @pin: pin number
|
||||
*
|
||||
* Translate the pin number of pinctrl to GPIO offset
|
||||
*
|
||||
* Return: a GPIO offset, or negative error code if translation can't be done.
|
||||
*/
|
||||
static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
|
||||
{
|
||||
|
|
@ -1039,15 +1044,14 @@ static void intel_gpio_irq_ack(struct irq_data *d)
|
|||
}
|
||||
}
|
||||
|
||||
static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
|
||||
static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
const struct intel_community *community;
|
||||
const struct intel_padgroup *padgrp;
|
||||
int pin;
|
||||
|
||||
pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
|
||||
pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp);
|
||||
if (pin >= 0) {
|
||||
unsigned int gpp, gpp_offset;
|
||||
unsigned long flags;
|
||||
|
|
@ -1077,12 +1081,20 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
|
|||
|
||||
static void intel_gpio_irq_mask(struct irq_data *d)
|
||||
{
|
||||
intel_gpio_irq_mask_unmask(d, true);
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
|
||||
intel_gpio_irq_mask_unmask(gc, hwirq, true);
|
||||
gpiochip_disable_irq(gc, hwirq);
|
||||
}
|
||||
|
||||
static void intel_gpio_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
intel_gpio_irq_mask_unmask(d, false);
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
|
||||
gpiochip_enable_irq(gc, hwirq);
|
||||
intel_gpio_irq_mask_unmask(gc, hwirq, false);
|
||||
}
|
||||
|
||||
static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
|
||||
|
|
@ -1157,6 +1169,17 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_chip intel_gpio_irq_chip = {
|
||||
.name = "intel-gpio",
|
||||
.irq_ack = intel_gpio_irq_ack,
|
||||
.irq_mask = intel_gpio_irq_mask,
|
||||
.irq_unmask = intel_gpio_irq_unmask,
|
||||
.irq_set_type = intel_gpio_irq_type,
|
||||
.irq_set_wake = intel_gpio_irq_wake,
|
||||
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
|
||||
const struct intel_community *community)
|
||||
{
|
||||
|
|
@ -1319,15 +1342,6 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
|
|||
pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
|
||||
pctrl->irq = irq;
|
||||
|
||||
/* Setup IRQ chip */
|
||||
pctrl->irqchip.name = dev_name(pctrl->dev);
|
||||
pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
|
||||
pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
|
||||
pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
|
||||
pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
|
||||
pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
|
||||
pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
|
||||
|
||||
/*
|
||||
* On some platforms several GPIO controllers share the same interrupt
|
||||
* line.
|
||||
|
|
@ -1340,8 +1354,9 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* Setup IRQ chip */
|
||||
girq = &pctrl->chip.irq;
|
||||
girq->chip = &pctrl->irqchip;
|
||||
gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip);
|
||||
/* This will let us handle the IRQ in the driver */
|
||||
girq->parent_handler = NULL;
|
||||
girq->num_parents = 0;
|
||||
|
|
|
|||
|
|
@ -223,7 +223,6 @@ struct intel_pinctrl_context {
|
|||
* @pctldesc: Pin controller description
|
||||
* @pctldev: Pointer to the pin controller device
|
||||
* @chip: GPIO chip in this pin controller
|
||||
* @irqchip: IRQ chip in this pin controller
|
||||
* @soc: SoC/PCH specific pin configuration data
|
||||
* @communities: All communities in this pin controller
|
||||
* @ncommunities: Number of communities in this pin controller
|
||||
|
|
@ -236,7 +235,6 @@ struct intel_pinctrl {
|
|||
struct pinctrl_desc pctldesc;
|
||||
struct pinctrl_dev *pctldev;
|
||||
struct gpio_chip chip;
|
||||
struct irq_chip irqchip;
|
||||
const struct intel_pinctrl_soc_data *soc;
|
||||
struct intel_community *communities;
|
||||
size_t ncommunities;
|
||||
|
|
|
|||
|
|
@ -663,7 +663,7 @@ static void lp_irq_ack(struct irq_data *d)
|
|||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
|
||||
unsigned long flags;
|
||||
|
||||
|
|
@ -684,10 +684,12 @@ static void lp_irq_enable(struct irq_data *d)
|
|||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
|
||||
unsigned long flags;
|
||||
|
||||
gpiochip_enable_irq(gc, hwirq);
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
|
@ -697,30 +699,33 @@ static void lp_irq_disable(struct irq_data *d)
|
|||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&lg->lock, flags);
|
||||
iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
|
||||
raw_spin_unlock_irqrestore(&lg->lock, flags);
|
||||
|
||||
gpiochip_disable_irq(gc, hwirq);
|
||||
}
|
||||
|
||||
static int lp_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *lg = gpiochip_get_data(gc);
|
||||
u32 hwirq = irqd_to_hwirq(d);
|
||||
void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
unsigned long flags;
|
||||
void __iomem *reg;
|
||||
u32 value;
|
||||
|
||||
if (hwirq >= lg->chip.ngpio)
|
||||
reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
|
||||
if (!reg)
|
||||
return -EINVAL;
|
||||
|
||||
/* Fail if BIOS reserved pin for ACPI use */
|
||||
if (lp_gpio_acpi_use(lg, hwirq)) {
|
||||
dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq);
|
||||
dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
|
|
@ -755,7 +760,7 @@ static int lp_irq_set_type(struct irq_data *d, unsigned int type)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip lp_irqchip = {
|
||||
static const struct irq_chip lp_irqchip = {
|
||||
.name = "LP-GPIO",
|
||||
.irq_ack = lp_irq_ack,
|
||||
.irq_mask = lp_irq_mask,
|
||||
|
|
@ -763,7 +768,8 @@ static struct irq_chip lp_irqchip = {
|
|||
.irq_enable = lp_irq_enable,
|
||||
.irq_disable = lp_irq_disable,
|
||||
.irq_set_type = lp_irq_set_type,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE,
|
||||
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
|
||||
|
|
@ -884,7 +890,7 @@ static int lp_gpio_probe(struct platform_device *pdev)
|
|||
struct gpio_irq_chip *girq;
|
||||
|
||||
girq = &gc->irq;
|
||||
girq->chip = &lp_irqchip;
|
||||
gpio_irq_chip_set_chip(girq, &lp_irqchip);
|
||||
girq->init_hw = lp_gpio_irq_init_hw;
|
||||
girq->parent_handler = lp_gpio_irq_handler;
|
||||
girq->num_parents = 1;
|
||||
|
|
|
|||
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