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PCI/PM: Rename pci_dev.d3_delay to d3hot_delay 

PCI devices support two variants of the D3 power state: D3hot (main power
present) D3cold (main power removed).  Previously struct pci_dev contained:

  unsigned int    d3_delay;       /* D3->D0 transition time in ms */
  unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */

"d3_delay" refers specifically to the D3hot state.  Rename it to
"d3hot_delay" to avoid ambiguity and align with the ACPI "_DSM for
Specifying Device Readiness Durations" in the PCI Firmware spec r3.2,
sec 4.6.9.

There is no change to the functionality.

Link: https://lore.kernel.org/r/20200730210848.1578826-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Krzysztof Wilczyński 2020-07-30 21:08:48 +00:00 коммит произвёл Bjorn Helgaas
Родитель a5d02e901e
Коммит 3789af9a13
12 изменённых файлов: 52 добавлений и 52 удалений
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2
Documentation/power/pci.rst
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@ -320,7 +320,7 @@ that these callbacks operate on::
unsigned int d2_support:1; /* Low power state D2 is supported */ unsigned int d2_support:1; /* Low power state D2 is supported */
unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
unsigned int wakeup_prepared:1; /* Device prepared for wake up */ unsigned int wakeup_prepared:1; /* Device prepared for wake up */
unsigned int d3_delay; /* D3->D0 transition time in ms */ unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
... ...
}; };

2
arch/x86/pci/fixup.c
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@ -587,7 +587,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26d, pci_invalid_bar);
static void pci_fixup_amd_ehci_pme(struct pci_dev *dev) static void pci_fixup_amd_ehci_pme(struct pci_dev *dev)
{ {
dev_info(&dev->dev, "PME# does not work under D3, disabling it\n"); dev_info(&dev->dev, "PME# does not work under D3, disabling it\n");
dev->pme_support &= ~((PCI_PM_CAP_PME_D3 | PCI_PM_CAP_PME_D3cold) dev->pme_support &= ~((PCI_PM_CAP_PME_D3hot | PCI_PM_CAP_PME_D3cold)
>> PCI_PM_CAP_PME_SHIFT); >> PCI_PM_CAP_PME_SHIFT);
} }
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme);

2
arch/x86/pci/intel_mid_pci.c
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@ -322,7 +322,7 @@ static void pci_d3delay_fixup(struct pci_dev *dev)
*/ */
if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID)) if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
return; return;
dev->d3_delay = 0; dev->d3hot_delay = 0;
} }
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);

2
drivers/hid/intel-ish-hid/ipc/ipc.c
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@ -755,7 +755,7 @@ static int _ish_hw_reset(struct ishtp_device *dev)
csr |= PCI_D3hot; csr |= PCI_D3hot;
pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr); pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr);
mdelay(pdev->d3_delay); mdelay(pdev->d3hot_delay);
csr &= ~PCI_PM_CTRL_STATE_MASK; csr &= ~PCI_PM_CTRL_STATE_MASK;
csr |= PCI_D0; csr |= PCI_D0;

2
drivers/net/ethernet/marvell/sky2.c
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@ -5105,7 +5105,7 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
INIT_WORK(&hw->restart_work, sky2_restart); INIT_WORK(&hw->restart_work, sky2_restart);
pci_set_drvdata(pdev, hw); pci_set_drvdata(pdev, hw);
pdev->d3_delay = 300; pdev->d3hot_delay = 300;
return 0; return 0;

6
drivers/pci/pci-acpi.c
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@ -1167,7 +1167,7 @@ static struct acpi_device *acpi_pci_find_companion(struct device *dev)
* @pdev: the PCI device whose delay is to be updated * @pdev: the PCI device whose delay is to be updated
* @handle: ACPI handle of this device * @handle: ACPI handle of this device
* *
* Update the d3_delay and d3cold_delay of a PCI device from the ACPI _DSM * Update the d3hot_delay and d3cold_delay of a PCI device from the ACPI _DSM
* control method of either the device itself or the PCI host bridge. * control method of either the device itself or the PCI host bridge.
* *
* Function 8, "Reset Delay," applies to the entire hierarchy below a PCI * Function 8, "Reset Delay," applies to the entire hierarchy below a PCI
@ -1206,8 +1206,8 @@ static void pci_acpi_optimize_delay(struct pci_dev *pdev,
} }
if (elements[3].type == ACPI_TYPE_INTEGER) { if (elements[3].type == ACPI_TYPE_INTEGER) {
value = (int)elements[3].integer.value / 1000; value = (int)elements[3].integer.value / 1000;
if (value < PCI_PM_D3_WAIT) if (value < PCI_PM_D3HOT_WAIT)
pdev->d3_delay = value; pdev->d3hot_delay = value;
} }
} }
ACPI_FREE(obj); ACPI_FREE(obj);

14
drivers/pci/pci.c
Просмотреть файл

@ -49,7 +49,7 @@ EXPORT_SYMBOL(isa_dma_bridge_buggy);
int pci_pci_problems; int pci_pci_problems;
EXPORT_SYMBOL(pci_pci_problems); EXPORT_SYMBOL(pci_pci_problems);
unsigned int pci_pm_d3_delay; unsigned int pci_pm_d3hot_delay;
static void pci_pme_list_scan(struct work_struct *work); static void pci_pme_list_scan(struct work_struct *work);
@ -66,10 +66,10 @@ struct pci_pme_device {
static void pci_dev_d3_sleep(struct pci_dev *dev) static void pci_dev_d3_sleep(struct pci_dev *dev)
{ {
unsigned int delay = dev->d3_delay; unsigned int delay = dev->d3hot_delay;
if (delay < pci_pm_d3_delay) if (delay < pci_pm_d3hot_delay)
delay = pci_pm_d3_delay; delay = pci_pm_d3hot_delay;
if (delay) if (delay)
msleep(delay); msleep(delay);
@ -3013,7 +3013,7 @@ void pci_pm_init(struct pci_dev *dev)
} }
dev->pm_cap = pm; dev->pm_cap = pm;
dev->d3_delay = PCI_PM_D3_WAIT; dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
dev->d3cold_delay = PCI_PM_D3COLD_WAIT; dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
dev->bridge_d3 = pci_bridge_d3_possible(dev); dev->bridge_d3 = pci_bridge_d3_possible(dev);
dev->d3cold_allowed = true; dev->d3cold_allowed = true;
@ -3038,7 +3038,7 @@ void pci_pm_init(struct pci_dev *dev)
(pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
(pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
(pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
(pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
(pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
dev->pme_poll = true; dev->pme_poll = true;
@ -4621,7 +4621,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
* *
* NOTE: This causes the caller to sleep for twice the device power transition * NOTE: This causes the caller to sleep for twice the device power transition
* cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
* by default (i.e. unless the @dev's d3_delay field has a different value). * by default (i.e. unless the @dev's d3hot_delay field has a different value).
* Moreover, only devices in D0 can be reset by this function. * Moreover, only devices in D0 can be reset by this function.
*/ */
static int pci_pm_reset(struct pci_dev *dev, int probe) static int pci_pm_reset(struct pci_dev *dev, int probe)

4
drivers/pci/pci.h
Просмотреть файл

@ -44,7 +44,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
int pci_bus_error_reset(struct pci_dev *dev); int pci_bus_error_reset(struct pci_dev *dev);
#define PCI_PM_D2_DELAY 200 #define PCI_PM_D2_DELAY 200
#define PCI_PM_D3_WAIT 10 #define PCI_PM_D3HOT_WAIT 10
#define PCI_PM_D3COLD_WAIT 100 #define PCI_PM_D3COLD_WAIT 100
#define PCI_PM_BUS_WAIT 50 #define PCI_PM_BUS_WAIT 50
@ -178,7 +178,7 @@ extern struct mutex pci_slot_mutex;
extern raw_spinlock_t pci_lock; extern raw_spinlock_t pci_lock;
extern unsigned int pci_pm_d3_delay; extern unsigned int pci_pm_d3hot_delay;
#ifdef CONFIG_PCI_MSI #ifdef CONFIG_PCI_MSI
void pci_no_msi(void); void pci_no_msi(void);

64
drivers/pci/quirks.c
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@ -1846,7 +1846,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pci
*/ */
static void quirk_intel_pcie_pm(struct pci_dev *dev) static void quirk_intel_pcie_pm(struct pci_dev *dev)
{ {
pci_pm_d3_delay = 120; pci_pm_d3hot_delay = 120;
dev->no_d1d2 = 1; dev->no_d1d2 = 1;
} }
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
@ -1873,12 +1873,12 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
{ {
if (dev->d3_delay >= delay) if (dev->d3hot_delay >= delay)
return; return;
dev->d3_delay = delay; dev->d3hot_delay = delay;
pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
dev->d3_delay); dev->d3hot_delay);
} }
static void quirk_radeon_pm(struct pci_dev *dev) static void quirk_radeon_pm(struct pci_dev *dev)
@ -3387,36 +3387,36 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
* PCI devices which are on Intel chips can skip the 10ms delay * PCI devices which are on Intel chips can skip the 10ms delay
* before entering D3 mode. * before entering D3 mode.
*/ */
static void quirk_remove_d3_delay(struct pci_dev *dev) static void quirk_remove_d3hot_delay(struct pci_dev *dev)
{ {
dev->d3_delay = 0; dev->d3hot_delay = 0;
} }
/* C600 Series devices do not need 10ms d3_delay */ /* C600 Series devices do not need 10ms d3hot_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
/* Lynxpoint-H PCH devices do not need 10ms d3_delay */ /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
/* Intel Cherrytrail devices do not need 10ms d3_delay */ /* Intel Cherrytrail devices do not need 10ms d3hot_delay */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
/* /*
* Some devices may pass our check in pci_intx_mask_supported() if * Some devices may pass our check in pci_intx_mask_supported() if

2
drivers/staging/media/atomisp/pci/atomisp_v4l2.c
Просмотреть файл

@ -1573,7 +1573,7 @@ static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *i
spin_lock_init(&isp->lock); spin_lock_init(&isp->lock);
/* This is not a true PCI device on SoC, so the delay is not needed. */ /* This is not a true PCI device on SoC, so the delay is not needed. */
pdev->d3_delay = 0; pdev->d3hot_delay = 0;
pci_set_drvdata(pdev, isp); pci_set_drvdata(pdev, isp);

2
include/linux/pci.h
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@ -373,7 +373,7 @@ struct pci_dev {
user sysfs */ user sysfs */
unsigned int clear_retrain_link:1; /* Need to clear Retrain Link unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
bit manually */ bit manually */
unsigned int d3_delay; /* D3->D0 transition time in ms */ unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
#ifdef CONFIG_PCIEASPM #ifdef CONFIG_PCIEASPM

2
include/uapi/linux/pci_regs.h
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@ -246,7 +246,7 @@
#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ #define PCI_PM_CAP_PME_D3hot 0x4000 /* PME# from D3 (hot) */
#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ #define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
#define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL 4 /* PM control and status register */