An assortment of vendor specific clk drivers fixes, most notably
fallout from adding Tegra210 and rockchip rk3036/rk3368 drivers this cycle. There's also the random smattering of sparse/checker fixes, a build "fix" to get the Tango clk driver to compile because the Kconfig symbol was renamed after the fact, and a clk gpio fix for a patch mismerge. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCAAGBQJWxohFAAoJENidgRMleOc9BdMP/A+OSpgI9wx0nQTFya9DOMLn cDJvsD3qagMqyy1KkEgd5Zx1H2vBdABn9Hdtm+nGccisV1yR3zxxy5t2TbxB/Dcl /bZKAmhGViArTV83VUjkzQuAJ0cvH4He85ODG8UkQlAl3PiSLjO2NkZVeZsgeszx mG0VHLVy+AzzPLVFPrT6Xa6iuk1IQFgy5QfkowjaWynawxAf4In6XBYmN6nPABL3 17WNzpfsl9jLw3PfybX0qKvM7tKmNT9+IQ7SDV2nObkL/dwHci5jiWuhE2dxkYrO S6g73WklMKd9ah4qvq3d7Jcxk6ee82uvdlBiSJmpcQQnWPKDjUnJhPJxNo+yWR0U 2XtQcbreNlyygg5NKDwqKaTZEypx7QnzDy7tEj30GvMVb0fRFMpnmEN4BjdJiyWT MwAG5e3WsoqkNFNAvMhpbOMG/grUp8XoyN1IILhmaerMAhhSc1+as2oUTI5ezPWF CiY/dyvVpzda+Z4/LglYbC550qWK7sUNFcVEMMJUHrNPAHeFifZlJzglMAD/5Tz4 hdwMEMeRXy3VgspwrRrmxuETSWuhsdxuzWYx1ZAyB0vYzrAWK+a5msVodyRttNIY K/RyaMqUacWQLZ01dItW/RVbXzOynptqmzpPsWF4ASZG7GAGsp/5gwYVN+lDr0G4 GrfRRcvcrKAwiF69AM8H =I6OK -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk driver fixes from Stephen Boyd: "An assortment of vendor specific clk drivers fixes, most notably fallout from adding Tegra210 and rockchip rk3036/rk3368 drivers this cycle. There's also the random smattering of sparse/checker fixes, a build "fix" to get the Tango clk driver to compile because the Kconfig symbol was renamed after the fact, and a clk gpio fix for a patch mismerge" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (28 commits) clk: gpio: Really allow an optional clock= DT property Revert "clk: qcom: Specify LE device endianness" clk: versatile: mask VCO bits before writing clk: tegra: super: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warning for pll_m clk: tegra: Use definition for pll_u override bit clk: tegra: Fix warning caused by pll_u failing to lock clk: tegra: Fix clock sources for Tegra210 EMC clk: tegra: Add the APB2APE audio clock on Tegra210 clk: tegra: Add missing of_node_put() clk: tegra: Fix PLLE SS coefficients clk: tegra: Fix typos around clearing PLLE bits during enable clk: tegra: Do not disable PLLE when under hardware control clk: tegra: Fix pllx dyn step calculation clk: tegra: pll: Fix potential sleeping-while-atomic clk: tegra: Fix the misnaming of nvenc from msenc clk: tegra: Fix naming of MISC registers clk: tango4: rename ARCH_TANGOX to ARCH_TANGO clk: scpi: Fix checking return value of platform_device_register_simple() ...
This commit is contained in:
Linus Torvalds
Коммит
37aa4dac99
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@ -30,7 +30,7 @@ that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required,
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- "ext_i2s" - external I2S clock - optional,
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- "ext_gmac" - external GMAC clock - optional
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- "rmii_clkin" - external EMAC clock - optional
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Example: Clock controller node:
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@ -43,7 +43,7 @@ obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
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obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
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obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
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obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o
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obj-$(CONFIG_ARCH_TANGOX) += clk-tango4.o
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obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o
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obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
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obj-$(CONFIG_ARCH_U300) += clk-u300.o
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obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
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@ -289,7 +289,7 @@ static void __init of_gpio_clk_setup(struct device_node *node,
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num_parents = of_clk_get_parent_count(node);
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if (num_parents < 0)
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return;
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num_parents = 0;
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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@ -299,7 +299,7 @@ static int scpi_clocks_probe(struct platform_device *pdev)
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/* Add the virtual cpufreq device */
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cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
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-1, NULL, 0);
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if (!cpufreq_dev)
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if (IS_ERR(cpufreq_dev))
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pr_warn("unable to register cpufreq device");
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return 0;
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@ -247,7 +247,7 @@ static struct clk_onecell_data dove_divider_data = {
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void __init dove_divider_clk_init(struct device_node *np)
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{
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void *base;
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void __iomem *base;
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base = of_iomap(np, 0);
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if (WARN_ON(!base))
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@ -3587,7 +3587,6 @@ static const struct regmap_config gcc_apq8084_regmap_config = {
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.val_bits = 32,
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.max_register = 0x1fc0,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc gcc_apq8084_desc = {
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@ -3005,7 +3005,6 @@ static const struct regmap_config gcc_ipq806x_regmap_config = {
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.val_bits = 32,
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.max_register = 0x3e40,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc gcc_ipq806x_desc = {
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@ -2702,7 +2702,6 @@ static const struct regmap_config gcc_msm8660_regmap_config = {
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.val_bits = 32,
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.max_register = 0x363c,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc gcc_msm8660_desc = {
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@ -3336,7 +3336,6 @@ static const struct regmap_config gcc_msm8916_regmap_config = {
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.val_bits = 32,
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.max_register = 0x80000,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc gcc_msm8916_desc = {
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@ -3468,7 +3468,6 @@ static const struct regmap_config gcc_msm8960_regmap_config = {
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.val_bits = 32,
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.max_register = 0x3660,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct regmap_config gcc_apq8064_regmap_config = {
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@ -3477,7 +3476,6 @@ static const struct regmap_config gcc_apq8064_regmap_config = {
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.val_bits = 32,
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.max_register = 0x3880,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc gcc_msm8960_desc = {
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@ -2680,7 +2680,6 @@ static const struct regmap_config gcc_msm8974_regmap_config = {
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.val_bits = 32,
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.max_register = 0x1fc0,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc gcc_msm8974_desc = {
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@ -419,7 +419,6 @@ static const struct regmap_config lcc_ipq806x_regmap_config = {
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.val_bits = 32,
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.max_register = 0xfc,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc lcc_ipq806x_desc = {
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@ -524,7 +524,6 @@ static const struct regmap_config lcc_msm8960_regmap_config = {
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.val_bits = 32,
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.max_register = 0xfc,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc lcc_msm8960_desc = {
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@ -3368,7 +3368,6 @@ static const struct regmap_config mmcc_apq8084_regmap_config = {
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.val_bits = 32,
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.max_register = 0x5104,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc mmcc_apq8084_desc = {
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@ -3029,7 +3029,6 @@ static const struct regmap_config mmcc_msm8960_regmap_config = {
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.val_bits = 32,
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.max_register = 0x334,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct regmap_config mmcc_apq8064_regmap_config = {
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@ -3038,7 +3037,6 @@ static const struct regmap_config mmcc_apq8064_regmap_config = {
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.val_bits = 32,
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.max_register = 0x350,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc mmcc_msm8960_desc = {
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@ -2594,7 +2594,6 @@ static const struct regmap_config mmcc_msm8974_regmap_config = {
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.val_bits = 32,
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.max_register = 0x5104,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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static const struct qcom_cc_desc mmcc_msm8974_desc = {
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@ -133,7 +133,7 @@ PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
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PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
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PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
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PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
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PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
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PNAME(mux_mac_p) = { "mac_pll_src", "rmii_clkin" };
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PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" };
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static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
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@ -224,16 +224,16 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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RK2928_CLKGATE_CON(2), 2, GFLAGS),
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COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
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RK2928_CLKSEL_CON(2), 4, 1, DFLAGS,
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RK2928_CLKSEL_CON(2), 4, 1, MFLAGS,
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RK2928_CLKGATE_CON(1), 0, GFLAGS),
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COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED,
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RK2928_CLKSEL_CON(2), 5, 1, DFLAGS,
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RK2928_CLKSEL_CON(2), 5, 1, MFLAGS,
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RK2928_CLKGATE_CON(1), 1, GFLAGS),
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COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED,
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RK2928_CLKSEL_CON(2), 6, 1, DFLAGS,
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RK2928_CLKSEL_CON(2), 6, 1, MFLAGS,
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RK2928_CLKGATE_CON(2), 4, GFLAGS),
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COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED,
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RK2928_CLKSEL_CON(2), 7, 1, DFLAGS,
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RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
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RK2928_CLKGATE_CON(2), 5, GFLAGS),
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MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
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@ -242,11 +242,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
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RK2928_CLKGATE_CON(1), 8, GFLAGS),
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COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
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RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
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RK2928_CLKGATE_CON(1), 8, GFLAGS),
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RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
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RK2928_CLKGATE_CON(1), 10, GFLAGS),
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COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
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RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
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RK2928_CLKGATE_CON(1), 8, GFLAGS),
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RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
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RK2928_CLKGATE_CON(1), 12, GFLAGS),
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COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(17), 0,
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RK2928_CLKGATE_CON(1), 9, GFLAGS,
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@ -279,13 +279,13 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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RK2928_CLKGATE_CON(3), 2, GFLAGS),
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COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0,
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RK2928_CLKSEL_CON(12), 8, 2, DFLAGS,
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RK2928_CLKSEL_CON(12), 8, 2, MFLAGS,
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RK2928_CLKGATE_CON(2), 11, GFLAGS),
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DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0,
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RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
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COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
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RK2928_CLKSEL_CON(12), 10, 2, DFLAGS,
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RK2928_CLKSEL_CON(12), 10, 2, MFLAGS,
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RK2928_CLKGATE_CON(2), 13, GFLAGS),
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DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
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RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
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@ -344,12 +344,12 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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RK2928_CLKGATE_CON(10), 5, GFLAGS),
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COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
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RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
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RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
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MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
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COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
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RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
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RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
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RK2928_CLKGATE_CON(2), 6, GFLAGS),
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MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
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|
|
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|
@ -780,13 +780,13 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS),
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/* pclk_pd_alive gates */
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GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 8, GFLAGS),
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GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 7, GFLAGS),
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GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 12, GFLAGS),
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GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 11, GFLAGS),
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GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 3, GFLAGS),
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GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 2, GFLAGS),
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GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(14), 1, GFLAGS),
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GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS),
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GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
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GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
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GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
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GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
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GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
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GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
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||||
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||||
/*
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||||
* pclk_vio gates
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||||
|
|
@ -796,12 +796,12 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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|||
GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
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||||
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/* pclk_pd_pmu gates */
|
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GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 0, GFLAGS),
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GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(17), 4, GFLAGS),
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GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 3, GFLAGS),
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GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 2, GFLAGS),
|
||||
GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 1, GFLAGS),
|
||||
GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 2, GFLAGS),
|
||||
GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
|
||||
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS),
|
||||
GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS),
|
||||
GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS),
|
||||
GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS),
|
||||
GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
|
||||
|
||||
/* timer gates */
|
||||
GATE(0, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),
|
||||
|
|
|
|||
|
|
@ -450,8 +450,10 @@ static int load_timings_from_dt(struct tegra_clk_emc *tegra,
|
|||
struct emc_timing *timing = tegra->timings + (i++);
|
||||
|
||||
err = load_one_timing_from_dt(tegra, timing, child);
|
||||
if (err)
|
||||
if (err) {
|
||||
of_node_put(child);
|
||||
return err;
|
||||
}
|
||||
|
||||
timing->ram_code = ram_code;
|
||||
}
|
||||
|
|
@ -499,9 +501,9 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
|
|||
* fuses until the apbmisc driver is loaded.
|
||||
*/
|
||||
err = load_timings_from_dt(tegra, node, node_ram_code);
|
||||
of_node_put(node);
|
||||
if (err)
|
||||
return ERR_PTR(err);
|
||||
of_node_put(node);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ enum clk_id {
|
|||
tegra_clk_afi,
|
||||
tegra_clk_amx,
|
||||
tegra_clk_amx1,
|
||||
tegra_clk_apb2ape,
|
||||
tegra_clk_apbdma,
|
||||
tegra_clk_apbif,
|
||||
tegra_clk_ape,
|
||||
|
|
|
|||
|
|
@ -86,15 +86,21 @@
|
|||
#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
|
||||
PLLE_SS_CNTL_SSC_BYP)
|
||||
#define PLLE_SS_MAX_MASK 0x1ff
|
||||
#define PLLE_SS_MAX_VAL 0x25
|
||||
#define PLLE_SS_MAX_VAL_TEGRA114 0x25
|
||||
#define PLLE_SS_MAX_VAL_TEGRA210 0x21
|
||||
#define PLLE_SS_INC_MASK (0xff << 16)
|
||||
#define PLLE_SS_INC_VAL (0x1 << 16)
|
||||
#define PLLE_SS_INCINTRV_MASK (0x3f << 24)
|
||||
#define PLLE_SS_INCINTRV_VAL (0x20 << 24)
|
||||
#define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
|
||||
#define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
|
||||
#define PLLE_SS_COEFFICIENTS_MASK \
|
||||
(PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
|
||||
#define PLLE_SS_COEFFICIENTS_VAL \
|
||||
(PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
|
||||
#define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
|
||||
(PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
|
||||
PLLE_SS_INCINTRV_VAL_TEGRA114)
|
||||
#define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
|
||||
(PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
|
||||
PLLE_SS_INCINTRV_VAL_TEGRA210)
|
||||
|
||||
#define PLLE_AUX_PLLP_SEL BIT(2)
|
||||
#define PLLE_AUX_USE_LOCKDET BIT(3)
|
||||
|
|
@ -880,7 +886,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll)
|
|||
static int clk_plle_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct tegra_clk_pll *pll = to_clk_pll(hw);
|
||||
unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
|
||||
unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
|
||||
struct tegra_clk_pll_freq_table sel;
|
||||
u32 val;
|
||||
int err;
|
||||
|
|
@ -1378,7 +1384,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
|
|||
u32 val;
|
||||
int ret;
|
||||
unsigned long flags = 0;
|
||||
unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
|
||||
unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
|
||||
|
||||
if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
|
||||
return -EINVAL;
|
||||
|
|
@ -1401,7 +1407,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
|
|||
val |= PLLE_MISC_IDDQ_SW_CTRL;
|
||||
val &= ~PLLE_MISC_IDDQ_SW_VALUE;
|
||||
val |= PLLE_MISC_PLLE_PTS;
|
||||
val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
|
||||
val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
|
||||
pll_writel_misc(val, pll);
|
||||
udelay(5);
|
||||
|
||||
|
|
@ -1428,7 +1434,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
|
|||
val = pll_readl(PLLE_SS_CTRL, pll);
|
||||
val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
|
||||
val &= ~PLLE_SS_COEFFICIENTS_MASK;
|
||||
val |= PLLE_SS_COEFFICIENTS_VAL;
|
||||
val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
|
||||
pll_writel(val, PLLE_SS_CTRL, pll);
|
||||
val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
|
||||
pll_writel(val, PLLE_SS_CTRL, pll);
|
||||
|
|
@ -2012,9 +2018,9 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
|
|||
struct tegra_clk_pll *pll = to_clk_pll(hw);
|
||||
struct tegra_clk_pll_freq_table sel;
|
||||
u32 val;
|
||||
int ret;
|
||||
int ret = 0;
|
||||
unsigned long flags = 0;
|
||||
unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
|
||||
unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
|
||||
|
||||
if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
|
||||
return -EINVAL;
|
||||
|
|
@ -2022,22 +2028,20 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
|
|||
if (pll->lock)
|
||||
spin_lock_irqsave(pll->lock, flags);
|
||||
|
||||
val = pll_readl(pll->params->aux_reg, pll);
|
||||
if (val & PLLE_AUX_SEQ_ENABLE)
|
||||
goto out;
|
||||
|
||||
val = pll_readl_base(pll);
|
||||
val &= ~BIT(30); /* Disable lock override */
|
||||
pll_writel_base(val, pll);
|
||||
|
||||
val = pll_readl(pll->params->aux_reg, pll);
|
||||
val |= PLLE_AUX_ENABLE_SWCTL;
|
||||
val &= ~PLLE_AUX_SEQ_ENABLE;
|
||||
pll_writel(val, pll->params->aux_reg, pll);
|
||||
udelay(1);
|
||||
|
||||
val = pll_readl_misc(pll);
|
||||
val |= PLLE_MISC_LOCK_ENABLE;
|
||||
val |= PLLE_MISC_IDDQ_SW_CTRL;
|
||||
val &= ~PLLE_MISC_IDDQ_SW_VALUE;
|
||||
val |= PLLE_MISC_PLLE_PTS;
|
||||
val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
|
||||
val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
|
||||
pll_writel_misc(val, pll);
|
||||
udelay(5);
|
||||
|
||||
|
|
@ -2067,7 +2071,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw)
|
|||
val = pll_readl(PLLE_SS_CTRL, pll);
|
||||
val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
|
||||
val &= ~PLLE_SS_COEFFICIENTS_MASK;
|
||||
val |= PLLE_SS_COEFFICIENTS_VAL;
|
||||
val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
|
||||
pll_writel(val, PLLE_SS_CTRL, pll);
|
||||
val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
|
||||
pll_writel(val, PLLE_SS_CTRL, pll);
|
||||
|
|
@ -2104,15 +2108,25 @@ static void clk_plle_tegra210_disable(struct clk_hw *hw)
|
|||
if (pll->lock)
|
||||
spin_lock_irqsave(pll->lock, flags);
|
||||
|
||||
/* If PLLE HW sequencer is enabled, SW should not disable PLLE */
|
||||
val = pll_readl(pll->params->aux_reg, pll);
|
||||
if (val & PLLE_AUX_SEQ_ENABLE)
|
||||
goto out;
|
||||
|
||||
val = pll_readl_base(pll);
|
||||
val &= ~PLLE_BASE_ENABLE;
|
||||
pll_writel_base(val, pll);
|
||||
|
||||
val = pll_readl(pll->params->aux_reg, pll);
|
||||
val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
|
||||
pll_writel(val, pll->params->aux_reg, pll);
|
||||
|
||||
val = pll_readl_misc(pll);
|
||||
val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
|
||||
pll_writel_misc(val, pll);
|
||||
udelay(1);
|
||||
|
||||
out:
|
||||
if (pll->lock)
|
||||
spin_unlock_irqrestore(pll->lock, flags);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -773,7 +773,7 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
|
||||
XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
|
||||
MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
|
||||
MUX8("msenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
|
||||
MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
|
||||
MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
|
||||
MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
|
||||
MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
|
||||
|
|
@ -782,7 +782,7 @@ static struct tegra_periph_init_data periph_clks[] = {
|
|||
NODIV("sor1", mux_clkm_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 15, MASK(1), 183, 0, tegra_clk_sor1, &sor1_lock),
|
||||
MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
|
||||
MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
|
||||
MUX("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, TEGRA_PERIPH_ON_APB, tegra_clk_vi_i2c),
|
||||
I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),
|
||||
MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),
|
||||
MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
|
||||
MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
|
||||
|
|
@ -829,6 +829,7 @@ static struct tegra_periph_init_data gate_clks[] = {
|
|||
GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
|
||||
GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
|
||||
GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
|
||||
GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
|
||||
};
|
||||
|
||||
static struct tegra_periph_init_data div_clks[] = {
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
|
|||
"pll_p", "pll_p_out4", "unused",
|
||||
"unused", "pll_x", "pll_x_out0" };
|
||||
|
||||
const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
|
||||
static const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
|
||||
.gen = gen4,
|
||||
.sclk_parents = sclk_parents,
|
||||
.cclk_g_parents = cclk_g_parents,
|
||||
|
|
@ -93,7 +93,7 @@ static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unu
|
|||
"unused", "unused", "unused", "unused",
|
||||
"dfllCPU_out" };
|
||||
|
||||
const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
|
||||
static const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
|
||||
.gen = gen5,
|
||||
.sclk_parents = sclk_parents_gen5,
|
||||
.cclk_g_parents = cclk_g_parents_gen5,
|
||||
|
|
@ -171,7 +171,7 @@ static void __init tegra_sclk_init(void __iomem *clk_base,
|
|||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
void __init tegra_super_clk_init(void __iomem *clk_base,
|
||||
static void __init tegra_super_clk_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *params,
|
||||
|
|
|
|||
|
|
@ -59,8 +59,8 @@
|
|||
#define PLLC3_MISC3 0x50c
|
||||
|
||||
#define PLLM_BASE 0x90
|
||||
#define PLLM_MISC0 0x9c
|
||||
#define PLLM_MISC1 0x98
|
||||
#define PLLM_MISC2 0x9c
|
||||
#define PLLP_BASE 0xa0
|
||||
#define PLLP_MISC0 0xac
|
||||
#define PLLP_MISC1 0x680
|
||||
|
|
@ -99,7 +99,7 @@
|
|||
#define PLLC4_MISC0 0x5a8
|
||||
#define PLLC4_OUT 0x5e4
|
||||
#define PLLMB_BASE 0x5e8
|
||||
#define PLLMB_MISC0 0x5ec
|
||||
#define PLLMB_MISC1 0x5ec
|
||||
#define PLLA1_BASE 0x6a4
|
||||
#define PLLA1_MISC0 0x6a8
|
||||
#define PLLA1_MISC1 0x6ac
|
||||
|
|
@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = {
|
|||
};
|
||||
|
||||
static const char *mux_pllmcp_clkm[] = {
|
||||
"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
|
||||
"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
|
||||
"pll_p",
|
||||
};
|
||||
#define mux_pllmcp_clkm_idx NULL
|
||||
|
||||
|
|
@ -367,12 +368,12 @@ static const char *mux_pllmcp_clkm[] = {
|
|||
/* PLLMB */
|
||||
#define PLLMB_BASE_LOCK (1 << 27)
|
||||
|
||||
#define PLLMB_MISC0_LOCK_OVERRIDE (1 << 18)
|
||||
#define PLLMB_MISC0_IDDQ (1 << 17)
|
||||
#define PLLMB_MISC0_LOCK_ENABLE (1 << 16)
|
||||
#define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18)
|
||||
#define PLLMB_MISC1_IDDQ (1 << 17)
|
||||
#define PLLMB_MISC1_LOCK_ENABLE (1 << 16)
|
||||
|
||||
#define PLLMB_MISC0_DEFAULT_VALUE 0x00030000
|
||||
#define PLLMB_MISC0_WRITE_MASK 0x0007ffff
|
||||
#define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
|
||||
#define PLLMB_MISC1_WRITE_MASK 0x0007ffff
|
||||
|
||||
/* PLLP */
|
||||
#define PLLP_BASE_OVERRIDE (1 << 28)
|
||||
|
|
@ -457,7 +458,8 @@ static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
|
|||
PLLCX_MISC3_WRITE_MASK);
|
||||
}
|
||||
|
||||
void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx)
|
||||
static void tegra210_pllcx_set_defaults(const char *name,
|
||||
struct tegra_clk_pll *pllcx)
|
||||
{
|
||||
pllcx->params->defaults_set = true;
|
||||
|
||||
|
|
@ -482,22 +484,22 @@ void tegra210_pllcx_set_defaults(const char *name, struct tegra_clk_pll *pllcx)
|
|||
udelay(1);
|
||||
}
|
||||
|
||||
void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
{
|
||||
tegra210_pllcx_set_defaults("PLL_C", pllcx);
|
||||
}
|
||||
|
||||
void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
{
|
||||
tegra210_pllcx_set_defaults("PLL_C2", pllcx);
|
||||
}
|
||||
|
||||
void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
{
|
||||
tegra210_pllcx_set_defaults("PLL_C3", pllcx);
|
||||
}
|
||||
|
||||
void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
|
||||
{
|
||||
tegra210_pllcx_set_defaults("PLL_A1", pllcx);
|
||||
}
|
||||
|
|
@ -507,7 +509,7 @@ void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
|
|||
* PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
|
||||
* Fractional SDM is allowed to provide exact audio rates.
|
||||
*/
|
||||
void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
|
||||
static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
|
||||
{
|
||||
u32 mask;
|
||||
u32 val = readl_relaxed(clk_base + plla->params->base_reg);
|
||||
|
|
@ -559,7 +561,7 @@ void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
|
|||
* PLLD
|
||||
* PLL with fractional SDM.
|
||||
*/
|
||||
void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
|
||||
static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
|
||||
{
|
||||
u32 val;
|
||||
u32 mask = 0xffff;
|
||||
|
|
@ -698,7 +700,7 @@ static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
|
|||
udelay(1);
|
||||
}
|
||||
|
||||
void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
|
||||
static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
|
||||
{
|
||||
plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
|
||||
PLLD2_MISC1_CFG_DEFAULT_VALUE,
|
||||
|
|
@ -706,7 +708,7 @@ void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
|
|||
PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
|
||||
}
|
||||
|
||||
void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
|
||||
static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
|
||||
{
|
||||
plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
|
||||
PLLDP_MISC1_CFG_DEFAULT_VALUE,
|
||||
|
|
@ -719,7 +721,7 @@ void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
|
|||
* Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
|
||||
* VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
|
||||
*/
|
||||
void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
|
||||
static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
|
||||
{
|
||||
plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
|
||||
}
|
||||
|
|
@ -728,7 +730,7 @@ void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
|
|||
* PLLRE
|
||||
* VCO is exposed to the clock tree directly along with post-divider output
|
||||
*/
|
||||
void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
|
||||
static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
|
||||
{
|
||||
u32 mask;
|
||||
u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
|
||||
|
|
@ -780,13 +782,13 @@ static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
|
|||
{
|
||||
unsigned long input_rate;
|
||||
|
||||
if (!IS_ERR_OR_NULL(hw->clk)) {
|
||||
/* cf rate */
|
||||
if (!IS_ERR_OR_NULL(hw->clk))
|
||||
input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
|
||||
/* cf rate */
|
||||
input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
|
||||
} else {
|
||||
else
|
||||
input_rate = 38400000;
|
||||
}
|
||||
|
||||
input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
|
||||
|
||||
switch (input_rate) {
|
||||
case 12000000:
|
||||
|
|
@ -841,7 +843,7 @@ static void pllx_check_defaults(struct tegra_clk_pll *pll)
|
|||
PLLX_MISC5_WRITE_MASK);
|
||||
}
|
||||
|
||||
void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
|
||||
static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
|
||||
{
|
||||
u32 val;
|
||||
u32 step_a, step_b;
|
||||
|
|
@ -901,7 +903,7 @@ void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
|
|||
}
|
||||
|
||||
/* PLLMB */
|
||||
void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
|
||||
static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
|
||||
{
|
||||
u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
|
||||
|
||||
|
|
@ -914,15 +916,15 @@ void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
|
|||
* PLL is ON: check if defaults already set, then set those
|
||||
* that can be updated in flight.
|
||||
*/
|
||||
val = PLLMB_MISC0_DEFAULT_VALUE & (~PLLMB_MISC0_IDDQ);
|
||||
mask = PLLMB_MISC0_LOCK_ENABLE | PLLMB_MISC0_LOCK_OVERRIDE;
|
||||
val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);
|
||||
mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;
|
||||
_pll_misc_chk_default(clk_base, pllmb->params, 0, val,
|
||||
~mask & PLLMB_MISC0_WRITE_MASK);
|
||||
~mask & PLLMB_MISC1_WRITE_MASK);
|
||||
|
||||
/* Enable lock detect */
|
||||
val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
|
||||
val &= ~mask;
|
||||
val |= PLLMB_MISC0_DEFAULT_VALUE & mask;
|
||||
val |= PLLMB_MISC1_DEFAULT_VALUE & mask;
|
||||
writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
|
||||
udelay(1);
|
||||
|
||||
|
|
@ -930,7 +932,7 @@ void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
|
|||
}
|
||||
|
||||
/* set IDDQ, enable lock detect */
|
||||
writel_relaxed(PLLMB_MISC0_DEFAULT_VALUE,
|
||||
writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
|
||||
clk_base + pllmb->params->ext_misc_reg[0]);
|
||||
udelay(1);
|
||||
}
|
||||
|
|
@ -960,7 +962,7 @@ static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
|
|||
~mask & PLLP_MISC1_WRITE_MASK);
|
||||
}
|
||||
|
||||
void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
|
||||
static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
|
||||
{
|
||||
u32 mask;
|
||||
u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
|
||||
|
|
@ -1022,7 +1024,7 @@ static void pllu_check_defaults(struct tegra_clk_pll *pll, bool hw_control)
|
|||
~mask & PLLU_MISC1_WRITE_MASK);
|
||||
}
|
||||
|
||||
void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
|
||||
static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
|
||||
{
|
||||
u32 val = readl_relaxed(clk_base + pllu->params->base_reg);
|
||||
|
||||
|
|
@ -1212,8 +1214,9 @@ static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
|
|||
cfg->m *= PLL_SDM_COEFF;
|
||||
}
|
||||
|
||||
unsigned long tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
|
||||
unsigned long parent_rate)
|
||||
static unsigned long
|
||||
tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long vco_min = params->vco_min;
|
||||
|
||||
|
|
@ -1386,7 +1389,7 @@ static struct tegra_clk_pll_params pll_c_params = {
|
|||
.mdiv_default = 3,
|
||||
.div_nmp = &pllc_nmp,
|
||||
.freq_table = pll_cx_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.set_defaults = _pllc_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1425,7 +1428,7 @@ static struct tegra_clk_pll_params pll_c2_params = {
|
|||
.ext_misc_reg[2] = PLLC2_MISC2,
|
||||
.ext_misc_reg[3] = PLLC2_MISC3,
|
||||
.freq_table = pll_cx_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.set_defaults = _pllc2_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1455,7 +1458,7 @@ static struct tegra_clk_pll_params pll_c3_params = {
|
|||
.ext_misc_reg[2] = PLLC3_MISC2,
|
||||
.ext_misc_reg[3] = PLLC3_MISC3,
|
||||
.freq_table = pll_cx_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.set_defaults = _pllc3_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1505,7 +1508,6 @@ static struct tegra_clk_pll_params pll_c4_vco_params = {
|
|||
.base_reg = PLLC4_BASE,
|
||||
.misc_reg = PLLC4_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.max_p = PLL_QLIN_PDIV_MAX,
|
||||
.ext_misc_reg[0] = PLLC4_MISC0,
|
||||
|
|
@ -1517,8 +1519,7 @@ static struct tegra_clk_pll_params pll_c4_vco_params = {
|
|||
.div_nmp = &pllss_nmp,
|
||||
.freq_table = pll_c4_vco_freq_table,
|
||||
.set_defaults = tegra210_pllc4_set_defaults,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
|
||||
TEGRA_PLL_VCO_OUT,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
||||
|
|
@ -1559,15 +1560,15 @@ static struct tegra_clk_pll_params pll_m_params = {
|
|||
.vco_min = 800000000,
|
||||
.vco_max = 1866000000,
|
||||
.base_reg = PLLM_BASE,
|
||||
.misc_reg = PLLM_MISC1,
|
||||
.misc_reg = PLLM_MISC2,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.iddq_reg = PLLM_MISC0,
|
||||
.iddq_reg = PLLM_MISC2,
|
||||
.iddq_bit_idx = PLLM_IDDQ_BIT,
|
||||
.max_p = PLL_QLIN_PDIV_MAX,
|
||||
.ext_misc_reg[0] = PLLM_MISC0,
|
||||
.ext_misc_reg[0] = PLLM_MISC1,
|
||||
.ext_misc_reg[0] = PLLM_MISC2,
|
||||
.ext_misc_reg[1] = PLLM_MISC1,
|
||||
.round_p_to_pdiv = pll_qlin_p_to_pdiv,
|
||||
.pdiv_tohw = pll_qlin_pdiv_to_hw,
|
||||
.div_nmp = &pllm_nmp,
|
||||
|
|
@ -1586,19 +1587,18 @@ static struct tegra_clk_pll_params pll_mb_params = {
|
|||
.vco_min = 800000000,
|
||||
.vco_max = 1866000000,
|
||||
.base_reg = PLLMB_BASE,
|
||||
.misc_reg = PLLMB_MISC0,
|
||||
.misc_reg = PLLMB_MISC1,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLMB_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.iddq_reg = PLLMB_MISC0,
|
||||
.iddq_reg = PLLMB_MISC1,
|
||||
.iddq_bit_idx = PLLMB_IDDQ_BIT,
|
||||
.max_p = PLL_QLIN_PDIV_MAX,
|
||||
.ext_misc_reg[0] = PLLMB_MISC0,
|
||||
.ext_misc_reg[0] = PLLMB_MISC1,
|
||||
.round_p_to_pdiv = pll_qlin_p_to_pdiv,
|
||||
.pdiv_tohw = pll_qlin_pdiv_to_hw,
|
||||
.div_nmp = &pllm_nmp,
|
||||
.freq_table = pll_m_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.set_defaults = tegra210_pllmb_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1671,7 +1671,6 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
|
|||
.base_reg = PLLRE_BASE,
|
||||
.misc_reg = PLLRE_MISC0,
|
||||
.lock_mask = PLLRE_MISC_LOCK,
|
||||
.lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.max_p = PLL_QLIN_PDIV_MAX,
|
||||
.ext_misc_reg[0] = PLLRE_MISC0,
|
||||
|
|
@ -1681,8 +1680,7 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
|
|||
.pdiv_tohw = pll_qlin_pdiv_to_hw,
|
||||
.div_nmp = &pllre_nmp,
|
||||
.freq_table = pll_re_vco_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_VCO_OUT,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,
|
||||
.set_defaults = tegra210_pllre_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1712,7 +1710,6 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
.base_reg = PLLP_BASE,
|
||||
.misc_reg = PLLP_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLP_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.iddq_reg = PLLP_MISC0,
|
||||
.iddq_bit_idx = PLLXP_IDDQ_BIT,
|
||||
|
|
@ -1721,8 +1718,7 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
.div_nmp = &pllp_nmp,
|
||||
.freq_table = pll_p_freq_table,
|
||||
.fixed_rate = 408000000,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_VCO_OUT,
|
||||
.flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
|
||||
.set_defaults = tegra210_pllp_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1750,7 +1746,7 @@ static struct tegra_clk_pll_params pll_a1_params = {
|
|||
.ext_misc_reg[2] = PLLA1_MISC2,
|
||||
.ext_misc_reg[3] = PLLA1_MISC3,
|
||||
.freq_table = pll_cx_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.set_defaults = _plla1_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -1787,7 +1783,6 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.base_reg = PLLA_BASE,
|
||||
.misc_reg = PLLA_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLA_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.round_p_to_pdiv = pll_qlin_p_to_pdiv,
|
||||
.pdiv_tohw = pll_qlin_pdiv_to_hw,
|
||||
|
|
@ -1802,8 +1797,7 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.ext_misc_reg[1] = PLLA_MISC1,
|
||||
.ext_misc_reg[2] = PLLA_MISC2,
|
||||
.freq_table = pll_a_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW |
|
||||
TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,
|
||||
.set_defaults = tegra210_plla_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
.set_gain = tegra210_clk_pll_set_gain,
|
||||
|
|
@ -1836,7 +1830,6 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.base_reg = PLLD_BASE,
|
||||
.misc_reg = PLLD_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLD_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
.iddq_reg = PLLD_MISC0,
|
||||
.iddq_bit_idx = PLLD_IDDQ_BIT,
|
||||
|
|
@ -1850,7 +1843,7 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.ext_misc_reg[0] = PLLD_MISC0,
|
||||
.ext_misc_reg[1] = PLLD_MISC1,
|
||||
.freq_table = pll_d_freq_table,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.mdiv_default = 1,
|
||||
.set_defaults = tegra210_plld_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
|
|
@ -1876,7 +1869,6 @@ static struct tegra_clk_pll_params pll_d2_params = {
|
|||
.base_reg = PLLD2_BASE,
|
||||
.misc_reg = PLLD2_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.iddq_reg = PLLD2_BASE,
|
||||
.iddq_bit_idx = PLLSS_IDDQ_BIT,
|
||||
|
|
@ -1897,7 +1889,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
|
|||
.mdiv_default = 1,
|
||||
.freq_table = tegra210_pll_d2_freq_table,
|
||||
.set_defaults = tegra210_plld2_set_defaults,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
.set_gain = tegra210_clk_pll_set_gain,
|
||||
.adjust_vco = tegra210_clk_adjust_vco_min,
|
||||
|
|
@ -1920,7 +1912,6 @@ static struct tegra_clk_pll_params pll_dp_params = {
|
|||
.base_reg = PLLDP_BASE,
|
||||
.misc_reg = PLLDP_MISC,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
.iddq_reg = PLLDP_BASE,
|
||||
.iddq_bit_idx = PLLSS_IDDQ_BIT,
|
||||
|
|
@ -1941,7 +1932,7 @@ static struct tegra_clk_pll_params pll_dp_params = {
|
|||
.mdiv_default = 1,
|
||||
.freq_table = pll_dp_freq_table,
|
||||
.set_defaults = tegra210_plldp_set_defaults,
|
||||
.flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
|
||||
.flags = TEGRA_PLL_USE_LOCK,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
.set_gain = tegra210_clk_pll_set_gain,
|
||||
.adjust_vco = tegra210_clk_adjust_vco_min,
|
||||
|
|
@ -1973,7 +1964,6 @@ static struct tegra_clk_pll_params pll_u_vco_params = {
|
|||
.base_reg = PLLU_BASE,
|
||||
.misc_reg = PLLU_MISC0,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLU_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
.iddq_reg = PLLU_MISC0,
|
||||
.iddq_bit_idx = PLLU_IDDQ_BIT,
|
||||
|
|
@ -1983,8 +1973,7 @@ static struct tegra_clk_pll_params pll_u_vco_params = {
|
|||
.pdiv_tohw = pll_qlin_pdiv_to_hw,
|
||||
.div_nmp = &pllu_nmp,
|
||||
.freq_table = pll_u_freq_table,
|
||||
.flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
|
||||
TEGRA_PLL_VCO_OUT,
|
||||
.flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
|
||||
.set_defaults = tegra210_pllu_set_defaults,
|
||||
.calc_rate = tegra210_pll_fixed_mdiv_cfg,
|
||||
};
|
||||
|
|
@ -2218,6 +2207,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
|
||||
[tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
|
||||
[tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
|
||||
[tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
|
||||
};
|
||||
|
||||
static struct tegra_devclk devclks[] __initdata = {
|
||||
|
|
@ -2519,7 +2509,7 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
|
|||
|
||||
/* PLLU_VCO */
|
||||
val = readl(clk_base + pll_u_vco_params.base_reg);
|
||||
val &= ~BIT(24); /* disable PLLU_OVERRIDE */
|
||||
val &= ~PLLU_BASE_OVERRIDE; /* disable PLLU_OVERRIDE */
|
||||
writel(val, clk_base + pll_u_vco_params.base_reg);
|
||||
|
||||
clk = tegra_clk_register_pllre("pll_u_vco", "pll_ref", clk_base, pmc,
|
||||
|
|
@ -2738,8 +2728,6 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
|
||||
{ TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
|
||||
{ TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
|
||||
{ TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
|
||||
{ TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
|
||||
{ TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
|
||||
{ TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
|
||||
|
|
|
|||
|
|
@ -78,6 +78,9 @@ static int vco_set(struct clk_icst *icst, struct icst_vco vco)
|
|||
ret = regmap_read(icst->map, icst->vcoreg_off, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Mask the 18 bits used by the VCO */
|
||||
val &= ~0x7ffff;
|
||||
val |= vco.v | (vco.r << 9) | (vco.s << 16);
|
||||
|
||||
/* This magic unlocks the VCO so it can be controlled */
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@
|
|||
/* 104 */
|
||||
/* 105 */
|
||||
#define TEGRA210_CLK_D_AUDIO 106
|
||||
/* 107 ( affects abp -> ape) */
|
||||
#define TEGRA210_CLK_APB2APE 107
|
||||
/* 108 */
|
||||
/* 109 */
|
||||
/* 110 */
|
||||
|
|
|
|||
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