MIPS: BCM63XX: Prepare irq code to handle different external irq hardware implementation.
External irq only works for 6348, change code to prepare support of other CPUs. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2895/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maxime Bizon
Ralf Baechle
Родитель
f61cced993
Коммит
37c42a741f
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@ -25,18 +25,32 @@ static void __dispatch_internal(void) __maybe_unused;
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#ifdef CONFIG_BCM63XX_CPU_6338
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#define irq_stat_reg PERF_IRQSTAT_6338_REG
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#define irq_mask_reg PERF_IRQMASK_6338_REG
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#define is_ext_irq_cascaded 0
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#define ext_irq_start 0
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#define ext_irq_end 0
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6345
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#define irq_stat_reg PERF_IRQSTAT_6345_REG
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#define irq_mask_reg PERF_IRQMASK_6345_REG
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#define is_ext_irq_cascaded 0
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#define ext_irq_start 0
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#define ext_irq_end 0
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6348
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#define irq_stat_reg PERF_IRQSTAT_6348_REG
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#define irq_mask_reg PERF_IRQMASK_6348_REG
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#define dispatch_internal __dispatch_internal
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#define is_ext_irq_cascaded 0
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#define ext_irq_start 0
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#define ext_irq_end 0
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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#define irq_stat_reg PERF_IRQSTAT_6358_REG
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#define irq_mask_reg PERF_IRQMASK_6358_REG
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#define dispatch_internal __dispatch_internal
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#define is_ext_irq_cascaded 1
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#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
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#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
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#endif
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#define dispatch_internal __dispatch_internal
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@ -51,6 +65,8 @@ static inline void bcm63xx_init_irq(void)
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static u32 irq_stat_addr, irq_mask_addr;
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static void (*dispatch_internal)(void);
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static int is_ext_irq_cascaded;
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static unsigned int ext_irq_start, ext_irq_end;
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static void bcm63xx_init_irq(void)
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{
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@ -73,6 +89,9 @@ static void bcm63xx_init_irq(void)
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case BCM6358_CPU_ID:
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irq_stat_addr += PERF_IRQSTAT_6358_REG;
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irq_mask_addr += PERF_IRQMASK_6358_REG;
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is_ext_irq_cascaded = 1;
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ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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break;
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default:
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BUG();
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@ -84,6 +103,10 @@ static void bcm63xx_init_irq(void)
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static inline void handle_internal(int intbit)
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{
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if (is_ext_irq_cascaded &&
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intbit >= ext_irq_start && intbit <= ext_irq_end)
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do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
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else
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do_IRQ(intbit + IRQ_INTERNAL_BASE);
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}
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@ -128,6 +151,7 @@ asmlinkage void plat_irq_dispatch(void)
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do_IRQ(7);
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if (cause & CAUSEF_IP2)
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dispatch_internal();
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if (!is_ext_irq_cascaded) {
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if (cause & CAUSEF_IP3)
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do_IRQ(IRQ_EXT_0);
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if (cause & CAUSEF_IP4)
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@ -136,6 +160,7 @@ asmlinkage void plat_irq_dispatch(void)
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do_IRQ(IRQ_EXT_2);
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if (cause & CAUSEF_IP6)
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do_IRQ(IRQ_EXT_3);
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}
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} while (1);
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}
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@ -143,9 +168,8 @@ asmlinkage void plat_irq_dispatch(void)
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* internal IRQs operations: only mask/unmask on PERF irq mask
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* register.
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*/
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static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
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static void internal_irq_mask(unsigned int irq)
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{
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unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
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u32 mask;
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mask = bcm_readl(irq_mask_addr);
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@ -153,9 +177,8 @@ static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
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bcm_writel(mask, irq_mask_addr);
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}
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static void bcm63xx_internal_irq_unmask(struct irq_data *d)
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static void internal_irq_unmask(unsigned int irq)
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{
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unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
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u32 mask;
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mask = bcm_readl(irq_mask_addr);
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@ -163,33 +186,47 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
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bcm_writel(mask, irq_mask_addr);
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}
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static void bcm63xx_internal_irq_mask(struct irq_data *d)
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{
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internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
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}
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static void bcm63xx_internal_irq_unmask(struct irq_data *d)
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{
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internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
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}
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/*
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* external IRQs operations: mask/unmask and clear on PERF external
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* irq control register.
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*/
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static void bcm63xx_external_irq_mask(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXT_BASE;
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg;
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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reg &= ~EXTIRQ_CFG_MASK(irq);
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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if (is_ext_irq_cascaded)
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internal_irq_mask(irq + ext_irq_start);
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}
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static void bcm63xx_external_irq_unmask(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXT_BASE;
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg;
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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reg |= EXTIRQ_CFG_MASK(irq);
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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if (is_ext_irq_cascaded)
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internal_irq_unmask(irq + ext_irq_start);
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}
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static void bcm63xx_external_irq_clear(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXT_BASE;
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg;
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reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
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@ -197,25 +234,10 @@ static void bcm63xx_external_irq_clear(struct irq_data *d)
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bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
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}
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static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
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{
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set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
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irq_enable_hazard();
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bcm63xx_external_irq_unmask(d);
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return 0;
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}
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static void bcm63xx_external_irq_shutdown(struct irq_data *d)
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{
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bcm63xx_external_irq_mask(d);
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clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
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irq_disable_hazard();
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}
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static int bcm63xx_external_irq_set_type(struct irq_data *d,
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unsigned int flow_type)
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{
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unsigned int irq = d->irq - IRQ_EXT_BASE;
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg;
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flow_type &= IRQ_TYPE_SENSE_MASK;
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@ -275,9 +297,6 @@ static struct irq_chip bcm63xx_internal_irq_chip = {
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static struct irq_chip bcm63xx_external_irq_chip = {
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.name = "bcm63xx_epic",
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.irq_startup = bcm63xx_external_irq_startup,
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.irq_shutdown = bcm63xx_external_irq_shutdown,
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.irq_ack = bcm63xx_external_irq_clear,
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.irq_mask = bcm63xx_external_irq_mask,
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@ -292,6 +311,12 @@ static struct irqaction cpu_ip2_cascade_action = {
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.flags = IRQF_NO_THREAD,
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};
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static struct irqaction cpu_ext_cascade_action = {
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.handler = no_action,
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.name = "cascade_extirq",
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.flags = IRQF_NO_THREAD,
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};
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void __init arch_init_irq(void)
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{
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int i;
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@ -302,9 +327,14 @@ void __init arch_init_irq(void)
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irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
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handle_level_irq);
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for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
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for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + 4; ++i)
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irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
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handle_edge_irq);
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setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
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if (!is_ext_irq_cascaded) {
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for (i = 3; i < 7; ++i)
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setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
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}
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setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
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}
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@ -3,13 +3,11 @@
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#include <bcm63xx_cpu.h>
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#define IRQ_MIPS_BASE 0
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#define IRQ_INTERNAL_BASE 8
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#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3)
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#define IRQ_EXT_0 (IRQ_EXT_BASE + 0)
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#define IRQ_EXT_1 (IRQ_EXT_BASE + 1)
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#define IRQ_EXT_2 (IRQ_EXT_BASE + 2)
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#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
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#define IRQ_EXTERNAL_BASE 100
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#define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0)
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#define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1)
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#define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2)
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#define IRQ_EXT_3 (IRQ_EXTERNAL_BASE + 3)
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#endif /* ! BCM63XX_IRQ_H_ */
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@ -0,0 +1,7 @@
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#ifndef __ASM_MACH_BCM63XX_IRQ_H
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#define __ASM_MACH_BCM63XX_IRQ_H
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#define NR_IRQS 128
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#define MIPS_CPU_IRQ_BASE 0
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#endif
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