x86/mce/AMD: Redo error logging from APIC LVT interrupt handlers
We have support for the new SMCA MCA_DE{STAT,ADDR} registers in Linux.
So we've used these registers in place of MCA_{STATUS,ADDR} on SMCA
systems.
However, the guidance for current SMCA implementations of is to continue
using MCA_{STATUS,ADDR} and to use MCA_DE{STAT,ADDR} only if a Deferred
error was not found in the former registers. If we logged a Deferred
error in MCA_STATUS then we should also clear MCA_DESTAT. This also
means we shouldn't clear MCA_CONFIG[LogDeferredInMcaStat].
Rework __log_error() to only log an error and add helpers for the
different error types being logged from the corresponding interrupt
handlers.
Boris: carve out common functionality into a _log_error_bank(). Cleanup
comments, check MCi_STATUS bits before reading MSRs. Streamline flow.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1493147772-2721-1-git-send-email-Yazen.Ghannam@amd.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Yazen Ghannam
Thomas Gleixner
Родитель
473e90b2e8
Коммит
37d43acfd7
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@ -471,20 +471,6 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
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*/
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smca_high |= BIT(0);
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/*
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* SMCA logs Deferred Error information in MCA_DE{STAT,ADDR}
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* registers with the option of additionally logging to
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* MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set.
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*
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* This bit is usually set by BIOS to retain the old behavior
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* for OSes that don't use the new registers. Linux supports the
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* new registers so let's disable that additional logging here.
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*
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* MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high
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* portion of the MSR).
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*/
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smca_high &= ~BIT(2);
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/*
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* SMCA sets the Deferred Error Interrupt type per bank.
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*
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@ -755,37 +741,19 @@ out_err:
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}
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EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
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static void
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__log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc)
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static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
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{
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u32 msr_status = msr_ops.status(bank);
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u32 msr_addr = msr_ops.addr(bank);
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struct mce m;
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u64 status;
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WARN_ON_ONCE(deferred_err && threshold_err);
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if (deferred_err && mce_flags.smca) {
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msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank);
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msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank);
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}
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rdmsrl(msr_status, status);
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if (!(status & MCI_STATUS_VAL))
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return;
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mce_setup(&m);
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m.status = status;
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m.misc = misc;
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m.bank = bank;
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m.tsc = rdtsc();
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if (threshold_err)
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m.misc = misc;
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if (m.status & MCI_STATUS_ADDRV) {
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rdmsrl(msr_addr, m.addr);
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m.addr = addr;
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/*
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* Extract [55:<lsb>] where lsb is the least significant
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@ -806,8 +774,6 @@ __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc)
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}
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mce_log(&m);
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wrmsrl(msr_status, 0);
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}
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static inline void __smp_deferred_error_interrupt(void)
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@ -832,45 +798,85 @@ asmlinkage __visible void __irq_entry smp_trace_deferred_error_interrupt(void)
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exiting_ack_irq();
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}
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/*
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* Returns true if the logged error is deferred. False, otherwise.
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*/
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static inline bool
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_log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
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{
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u64 status, addr = 0;
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rdmsrl(msr_stat, status);
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if (!(status & MCI_STATUS_VAL))
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return false;
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if (status & MCI_STATUS_ADDRV)
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rdmsrl(msr_addr, addr);
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__log_error(bank, status, addr, misc);
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wrmsrl(status, 0);
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return status & MCI_STATUS_DEFERRED;
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}
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/*
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* We have three scenarios for checking for Deferred errors:
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*
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* 1) Non-SMCA systems check MCA_STATUS and log error if found.
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* 2) SMCA systems check MCA_STATUS. If error is found then log it and also
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* clear MCA_DESTAT.
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* 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
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* log it.
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*/
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static void log_error_deferred(unsigned int bank)
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{
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bool defrd;
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defrd = _log_error_bank(bank, msr_ops.status(bank),
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msr_ops.addr(bank), 0);
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if (!mce_flags.smca)
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return;
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/* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
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if (defrd) {
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wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
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return;
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}
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/*
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* Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
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* for a valid error.
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*/
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_log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
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MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
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}
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/* APIC interrupt handler for deferred errors */
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static void amd_deferred_error_interrupt(void)
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{
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unsigned int bank;
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u32 msr_status;
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u64 status;
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for (bank = 0; bank < mca_cfg.banks; ++bank) {
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msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank)
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: msr_ops.status(bank);
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for (bank = 0; bank < mca_cfg.banks; ++bank)
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log_error_deferred(bank);
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}
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rdmsrl(msr_status, status);
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if (!(status & MCI_STATUS_VAL) ||
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!(status & MCI_STATUS_DEFERRED))
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continue;
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__log_error(bank, true, false, 0);
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break;
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}
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static void log_error_thresholding(unsigned int bank, u64 misc)
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{
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_log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);
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}
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/*
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* APIC Interrupt Handler
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* Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
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* goes off when error_count reaches threshold_limit.
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*/
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/*
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* threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
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* the interrupt goes off when error_count reaches threshold_limit.
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* the handler will simply log mcelog w/ software defined bank number.
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*/
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static void amd_threshold_interrupt(void)
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{
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u32 low = 0, high = 0, address = 0;
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unsigned int bank, block, cpu = smp_processor_id();
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struct thresh_restart tr;
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/* assume first bank caused it */
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for (bank = 0; bank < mca_cfg.banks; ++bank) {
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if (!(per_cpu(bank_map, cpu) & (1 << bank)))
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continue;
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@ -893,23 +899,18 @@ static void amd_threshold_interrupt(void)
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(high & MASK_LOCKED_HI))
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continue;
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/*
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* Log the machine check that caused the threshold
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* event.
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*/
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if (high & MASK_OVERFLOW_HI)
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goto log;
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}
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}
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return;
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if (!(high & MASK_OVERFLOW_HI))
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continue;
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log:
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__log_error(bank, false, true, ((u64)high << 32) | low);
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/* Log the MCE which caused the threshold event. */
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log_error_thresholding(bank, ((u64)high << 32) | low);
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/* Reset threshold block after logging error. */
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memset(&tr, 0, sizeof(tr));
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tr.b = &per_cpu(threshold_banks, cpu)[bank]->blocks[block];
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threshold_restart_bank(&tr);
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}
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}
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}
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/*
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