Merge branch 'remotes/lorenzo/pci/cadence'
- Correct the Cadence cdns_pcie_writel() signature (Alan Douglas) - Add Cadence support for optional generic PHYs (Alan Douglas) - Add Cadence power management ops (Alan Douglas) - Remove redundant variable from Cadence driver (Colin Ian King) * remotes/lorenzo/pci/cadence: PCI: pcie-cadence-ep: Remove redundant variable mmc PCI: cadence: Add shutdown callback to host driver PCI: cadence: Add Power Management ops for host and EP dt-bindings: PCI: cadence: Add DT bindings for optional PHYs PCI: cadence: Add generic PHY support to host and EP drivers PCI: cadence: Update cdns_pcie_writel() function signature
This commit is contained in:
Bjorn Helgaas
Коммит
37f0e311bc
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@ -9,6 +9,9 @@ Required properties:
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Optional properties:
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- max-functions: Maximum number of functions that can be configured (default 1).
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- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
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than one in the list. If only one PHY listed it must manage all lanes.
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- phy-names: List of names to identify the PHY.
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Example:
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@ -19,4 +22,6 @@ pcie@fc000000 {
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reg-names = "reg", "mem";
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cdns,max-outbound-regions = <16>;
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max-functions = /bits/ 8 <8>;
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phys = <&ep_phy0 &ep_phy1>;
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phy-names = "pcie-lane0","pcie-lane1";
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};
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@ -24,6 +24,9 @@ Optional properties:
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translations (default 32)
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- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
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- device-id: The PCI device ID (16 bits, default is design dependent)
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- phys: From PHY bindings: List of Generic PHY phandles. One per lane if more
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than one in the list. If only one PHY listed it must manage all lanes.
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- phy-names: List of names to identify the PHY.
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Example:
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@ -57,4 +60,7 @@ pcie@fb000000 {
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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msi-parent = <&its_pci>;
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phys = <&pcie_phy0>;
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phy-names = "pcie-phy";
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};
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@ -238,7 +238,7 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
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struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
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struct cdns_pcie *pcie = &ep->pcie;
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u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
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u16 flags, mmc, mme;
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u16 flags, mme;
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/* Validate that the MSI feature is actually enabled. */
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flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
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@ -249,7 +249,6 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
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* Get the Multiple Message Enable bitfield from the Message Control
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* register.
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*/
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mmc = (flags & PCI_MSI_FLAGS_QMASK) >> 1;
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mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
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return mme;
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@ -439,6 +438,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
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struct pci_epc *epc;
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struct resource *res;
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int ret;
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int phy_count;
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ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
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if (!ep)
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@ -473,6 +473,12 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
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if (!ep->ob_addr)
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return -ENOMEM;
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ret = cdns_pcie_init_phy(dev, pcie);
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if (ret) {
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dev_err(dev, "failed to init phy\n");
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return ret;
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}
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platform_set_drvdata(pdev, pcie);
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pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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@ -521,6 +527,10 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
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err_get_sync:
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pm_runtime_disable(dev);
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cdns_pcie_disable_phy(pcie);
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phy_count = pcie->phy_count;
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while (phy_count--)
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device_link_del(pcie->link[phy_count]);
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return ret;
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}
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@ -528,6 +538,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
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static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct cdns_pcie *pcie = dev_get_drvdata(dev);
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int ret;
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ret = pm_runtime_put_sync(dev);
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@ -536,13 +547,14 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
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pm_runtime_disable(dev);
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/* The PCIe controller can't be disabled. */
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cdns_pcie_disable_phy(pcie);
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}
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static struct platform_driver cdns_pcie_ep_driver = {
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.driver = {
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.name = "cdns-pcie-ep",
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.of_match_table = cdns_pcie_ep_of_match,
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.pm = &cdns_pcie_pm_ops,
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},
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.probe = cdns_pcie_ep_probe,
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.shutdown = cdns_pcie_ep_shutdown,
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@ -58,6 +58,11 @@ static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
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return pcie->reg_base + (where & 0xfff);
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}
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/* Check that the link is up */
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if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
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return NULL;
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/* Clear AXI link-down status */
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
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/* Update Output registers for AXI region 0. */
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addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
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@ -239,6 +244,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
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struct cdns_pcie *pcie;
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struct resource *res;
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int ret;
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int phy_count;
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
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if (!bridge)
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@ -290,6 +296,13 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
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}
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pcie->mem_res = res;
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ret = cdns_pcie_init_phy(dev, pcie);
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if (ret) {
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dev_err(dev, "failed to init phy\n");
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return ret;
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}
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platform_set_drvdata(pdev, pcie);
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pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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@ -322,15 +335,35 @@ static int cdns_pcie_host_probe(struct platform_device *pdev)
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err_get_sync:
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pm_runtime_disable(dev);
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cdns_pcie_disable_phy(pcie);
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phy_count = pcie->phy_count;
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while (phy_count--)
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device_link_del(pcie->link[phy_count]);
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return ret;
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}
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static void cdns_pcie_shutdown(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct cdns_pcie *pcie = dev_get_drvdata(dev);
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int ret;
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ret = pm_runtime_put_sync(dev);
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if (ret < 0)
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dev_dbg(dev, "pm_runtime_put_sync failed\n");
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pm_runtime_disable(dev);
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cdns_pcie_disable_phy(pcie);
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}
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static struct platform_driver cdns_pcie_host_driver = {
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.driver = {
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.name = "cdns-pcie-host",
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.of_match_table = cdns_pcie_host_of_match,
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.pm = &cdns_pcie_pm_ops,
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},
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.probe = cdns_pcie_host_probe,
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.shutdown = cdns_pcie_shutdown,
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};
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builtin_platform_driver(cdns_pcie_host_driver);
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@ -124,3 +124,126 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);
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}
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void cdns_pcie_disable_phy(struct cdns_pcie *pcie)
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{
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int i = pcie->phy_count;
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while (i--) {
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phy_power_off(pcie->phy[i]);
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phy_exit(pcie->phy[i]);
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}
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}
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int cdns_pcie_enable_phy(struct cdns_pcie *pcie)
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{
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int ret;
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int i;
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for (i = 0; i < pcie->phy_count; i++) {
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ret = phy_init(pcie->phy[i]);
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if (ret < 0)
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goto err_phy;
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ret = phy_power_on(pcie->phy[i]);
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if (ret < 0) {
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phy_exit(pcie->phy[i]);
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goto err_phy;
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}
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}
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return 0;
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err_phy:
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while (--i >= 0) {
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phy_power_off(pcie->phy[i]);
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phy_exit(pcie->phy[i]);
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}
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return ret;
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}
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int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
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{
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struct device_node *np = dev->of_node;
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int phy_count;
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struct phy **phy;
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struct device_link **link;
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int i;
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int ret;
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const char *name;
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phy_count = of_property_count_strings(np, "phy-names");
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if (phy_count < 1) {
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dev_err(dev, "no phy-names. PHY will not be initialized\n");
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pcie->phy_count = 0;
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return 0;
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}
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phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
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if (!phy)
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return -ENOMEM;
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link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
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if (!link)
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return -ENOMEM;
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for (i = 0; i < phy_count; i++) {
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of_property_read_string_index(np, "phy-names", i, &name);
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phy[i] = devm_phy_optional_get(dev, name);
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if (IS_ERR(phy))
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return PTR_ERR(phy);
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link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
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if (!link[i]) {
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ret = -EINVAL;
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goto err_link;
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}
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}
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pcie->phy_count = phy_count;
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pcie->phy = phy;
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pcie->link = link;
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ret = cdns_pcie_enable_phy(pcie);
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if (ret)
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goto err_link;
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return 0;
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err_link:
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while (--i >= 0)
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device_link_del(link[i]);
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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static int cdns_pcie_suspend_noirq(struct device *dev)
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{
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struct cdns_pcie *pcie = dev_get_drvdata(dev);
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cdns_pcie_disable_phy(pcie);
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return 0;
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}
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static int cdns_pcie_resume_noirq(struct device *dev)
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{
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struct cdns_pcie *pcie = dev_get_drvdata(dev);
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int ret;
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ret = cdns_pcie_enable_phy(pcie);
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if (ret) {
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dev_err(dev, "failed to enable phy\n");
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return ret;
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}
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return 0;
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}
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#endif
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const struct dev_pm_ops cdns_pcie_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq,
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cdns_pcie_resume_noirq)
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};
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@ -8,6 +8,7 @@
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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/*
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* Local Management Registers
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@ -165,6 +166,9 @@
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#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
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(CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
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/* AXI link down register */
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#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
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enum cdns_pcie_rp_bar {
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RP_BAR0,
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RP_BAR1,
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@ -229,6 +233,9 @@ struct cdns_pcie {
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struct resource *mem_res;
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bool is_rc;
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u8 bus;
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int phy_count;
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struct phy **phy;
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struct device_link **link;
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};
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/* Register access */
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@ -279,7 +286,7 @@ static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
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}
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static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
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u32 reg, u16 value)
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u32 reg, u32 value)
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{
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writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
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}
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@ -307,5 +314,9 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
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u32 r, u64 cpu_addr);
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void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
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void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
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int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
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int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
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extern const struct dev_pm_ops cdns_pcie_pm_ops;
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#endif /* _PCIE_CADENCE_H */
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