Merge branch 'rmobile-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x
* 'rmobile-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x: ARM: mach-shmobile: sh7372 CMT3 and CMT4 clock support ARM: mach-shmobile: sh7372 MSIOF clock support ARM: mach-shmobile: clock-sh7372: fixup USB-DMAC1 settings ARM: mach-shmobile: clock-sh73a0: tidyup CKSCR main clock selecter ARM: mach-shmobile: Remove 3DG/SGX from sh7372 INTCS ARM: mach-shmobile: mackerel: Add USB-DMA ID mmc: sdhi, mmcif: zboot: Correct clock disable logic ARM: mach-shmobile: ag5evm: SDHI requires waiting for idle ARM: static should be at beginning of declaration ARM: mach-shmobile: Use CMT2 for timer on sh7372 ARM: mach-shmobile: sh7372: Add USB-DMAC support
This commit is contained in:
Linus Torvalds
Коммит
380dc20088
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@ -82,7 +82,7 @@ asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
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/* Disable clock to MMC hardware block */
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__raw_writel(__raw_readl(SMSTPCR3) & (1 << 12), SMSTPCR3);
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__raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3);
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mmc_update_progress(MMC_PROGRESS_DONE);
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}
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@ -85,7 +85,7 @@ asmlinkage void mmc_loader(unsigned short *buf, unsigned long len)
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goto err;
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/* Disable clock to SDHI1 hardware block */
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__raw_writel(__raw_readl(SMSTPCR3) & (1 << 13), SMSTPCR3);
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__raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3);
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mmc_update_progress(MMC_PROGRESS_DONE);
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@ -341,6 +341,7 @@ static struct platform_device mipidsi0_device = {
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static struct sh_mobile_sdhi_info sdhi0_info = {
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.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
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.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
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.tmio_caps = MMC_CAP_SD_HIGHSPEED,
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.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
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};
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@ -382,7 +383,7 @@ void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
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}
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static struct sh_mobile_sdhi_info sh_sdhi1_info = {
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.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
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.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
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.tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
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.tmio_ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
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.set_pwr = ag5evm_sdhi1_set_pwr,
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@ -641,6 +641,8 @@ static struct usbhs_private usbhs0_private = {
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},
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.driver_param = {
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.buswait_bwait = 4,
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.d0_tx_id = SHDMA_SLAVE_USB0_TX,
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.d1_rx_id = SHDMA_SLAVE_USB0_RX,
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},
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},
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};
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@ -810,6 +812,8 @@ static struct usbhs_private usbhs1_private = {
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.buswait_bwait = 4,
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.pipe_type = usbhs1_pipe_cfg,
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.pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg),
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.d0_tx_id = SHDMA_SLAVE_USB1_TX,
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.d1_rx_id = SHDMA_SLAVE_USB1_RX,
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},
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},
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};
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@ -503,16 +503,17 @@ static struct clk *late_main_clks[] = {
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&sh7372_fsidivb_clk,
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};
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enum { MSTP001,
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enum { MSTP001, MSTP000,
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MSTP131, MSTP130,
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MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
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MSTP118, MSTP117, MSTP116, MSTP113,
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MSTP106, MSTP101, MSTP100,
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MSTP223,
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MSTP218, MSTP217, MSTP216,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
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MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
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MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
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MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
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MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
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MSTP405, MSTP404, MSTP403, MSTP400,
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MSTP_NR };
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#define MSTP(_parent, _reg, _bit, _flags) \
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@ -520,6 +521,7 @@ enum { MSTP001,
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
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[MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
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[MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
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[MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
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[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
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@ -538,14 +540,16 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
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[MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
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[MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
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[MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
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[MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
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[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
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[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
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[MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
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[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
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[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
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[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
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[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
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[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
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[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
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[MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
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[MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
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[MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
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@ -557,8 +561,12 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
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[MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
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[MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
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[MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
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[MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
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[MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
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[MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
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[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
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[MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
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};
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static struct clk_lookup lookups[] = {
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@ -609,6 +617,7 @@ static struct clk_lookup lookups[] = {
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
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CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
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CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
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CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
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CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
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@ -629,14 +638,16 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
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CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
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CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
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CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */
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CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
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CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
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CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
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CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
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CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
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CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
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CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
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@ -650,10 +661,14 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
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CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
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CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
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CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
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CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
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CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
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CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
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CLKDEV_DEV_ID("sh_cmt.4", &mstp_clks[MSTP405]), /* CMT4 */
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CLKDEV_DEV_ID("sh_cmt.3", &mstp_clks[MSTP404]), /* CMT3 */
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CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
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CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
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CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
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&div6_reparent_clks[DIV6_HDMI]),
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@ -365,7 +365,7 @@ void __init sh73a0_clock_init(void)
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__raw_writel(0x108, SD2CKCR);
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/* detect main clock parent */
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switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
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switch ((__raw_readl(CKSCR) >> 28) & 0x03) {
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case 0:
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main_clk.parent = &sh73a0_extal1_clk;
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break;
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@ -459,6 +459,10 @@ enum {
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SHDMA_SLAVE_SDHI2_TX,
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SHDMA_SLAVE_MMCIF_RX,
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SHDMA_SLAVE_MMCIF_TX,
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SHDMA_SLAVE_USB0_TX,
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SHDMA_SLAVE_USB0_RX,
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SHDMA_SLAVE_USB1_TX,
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SHDMA_SLAVE_USB1_RX,
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};
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extern struct clk sh7372_extal1_clk;
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@ -379,7 +379,7 @@ enum {
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/* BBIF2 */
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VPU,
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TSIF1,
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_3DG_SGX530,
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/* 3DG */
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_2DDMAC,
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IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
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IPMMU_IPMMUR, IPMMU_IPMMUR2,
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@ -436,7 +436,7 @@ static struct intc_vect intcs_vectors[] = {
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/* BBIF2 */
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INTCS_VECT(VPU, 0x980),
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INTCS_VECT(TSIF1, 0x9a0),
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INTCS_VECT(_3DG_SGX530, 0x9e0),
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/* 3DG */
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INTCS_VECT(_2DDMAC, 0xa00),
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INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
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INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
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@ -521,7 +521,7 @@ static struct intc_mask_reg intcs_mask_registers[] = {
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RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
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{ 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
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{ 0, 0, MSIOF, 0,
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_3DG_SGX530, 0, 0, 0 } },
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0, 0, 0, 0 } },
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{ 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
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{ 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
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0, 0, 0, 0 } },
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@ -561,7 +561,6 @@ static struct intc_prio_reg intcs_prio_registers[] = {
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TMU_TUNI2, TSIF1 } },
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{ 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
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{ 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
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{ 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX530, 0, 0 } },
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{ 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
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{ 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
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{ 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
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@ -169,35 +169,35 @@ static struct platform_device scif6_device = {
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};
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/* CMT */
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static struct sh_timer_config cmt10_platform_data = {
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.name = "CMT10",
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.channel_offset = 0x10,
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.timer_bit = 0,
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static struct sh_timer_config cmt2_platform_data = {
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.name = "CMT2",
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.channel_offset = 0x40,
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.timer_bit = 5,
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.clockevent_rating = 125,
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.clocksource_rating = 125,
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};
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static struct resource cmt10_resources[] = {
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static struct resource cmt2_resources[] = {
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[0] = {
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.name = "CMT10",
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.start = 0xe6138010,
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.end = 0xe613801b,
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.name = "CMT2",
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.start = 0xe6130040,
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.end = 0xe613004b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x0b00), /* CMT1_CMT10 */
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.start = evt2irq(0x0b80), /* CMT2 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cmt10_device = {
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static struct platform_device cmt2_device = {
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.name = "sh_cmt",
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.id = 10,
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.id = 2,
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.dev = {
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.platform_data = &cmt10_platform_data,
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.platform_data = &cmt2_platform_data,
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},
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.resource = cmt10_resources,
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.num_resources = ARRAY_SIZE(cmt10_resources),
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.resource = cmt2_resources,
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.num_resources = ARRAY_SIZE(cmt2_resources),
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};
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/* TMU */
|
||||
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@ -602,6 +602,150 @@ static struct platform_device dma2_device = {
|
|||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* USB-DMAC
|
||||
*/
|
||||
|
||||
unsigned int usbts_shift[] = {3, 4, 5};
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||||
|
||||
enum {
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||||
XMIT_SZ_8BYTE = 0,
|
||||
XMIT_SZ_16BYTE = 1,
|
||||
XMIT_SZ_32BYTE = 2,
|
||||
};
|
||||
|
||||
#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
|
||||
|
||||
static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
|
||||
{
|
||||
.offset = 0,
|
||||
}, {
|
||||
.offset = 0x20,
|
||||
},
|
||||
};
|
||||
|
||||
/* USB DMAC0 */
|
||||
static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
|
||||
{
|
||||
.slave_id = SHDMA_SLAVE_USB0_TX,
|
||||
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_USB0_RX,
|
||||
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_dmae_pdata usb_dma0_platform_data = {
|
||||
.slave = sh7372_usb_dmae0_slaves,
|
||||
.slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
|
||||
.channel = sh7372_usb_dmae_channels,
|
||||
.channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
|
||||
.ts_low_shift = 6,
|
||||
.ts_low_mask = 0xc0,
|
||||
.ts_high_shift = 0,
|
||||
.ts_high_mask = 0,
|
||||
.ts_shift = usbts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(usbts_shift),
|
||||
.dmaor_init = DMAOR_DME,
|
||||
.chcr_offset = 0x14,
|
||||
.chcr_ie_bit = 1 << 5,
|
||||
.dmaor_is_32bit = 1,
|
||||
.needs_tend_set = 1,
|
||||
.no_dmars = 1,
|
||||
};
|
||||
|
||||
static struct resource sh7372_usb_dmae0_resources[] = {
|
||||
{
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xe68a0020,
|
||||
.end = 0xe68a0064 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* VCR/SWR/DMICR */
|
||||
.start = 0xe68a0000,
|
||||
.end = 0xe68a0014 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels */
|
||||
.start = evt2irq(0x0a00),
|
||||
.end = evt2irq(0x0a00),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device usb_dma0_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 3,
|
||||
.resource = sh7372_usb_dmae0_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
|
||||
.dev = {
|
||||
.platform_data = &usb_dma0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* USB DMAC1 */
|
||||
static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
|
||||
{
|
||||
.slave_id = SHDMA_SLAVE_USB1_TX,
|
||||
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_USB1_RX,
|
||||
.chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_dmae_pdata usb_dma1_platform_data = {
|
||||
.slave = sh7372_usb_dmae1_slaves,
|
||||
.slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
|
||||
.channel = sh7372_usb_dmae_channels,
|
||||
.channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
|
||||
.ts_low_shift = 6,
|
||||
.ts_low_mask = 0xc0,
|
||||
.ts_high_shift = 0,
|
||||
.ts_high_mask = 0,
|
||||
.ts_shift = usbts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(usbts_shift),
|
||||
.dmaor_init = DMAOR_DME,
|
||||
.chcr_offset = 0x14,
|
||||
.chcr_ie_bit = 1 << 5,
|
||||
.dmaor_is_32bit = 1,
|
||||
.needs_tend_set = 1,
|
||||
.no_dmars = 1,
|
||||
};
|
||||
|
||||
static struct resource sh7372_usb_dmae1_resources[] = {
|
||||
{
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xe68c0020,
|
||||
.end = 0xe68c0064 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* VCR/SWR/DMICR */
|
||||
.start = 0xe68c0000,
|
||||
.end = 0xe68c0014 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels */
|
||||
.start = evt2irq(0x1d00),
|
||||
.end = evt2irq(0x1d00),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device usb_dma1_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 4,
|
||||
.resource = sh7372_usb_dmae1_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
|
||||
.dev = {
|
||||
.platform_data = &usb_dma1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* VPU */
|
||||
static struct uio_info vpu_platform_data = {
|
||||
.name = "VPU5HG",
|
||||
|
|
@ -818,7 +962,7 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
|
|||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&cmt10_device,
|
||||
&cmt2_device,
|
||||
&tmu00_device,
|
||||
&tmu01_device,
|
||||
};
|
||||
|
|
@ -829,6 +973,8 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
|
|||
&dma0_device,
|
||||
&dma1_device,
|
||||
&dma2_device,
|
||||
&usb_dma0_device,
|
||||
&usb_dma1_device,
|
||||
&vpu_device,
|
||||
&veu0_device,
|
||||
&veu1_device,
|
||||
|
|
|
|||
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