drm/msm/dpu: add SM8150 to hw catalog
This brings up basic video mode functionality for SM8150 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> [fixup max_linewidth warning] Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Jonathan Marek
Rob Clark
Родитель
fc3a69ec68
Коммит
386fced3f7
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@ -92,6 +92,22 @@ static const struct dpu_caps sc7180_dpu_caps = {
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_caps sm8150_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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.qseed_type = DPU_SSPP_SCALER_QSEED3,
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.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
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.ubwc_version = DPU_HW_UBWC_VER_30,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 4096,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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.max_hdeci_exp = MAX_HORZ_DECIMATION,
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_mdp_cfg sdm845_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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@ -183,6 +199,39 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
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},
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};
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static const struct dpu_ctl_cfg sm8150_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x1000, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
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},
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{
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.name = "ctl_1", .id = CTL_1,
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.base = 0x1200, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY)
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},
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{
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.name = "ctl_2", .id = CTL_2,
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.base = 0x1400, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG)
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},
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{
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.name = "ctl_3", .id = CTL_3,
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.base = 0x1600, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG)
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},
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{
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.name = "ctl_4", .id = CTL_4,
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.base = 0x1800, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG)
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},
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{
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.name = "ctl_5", .id = CTL_5,
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.base = 0x1a00, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG)
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},
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};
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/*************************************************************
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* SSPP sub blocks config
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*************************************************************/
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@ -338,6 +387,23 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
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&sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
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};
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/* SM8150 */
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static const struct dpu_lm_cfg sm8150_lm[] = {
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LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
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LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
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LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
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LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
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LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
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LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
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&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
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};
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/*************************************************************
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* DSPP sub blocks config
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*************************************************************/
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@ -357,6 +423,7 @@ static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = {
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static const struct dpu_dspp_cfg sc7180_dspp[] = {
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DSPP_BLK("dspp_0", DSPP_0, 0x54000),
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};
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/*************************************************************
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* PINGPONG sub blocks config
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*************************************************************/
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@ -399,6 +466,15 @@ static struct dpu_pingpong_cfg sc7180_pp[] = {
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800),
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};
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static const struct dpu_pingpong_cfg sm8150_pp[] = {
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000),
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800),
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PP_BLK("pingpong_2", PINGPONG_2, 0x71000),
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PP_BLK("pingpong_3", PINGPONG_3, 0x71800),
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PP_BLK("pingpong_4", PINGPONG_4, 0x72000),
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PP_BLK("pingpong_5", PINGPONG_5, 0x72800),
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};
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/*************************************************************
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* INTF sub blocks config
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*************************************************************/
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@ -424,6 +500,13 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
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INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK),
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};
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static const struct dpu_intf_cfg sm8150_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK),
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INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK),
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INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SC7180_MASK),
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INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SC7180_MASK),
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};
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/*************************************************************
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* VBIF sub blocks config
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*************************************************************/
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@ -454,6 +537,10 @@ static const struct dpu_reg_dma_cfg sdm845_regdma = {
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.base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
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};
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static const struct dpu_reg_dma_cfg sm8150_regdma = {
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.base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
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};
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/*************************************************************
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* PERF data config
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*************************************************************/
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@ -478,6 +565,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
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{.fl = 0, .lut = 0x0011222222335777},
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};
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static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
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{.fl = 0, .lut = 0x0011222222223357 },
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};
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static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
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{.fl = 10, .lut = 0x344556677},
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{.fl = 11, .lut = 0x3344556677},
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@ -562,6 +653,31 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
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},
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};
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static const struct dpu_perf_cfg sm8150_perf_data = {
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.max_bw_low = 12800000,
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.max_bw_high = 12800000,
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.min_core_ib = 2400000,
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.min_llcc_ib = 800000,
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.min_dram_ib = 800000,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sm8150_qos_linear),
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.entries = sm8150_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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};
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/*************************************************************
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* Hardware catalog init
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*************************************************************/
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@ -626,9 +742,40 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
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};
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}
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/*
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* sm8150_cfg_init(): populate sm8150 dpu sub-blocks reg offsets
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* and instance counts.
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*/
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static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
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{
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*dpu_cfg = (struct dpu_mdss_cfg){
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.caps = &sm8150_dpu_caps,
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.mdp_count = ARRAY_SIZE(sdm845_mdp),
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.mdp = sdm845_mdp,
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.ctl_count = ARRAY_SIZE(sm8150_ctl),
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.ctl = sm8150_ctl,
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.sspp_count = ARRAY_SIZE(sdm845_sspp),
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.sspp = sdm845_sspp,
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.mixer_count = ARRAY_SIZE(sm8150_lm),
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.mixer = sm8150_lm,
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.pingpong_count = ARRAY_SIZE(sm8150_pp),
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.pingpong = sm8150_pp,
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.intf_count = ARRAY_SIZE(sm8150_intf),
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.intf = sm8150_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.reg_dma_count = 1,
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.dma_cfg = sm8150_regdma,
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.perf = sm8150_perf_data,
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.mdss_irqs = 0x3ff,
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};
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}
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static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
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{ .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init},
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{ .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init},
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{ .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init},
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{ .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init},
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{ .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init},
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};
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@ -171,6 +171,7 @@ enum dpu_ctl {
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CTL_2,
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CTL_3,
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CTL_4,
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CTL_5,
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CTL_MAX
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};
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@ -180,6 +181,7 @@ enum dpu_pingpong {
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PINGPONG_2,
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PINGPONG_3,
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PINGPONG_4,
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PINGPONG_5,
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PINGPONG_S0,
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PINGPONG_MAX
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};
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