MIPS: CM: Add support for reporting CM cache errors
The CM cache error reporting code is not Malta specific and as such it should live in the mips-cm.c file. Moreover, CM2 and CM3 differ in the way cache errors are being recorded to the registers so extend the previous code to add support for the CM3 as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10646/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Markos Chandras
Ralf Baechle
Родитель
391057d915
Коммит
3885c2b463
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@ -47,6 +47,15 @@ extern phys_addr_t __mips_cm_phys_base(void);
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*/
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extern int mips_cm_is64;
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/**
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* mips_cm_error_report - Report CM cache errors
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*/
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#ifdef CONFIG_MIPS_CM
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extern void mips_cm_error_report(void);
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#else
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static inline void mips_cm_error_report(void) {}
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#endif
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/**
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* mips_cm_probe - probe for a Coherence Manager
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*
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@ -17,6 +17,125 @@ void __iomem *mips_cm_base;
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void __iomem *mips_cm_l2sync_base;
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int mips_cm_is64;
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static char *cm2_tr[8] = {
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"mem", "gcr", "gic", "mmio",
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"0x04", "cpc", "0x06", "0x07"
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};
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/* CM3 Tag ECC transation type */
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static char *cm3_tr[16] = {
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[0x0] = "ReqNoData",
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[0x1] = "0x1",
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[0x2] = "ReqWData",
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[0x3] = "0x3",
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[0x4] = "IReqNoResp",
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[0x5] = "IReqWResp",
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[0x6] = "IReqNoRespDat",
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[0x7] = "IReqWRespDat",
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[0x8] = "RespNoData",
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[0x9] = "RespDataFol",
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[0xa] = "RespWData",
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[0xb] = "RespDataOnly",
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[0xc] = "IRespNoData",
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[0xd] = "IRespDataFol",
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[0xe] = "IRespWData",
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[0xf] = "IRespDataOnly"
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};
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static char *cm2_cmd[32] = {
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[0x00] = "0x00",
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[0x01] = "Legacy Write",
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[0x02] = "Legacy Read",
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[0x03] = "0x03",
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[0x04] = "0x04",
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[0x05] = "0x05",
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[0x06] = "0x06",
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[0x07] = "0x07",
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[0x08] = "Coherent Read Own",
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[0x09] = "Coherent Read Share",
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[0x0a] = "Coherent Read Discard",
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[0x0b] = "Coherent Ready Share Always",
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[0x0c] = "Coherent Upgrade",
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[0x0d] = "Coherent Writeback",
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[0x0e] = "0x0e",
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[0x0f] = "0x0f",
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[0x10] = "Coherent Copyback",
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[0x11] = "Coherent Copyback Invalidate",
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[0x12] = "Coherent Invalidate",
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[0x13] = "Coherent Write Invalidate",
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[0x14] = "Coherent Completion Sync",
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[0x15] = "0x15",
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[0x16] = "0x16",
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[0x17] = "0x17",
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[0x18] = "0x18",
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[0x19] = "0x19",
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[0x1a] = "0x1a",
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[0x1b] = "0x1b",
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[0x1c] = "0x1c",
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[0x1d] = "0x1d",
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[0x1e] = "0x1e",
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[0x1f] = "0x1f"
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};
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/* CM3 Tag ECC command type */
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static char *cm3_cmd[16] = {
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[0x0] = "Legacy Read",
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[0x1] = "Legacy Write",
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[0x2] = "Coherent Read Own",
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[0x3] = "Coherent Read Share",
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[0x4] = "Coherent Read Discard",
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[0x5] = "Coherent Evicted",
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[0x6] = "Coherent Upgrade",
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[0x7] = "Coherent Upgrade for Store Conditional",
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[0x8] = "Coherent Writeback",
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[0x9] = "Coherent Write Invalidate",
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[0xa] = "0xa",
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[0xb] = "0xb",
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[0xc] = "0xc",
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[0xd] = "0xd",
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[0xe] = "0xe",
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[0xf] = "0xf"
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};
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/* CM3 Tag ECC command group */
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static char *cm3_cmd_group[8] = {
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[0x0] = "Normal",
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[0x1] = "Registers",
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[0x2] = "TLB",
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[0x3] = "0x3",
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[0x4] = "L1I",
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[0x5] = "L1D",
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[0x6] = "L3",
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[0x7] = "L2"
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};
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static char *cm2_core[8] = {
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"Invalid/OK", "Invalid/Data",
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"Shared/OK", "Shared/Data",
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"Modified/OK", "Modified/Data",
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"Exclusive/OK", "Exclusive/Data"
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};
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static char *cm2_causes[32] = {
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"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
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"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
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"0x08", "0x09", "0x0a", "0x0b",
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"0x0c", "0x0d", "0x0e", "0x0f",
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"0x10", "0x11", "0x12", "0x13",
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"0x14", "0x15", "0x16", "INTVN_WR_ERR",
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"INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
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"0x1c", "0x1d", "0x1e", "0x1f"
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};
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static char *cm3_causes[32] = {
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"0x0", "MP_CORRECTABLE_ECC_ERR", "MP_REQUEST_DECODE_ERR",
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"MP_UNCORRECTABLE_ECC_ERR", "MP_PARITY_ERR", "MP_COHERENCE_ERR",
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"CMBIU_REQUEST_DECODE_ERR", "CMBIU_PARITY_ERR", "CMBIU_AXI_RESP_ERR",
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"0x9", "RBI_BUS_ERR", "0xb", "0xc", "0xd", "0xe", "0xf", "0x10",
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"0x11", "0x12", "0x13", "0x14", "0x15", "0x16", "0x17", "0x18",
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"0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f"
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};
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phys_addr_t __mips_cm_phys_base(void)
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{
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u32 config3 = read_c0_config3();
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@ -130,3 +249,128 @@ int mips_cm_probe(void)
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return 0;
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}
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void mips_cm_error_report(void)
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{
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unsigned long revision = mips_cm_revision();
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/*
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* CM3 has a 64-bit Error cause register with 0:57 containing the error
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* info and 63:58 the error type. For old CMs, everything is contained
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* in a single 32-bit register (0:26 and 31:27 respectively). Even
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* though the cm_error is u64, we will simply ignore the upper word
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* for CM2.
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*/
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u64 cm_error = read_gcr_error_cause();
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int cm_error_cause_sft = CM_GCR_ERROR_CAUSE_ERRTYPE_SHF +
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((revision >= CM_REV_CM3) ? 31 : 0);
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unsigned long cm_addr = read_gcr_error_addr();
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unsigned long cm_other = read_gcr_error_mult();
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int ocause, cause;
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char buf[256];
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if (!mips_cm_present())
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return;
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cause = cm_error >> cm_error_cause_sft;
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if (!cause)
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/* All good */
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return;
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ocause = cm_other >> CM_GCR_ERROR_MULT_ERR2ND_SHF;
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if (revision < CM_REV_CM3) { /* CM2 */
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if (cause < 16) {
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unsigned long cca_bits = (cm_error >> 15) & 7;
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unsigned long tr_bits = (cm_error >> 12) & 7;
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unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
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unsigned long stag_bits = (cm_error >> 3) & 15;
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unsigned long sport_bits = (cm_error >> 0) & 7;
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snprintf(buf, sizeof(buf),
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"CCA=%lu TR=%s MCmd=%s STag=%lu "
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"SPort=%lu\n", cca_bits, cm2_tr[tr_bits],
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cm2_cmd[cmd_bits], stag_bits, sport_bits);
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} else {
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/* glob state & sresp together */
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unsigned long c3_bits = (cm_error >> 18) & 7;
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unsigned long c2_bits = (cm_error >> 15) & 7;
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unsigned long c1_bits = (cm_error >> 12) & 7;
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unsigned long c0_bits = (cm_error >> 9) & 7;
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unsigned long sc_bit = (cm_error >> 8) & 1;
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unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
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unsigned long sport_bits = (cm_error >> 0) & 7;
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snprintf(buf, sizeof(buf),
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"C3=%s C2=%s C1=%s C0=%s SC=%s "
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"MCmd=%s SPort=%lu\n",
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cm2_core[c3_bits], cm2_core[c2_bits],
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cm2_core[c1_bits], cm2_core[c0_bits],
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sc_bit ? "True" : "False",
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cm2_cmd[cmd_bits], sport_bits);
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}
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pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
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cm2_causes[cause], buf);
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pr_err("CM_ADDR =%08lx\n", cm_addr);
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pr_err("CM_OTHER=%08lx %s\n", cm_other, cm2_causes[ocause]);
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} else { /* CM3 */
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/* Used by cause == {1,2,3} */
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unsigned long core_id_bits = (cm_error >> 22) & 0xf;
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unsigned long vp_id_bits = (cm_error >> 18) & 0xf;
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unsigned long cmd_bits = (cm_error >> 14) & 0xf;
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unsigned long cmd_group_bits = (cm_error >> 11) & 0xf;
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unsigned long cm3_cca_bits = (cm_error >> 8) & 7;
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unsigned long mcp_bits = (cm_error >> 5) & 0xf;
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unsigned long cm3_tr_bits = (cm_error >> 1) & 0xf;
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unsigned long sched_bit = cm_error & 0x1;
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if (cause == 1 || cause == 3) { /* Tag ECC */
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unsigned long tag_ecc = (cm_error >> 57) & 0x1;
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unsigned long tag_way_bits = (cm_error >> 29) & 0xffff;
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unsigned long dword_bits = (cm_error >> 49) & 0xff;
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unsigned long data_way_bits = (cm_error >> 45) & 0xf;
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unsigned long data_sets_bits = (cm_error >> 29) & 0xfff;
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unsigned long bank_bit = (cm_error >> 28) & 0x1;
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snprintf(buf, sizeof(buf),
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"%s ECC Error: Way=%lu (DWORD=%lu, Sets=%lu)"
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"Bank=%lu CoreID=%lu VPID=%lu Command=%s"
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"Command Group=%s CCA=%lu MCP=%d"
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"Transaction type=%s Scheduler=%lu\n",
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tag_ecc ? "TAG" : "DATA",
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tag_ecc ? (unsigned long)ffs(tag_way_bits) - 1 :
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data_way_bits, bank_bit, dword_bits,
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data_sets_bits,
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core_id_bits, vp_id_bits,
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cm3_cmd[cmd_bits],
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cm3_cmd_group[cmd_group_bits],
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cm3_cca_bits, 1 << mcp_bits,
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cm3_tr[cm3_tr_bits], sched_bit);
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} else if (cause == 2) {
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unsigned long data_error_type = (cm_error >> 41) & 0xfff;
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unsigned long data_decode_cmd = (cm_error >> 37) & 0xf;
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unsigned long data_decode_group = (cm_error >> 34) & 0x7;
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unsigned long data_decode_destination_id = (cm_error >> 28) & 0x3f;
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snprintf(buf, sizeof(buf),
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"Decode Request Error: Type=%lu, Command=%lu"
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"Command Group=%lu Destination ID=%lu"
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"CoreID=%lu VPID=%lu Command=%s"
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"Command Group=%s CCA=%lu MCP=%d"
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"Transaction type=%s Scheduler=%lu\n",
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data_error_type, data_decode_cmd,
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data_decode_group, data_decode_destination_id,
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core_id_bits, vp_id_bits,
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cm3_cmd[cmd_bits],
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cm3_cmd_group[cmd_group_bits],
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cm3_cca_bits, 1 << mcp_bits,
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cm3_tr[cm3_tr_bits], sched_bit);
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}
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pr_err("CM_ERROR=%llx %s <%s>\n", cm_error,
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cm3_causes[cause], buf);
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pr_err("CM_ADDR =%lx\n", cm_addr);
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pr_err("CM_OTHER=%lx %s\n", cm_other, cm3_causes[ocause]);
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}
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/* reprime cause register */
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write_gcr_error_cause(0);
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}
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@ -382,122 +382,12 @@ void malta_be_init(void)
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/* Could change CM error mask register. */
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}
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static char *tr[8] = {
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"mem", "gcr", "gic", "mmio",
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"0x04", "0x05", "0x06", "0x07"
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};
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static char *mcmd[32] = {
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[0x00] = "0x00",
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[0x01] = "Legacy Write",
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[0x02] = "Legacy Read",
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[0x03] = "0x03",
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[0x04] = "0x04",
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[0x05] = "0x05",
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[0x06] = "0x06",
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[0x07] = "0x07",
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[0x08] = "Coherent Read Own",
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[0x09] = "Coherent Read Share",
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[0x0a] = "Coherent Read Discard",
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[0x0b] = "Coherent Ready Share Always",
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[0x0c] = "Coherent Upgrade",
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[0x0d] = "Coherent Writeback",
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[0x0e] = "0x0e",
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[0x0f] = "0x0f",
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[0x10] = "Coherent Copyback",
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[0x11] = "Coherent Copyback Invalidate",
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[0x12] = "Coherent Invalidate",
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[0x13] = "Coherent Write Invalidate",
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[0x14] = "Coherent Completion Sync",
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[0x15] = "0x15",
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[0x16] = "0x16",
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[0x17] = "0x17",
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[0x18] = "0x18",
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[0x19] = "0x19",
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[0x1a] = "0x1a",
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[0x1b] = "0x1b",
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[0x1c] = "0x1c",
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[0x1d] = "0x1d",
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[0x1e] = "0x1e",
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[0x1f] = "0x1f"
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};
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static char *core[8] = {
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"Invalid/OK", "Invalid/Data",
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"Shared/OK", "Shared/Data",
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"Modified/OK", "Modified/Data",
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"Exclusive/OK", "Exclusive/Data"
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};
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static char *causes[32] = {
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"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
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"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
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"0x08", "0x09", "0x0a", "0x0b",
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"0x0c", "0x0d", "0x0e", "0x0f",
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"0x10", "0x11", "0x12", "0x13",
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"0x14", "0x15", "0x16", "INTVN_WR_ERR",
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"INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
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"0x1c", "0x1d", "0x1e", "0x1f"
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};
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int malta_be_handler(struct pt_regs *regs, int is_fixup)
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{
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/* This duplicates the handling in do_be which seems wrong */
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int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
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if (mips_cm_present()) {
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unsigned long cm_error = read_gcr_error_cause();
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unsigned long cm_addr = read_gcr_error_addr();
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unsigned long cm_other = read_gcr_error_mult();
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unsigned long cause, ocause;
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char buf[256];
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cause = cm_error & CM_GCR_ERROR_CAUSE_ERRTYPE_MSK;
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if (cause != 0) {
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cause >>= CM_GCR_ERROR_CAUSE_ERRTYPE_SHF;
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if (cause < 16) {
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unsigned long cca_bits = (cm_error >> 15) & 7;
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unsigned long tr_bits = (cm_error >> 12) & 7;
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unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
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unsigned long stag_bits = (cm_error >> 3) & 15;
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unsigned long sport_bits = (cm_error >> 0) & 7;
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snprintf(buf, sizeof(buf),
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"CCA=%lu TR=%s MCmd=%s STag=%lu "
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"SPort=%lu\n",
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cca_bits, tr[tr_bits], mcmd[cmd_bits],
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stag_bits, sport_bits);
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} else {
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/* glob state & sresp together */
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unsigned long c3_bits = (cm_error >> 18) & 7;
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unsigned long c2_bits = (cm_error >> 15) & 7;
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unsigned long c1_bits = (cm_error >> 12) & 7;
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unsigned long c0_bits = (cm_error >> 9) & 7;
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unsigned long sc_bit = (cm_error >> 8) & 1;
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unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
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unsigned long sport_bits = (cm_error >> 0) & 7;
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snprintf(buf, sizeof(buf),
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"C3=%s C2=%s C1=%s C0=%s SC=%s "
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"MCmd=%s SPort=%lu\n",
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core[c3_bits], core[c2_bits],
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core[c1_bits], core[c0_bits],
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sc_bit ? "True" : "False",
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mcmd[cmd_bits], sport_bits);
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}
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ocause = (cm_other & CM_GCR_ERROR_MULT_ERR2ND_MSK) >>
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CM_GCR_ERROR_MULT_ERR2ND_SHF;
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||||
|
||||
pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error,
|
||||
causes[cause], buf);
|
||||
pr_err("CM_ADDR =%08lx\n", cm_addr);
|
||||
pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
|
||||
|
||||
/* reprime cause register */
|
||||
write_gcr_error_cause(0);
|
||||
}
|
||||
}
|
||||
mips_cm_error_report();
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
|
|
|||
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