iommu/amd: Detect and enable guest vAPIC support
This patch introduces a new IOMMU driver parameter, amd_iommu_guest_ir,
which can be used to specify different interrupt remapping mode for
passthrough devices to VM guest:
* legacy: Legacy interrupt remapping (w/ 32-bit IRTE)
* vapic : Guest vAPIC interrupt remapping (w/ GA mode 128-bit IRTE)
Note that in vapic mode, it can also supports legacy interrupt remapping
for non-passthrough devices with the 128-bit IRTE.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Suravee Suthikulpanit
Joerg Roedel
Родитель
29b4817d40
Коммит
3928aa3f57
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@ -460,6 +460,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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driver will print ACPI tables for AMD IOMMU during
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IOMMU initialization.
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amd_iommu_intr= [HW,X86-64]
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Specifies one of the following AMD IOMMU interrupt
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remapping modes:
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legacy - Use legacy interrupt remapping mode.
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vapic - Use virtual APIC mode, which allows IOMMU
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to inject interrupts directly into guest.
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This mode requires kvm-amd.avic=1.
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(Default when IOMMU HW support is present.)
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amijoy.map= [HW,JOY] Amiga joystick support
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Map of devices attached to JOY0DAT and JOY1DAT
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Format: <a>,<b>
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@ -145,6 +145,8 @@ struct ivmd_header {
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bool amd_iommu_dump;
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bool amd_iommu_irq_remap __read_mostly;
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int amd_iommu_guest_ir;
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static bool amd_iommu_detected;
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static bool __initdata amd_iommu_disabled;
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static int amd_iommu_target_ivhd_type;
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@ -1258,6 +1260,8 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
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iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
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else
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iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
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if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
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break;
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case 0x11:
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case 0x40:
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@ -1265,6 +1269,8 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
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iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
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else
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iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
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if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
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break;
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default:
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return -EINVAL;
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@ -1488,6 +1494,14 @@ static int iommu_init_pci(struct amd_iommu *iommu)
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if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
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return -ENOMEM;
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/* Note: We have already checked GASup from IVRS table.
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* Now, we need to make sure that GAMSup is set.
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*/
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if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
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!iommu_feature(iommu, FEATURE_GAM_VAPIC))
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
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if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
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amd_iommu_np_cache = true;
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@ -1545,16 +1559,24 @@ static void print_iommu_info(void)
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dev_name(&iommu->dev->dev), iommu->cap_ptr);
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if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
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pr_info("AMD-Vi: Extended features: ");
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pr_info("AMD-Vi: Extended features (%#llx):\n",
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iommu->features);
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for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
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if (iommu_feature(iommu, (1ULL << i)))
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pr_cont(" %s", feat_str[i]);
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}
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if (iommu->features & FEATURE_GAM_VAPIC)
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pr_cont(" GA_vAPIC");
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pr_cont("\n");
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}
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}
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if (irq_remapping_enabled)
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if (irq_remapping_enabled) {
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pr_info("AMD-Vi: Interrupt remapping enabled\n");
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if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
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pr_info("AMD-Vi: virtual APIC enabled\n");
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}
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}
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static int __init amd_iommu_init_pci(void)
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@ -1862,6 +1884,22 @@ static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
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iommu->stored_addr_lo | 1);
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}
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static void iommu_enable_ga(struct amd_iommu *iommu)
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{
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#ifdef CONFIG_IRQ_REMAP
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switch (amd_iommu_guest_ir) {
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case AMD_IOMMU_GUEST_IR_VAPIC:
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iommu_feature_enable(iommu, CONTROL_GAM_EN);
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/* Fall through */
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case AMD_IOMMU_GUEST_IR_LEGACY_GA:
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iommu_feature_enable(iommu, CONTROL_GA_EN);
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break;
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default:
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break;
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}
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#endif
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}
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/*
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* This function finally enables all IOMMUs found in the system after
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* they have been initialized
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@ -1877,6 +1915,7 @@ static void early_enable_iommus(void)
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iommu_enable_command_buffer(iommu);
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iommu_enable_event_buffer(iommu);
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iommu_set_exclusion_range(iommu);
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iommu_enable_ga(iommu);
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iommu_enable(iommu);
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iommu_flush_all_caches(iommu);
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}
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@ -2059,7 +2098,7 @@ static int __init early_amd_iommu_init(void)
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struct acpi_table_header *ivrs_base;
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acpi_size ivrs_size;
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acpi_status status;
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int i, ret = 0;
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int i, remap_cache_sz, ret = 0;
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if (!amd_iommu_detected)
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return -ENODEV;
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@ -2157,10 +2196,14 @@ static int __init early_amd_iommu_init(void)
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* remapping tables.
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*/
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ret = -ENOMEM;
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if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
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remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
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else
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remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
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amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
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MAX_IRQS_PER_TABLE * sizeof(u32),
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IRQ_TABLE_ALIGNMENT,
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0, NULL);
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remap_cache_sz,
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IRQ_TABLE_ALIGNMENT,
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0, NULL);
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if (!amd_iommu_irq_cache)
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goto out;
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@ -2413,6 +2456,21 @@ static int __init parse_amd_iommu_dump(char *str)
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return 1;
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}
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static int __init parse_amd_iommu_intr(char *str)
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{
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for (; *str; ++str) {
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if (strncmp(str, "legacy", 6) == 0) {
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
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break;
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}
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if (strncmp(str, "vapic", 5) == 0) {
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amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
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break;
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}
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}
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return 1;
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}
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static int __init parse_amd_iommu_options(char *str)
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{
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for (; *str; ++str) {
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@ -2521,6 +2579,7 @@ static int __init parse_ivrs_acpihid(char *str)
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__setup("amd_iommu_dump", parse_amd_iommu_dump);
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__setup("amd_iommu=", parse_amd_iommu_options);
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__setup("amd_iommu_intr=", parse_amd_iommu_intr);
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__setup("ivrs_ioapic", parse_ivrs_ioapic);
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__setup("ivrs_hpet", parse_ivrs_hpet);
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__setup("ivrs_acpihid", parse_ivrs_acpihid);
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@ -38,6 +38,7 @@ extern int amd_iommu_enable(void);
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extern void amd_iommu_disable(void);
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extern int amd_iommu_reenable(int);
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extern int amd_iommu_enable_faulting(void);
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extern int amd_iommu_guest_ir;
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/* IOMMUv2 specific functions */
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struct iommu_domain;
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@ -92,6 +92,7 @@
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#define FEATURE_GA (1ULL<<7)
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#define FEATURE_HE (1ULL<<8)
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#define FEATURE_PC (1ULL<<9)
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#define FEATURE_GAM_VAPIC (1ULL<<21)
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#define FEATURE_PASID_SHIFT 32
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#define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
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@ -146,6 +147,8 @@
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#define CONTROL_PPFINT_EN 0x0eULL
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#define CONTROL_PPR_EN 0x0fULL
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#define CONTROL_GT_EN 0x10ULL
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#define CONTROL_GA_EN 0x11ULL
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#define CONTROL_GAM_EN 0x19ULL
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#define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
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#define CTRL_INV_TO_NONE 0
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@ -329,6 +332,12 @@
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#define IOMMU_CAP_NPCACHE 26
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#define IOMMU_CAP_EFR 27
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/* IOMMU Feature Reporting Field (for IVHD type 10h */
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#define IOMMU_FEAT_GASUP_SHIFT 6
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/* IOMMU Extended Feature Register (EFR) */
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#define IOMMU_EFR_GASUP_SHIFT 7
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#define MAX_DOMAIN_ID 65536
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/* Protection domain flags */
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@ -681,4 +690,19 @@ static inline int get_hpet_devid(int id)
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return -EINVAL;
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}
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enum amd_iommu_intr_mode_type {
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AMD_IOMMU_GUEST_IR_LEGACY,
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/* This mode is not visible to users. It is used when
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* we cannot fully enable vAPIC and fallback to only support
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* legacy interrupt remapping via 128-bit IRTE.
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*/
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AMD_IOMMU_GUEST_IR_LEGACY_GA,
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AMD_IOMMU_GUEST_IR_VAPIC,
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};
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#define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \
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x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
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#define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC)
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#endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
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