[ARM] 4298/1: fix memory barriers for DMA coherent and SMP platforms
This patch: - Switches mb/rmb/wmb back to being full-blown DMBs on ARM SMP systems, since mb/rmb/wmb are required to order Normal memory accesses as well. - Enables the use of DMB and ISB on XSC3 (which is an ARMv5TE ISA core but conforms to the ARMv6 memory ordering model and supports the various ARMv6 barriers.) - Makes DMA coherent platforms (only ixp23xx at the moment) map mb/rmb/wmb to dmb(), as on DMA coherent platforms, DMA consistent mappings are done as Normal mappings, which are weakly ordered. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Acked-by: David Howells <dhowells@redhat.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -3,6 +3,7 @@
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#ifdef __KERNEL__
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#include <asm/memory.h>
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#define CPU_ARCH_UNKNOWN 0
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#define CPU_ARCH_ARMv3 1
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@ -154,7 +155,7 @@ extern unsigned int user_debug;
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#define vectors_high() (0)
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#endif
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#if __LINUX_ARM_ARCH__ >= 6
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#if defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ >= 6
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#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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@ -168,22 +169,23 @@ extern unsigned int user_debug;
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#define dmb() __asm__ __volatile__ ("" : : : "memory")
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#endif
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#define mb() barrier()
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#define rmb() barrier()
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#define wmb() barrier()
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#define read_barrier_depends() do { } while(0)
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#ifdef CONFIG_SMP
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#define smp_mb() dmb()
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#define smp_rmb() dmb()
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#define smp_wmb() dmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#ifndef CONFIG_SMP
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#define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
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#define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
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#define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() read_barrier_depends()
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#endif /* CONFIG_SMP */
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#define mb() dmb()
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#define rmb() dmb()
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#define wmb() dmb()
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#define smp_mb() dmb()
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#define smp_rmb() dmb()
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#define smp_wmb() dmb()
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#endif
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#define read_barrier_depends() do { } while(0)
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#define smp_read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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