cxl/core: Refactor CXL register lookup for bridge reuse
While CXL Memory Device endpoints locate the CXL MMIO registers in a PCI BAR, CXL root bridges have their MMIO base address described by platform firmware. Refactor the existing register lookup into a generic facility for endpoints and bridges to share. Reviewed-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/162096972534.1865304.3218686216153688039.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
Родитель
5f653f7590
Коммит
399d34ebc2
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@ -1,7 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include "cxl.h"
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/**
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* DOC: cxl core
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@ -10,6 +12,61 @@
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* point for cross-device interleave coordination through cxl ports.
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*/
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/**
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* cxl_setup_device_regs() - Detect CXL Device register blocks
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* @dev: Host device of the @base mapping
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* @base: Mapping of CXL 2.0 8.2.8 CXL Device Register Interface
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* @regs: Base pointers for device register blocks (see CXL_DEVICE_REGS())
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*/
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void cxl_setup_device_regs(struct device *dev, void __iomem *base,
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struct cxl_device_regs *regs)
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{
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int cap, cap_count;
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u64 cap_array;
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*regs = (struct cxl_device_regs) { 0 };
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cap_array = readq(base + CXLDEV_CAP_ARRAY_OFFSET);
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if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) !=
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CXLDEV_CAP_ARRAY_CAP_ID)
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return;
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cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array);
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for (cap = 1; cap <= cap_count; cap++) {
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void __iomem *register_block;
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u32 offset;
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u16 cap_id;
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cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK,
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readl(base + cap * 0x10));
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offset = readl(base + cap * 0x10 + 0x4);
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register_block = base + offset;
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switch (cap_id) {
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case CXLDEV_CAP_CAP_ID_DEVICE_STATUS:
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dev_dbg(dev, "found Status capability (0x%x)\n", offset);
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regs->status = register_block;
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break;
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case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX:
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dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset);
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regs->mbox = register_block;
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break;
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case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX:
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dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset);
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break;
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case CXLDEV_CAP_CAP_ID_MEMDEV:
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dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset);
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regs->memdev = register_block;
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break;
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default:
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dev_dbg(dev, "Unknown cap ID: %d (0x%x)\n", cap_id, offset);
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break;
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}
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}
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}
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EXPORT_SYMBOL_GPL(cxl_setup_device_regs);
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struct bus_type cxl_bus_type = {
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.name = "cxl",
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};
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@ -66,5 +66,8 @@ struct cxl_regs {
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};
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};
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void cxl_setup_device_regs(struct device *dev, void __iomem *base,
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struct cxl_device_regs *regs);
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extern struct bus_type cxl_bus_type;
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#endif /* __CXL_H__ */
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@ -884,53 +884,15 @@ static int cxl_mem_mbox_send_cmd(struct cxl_mem *cxlm, u16 opcode,
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static int cxl_mem_setup_regs(struct cxl_mem *cxlm)
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{
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struct device *dev = &cxlm->pdev->dev;
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int cap, cap_count;
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u64 cap_array;
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struct cxl_regs *regs = &cxlm->regs;
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cap_array = readq(cxlm->base + CXLDEV_CAP_ARRAY_OFFSET);
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if (FIELD_GET(CXLDEV_CAP_ARRAY_ID_MASK, cap_array) !=
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CXLDEV_CAP_ARRAY_CAP_ID)
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return -ENODEV;
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cxl_setup_device_regs(dev, cxlm->base, ®s->device_regs);
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cap_count = FIELD_GET(CXLDEV_CAP_ARRAY_COUNT_MASK, cap_array);
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for (cap = 1; cap <= cap_count; cap++) {
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void __iomem *register_block;
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u32 offset;
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u16 cap_id;
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cap_id = FIELD_GET(CXLDEV_CAP_HDR_CAP_ID_MASK,
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readl(cxlm->base + cap * 0x10));
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offset = readl(cxlm->base + cap * 0x10 + 0x4);
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register_block = cxlm->base + offset;
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switch (cap_id) {
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case CXLDEV_CAP_CAP_ID_DEVICE_STATUS:
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dev_dbg(dev, "found Status capability (0x%x)\n", offset);
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cxlm->regs.status = register_block;
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break;
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case CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX:
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dev_dbg(dev, "found Mailbox capability (0x%x)\n", offset);
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cxlm->regs.mbox = register_block;
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break;
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case CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX:
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dev_dbg(dev, "found Secondary Mailbox capability (0x%x)\n", offset);
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break;
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case CXLDEV_CAP_CAP_ID_MEMDEV:
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dev_dbg(dev, "found Memory Device capability (0x%x)\n", offset);
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cxlm->regs.memdev = register_block;
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break;
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default:
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dev_dbg(dev, "Unknown cap ID: %d (0x%x)\n", cap_id, offset);
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break;
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}
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}
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if (!cxlm->regs.status || !cxlm->regs.mbox || !cxlm->regs.memdev) {
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if (!regs->status || !regs->mbox || !regs->memdev) {
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dev_err(dev, "registers not found: %s%s%s\n",
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!cxlm->regs.status ? "status " : "",
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!cxlm->regs.mbox ? "mbox " : "",
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!cxlm->regs.memdev ? "memdev" : "");
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!regs->status ? "status " : "",
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!regs->mbox ? "mbox " : "",
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!regs->memdev ? "memdev" : "");
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return -ENXIO;
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}
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