[MIPS] Extend performance counter event field.
The latest draft version of the MIPS Architecture Specification extends the 6 bit event field by adding a directly adjacent 4-bit EventExt field for a total of 10 bits. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -19,7 +19,7 @@
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#define M_PERFCTL_SUPERVISOR (1UL << 2)
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#define M_PERFCTL_USER (1UL << 3)
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#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
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#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5)
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#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
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#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
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#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
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#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
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