[POWERPC] Made FSL Book-E PMC support more generic
Some of the more recent e300 cores have the same performance monitor implementation as the e500. e300 isn't book-e, so the name isn't really appropriate. In preparation for e300 support, rename a bunch of fsl_booke things to say fsl_emb (Freescale Embedded Performance Monitors). Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -1435,7 +1435,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.dcache_bsize = 32,
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.num_pmcs = 4,
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.oprofile_cpu_type = "ppc/e500",
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.oprofile_type = PPC_OPROFILE_BOOKE,
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.oprofile_type = PPC_OPROFILE_FSL_EMB,
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.machine_check = machine_check_e500,
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.platform = "ppc8540",
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},
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@ -1453,7 +1453,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.dcache_bsize = 32,
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.num_pmcs = 4,
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.oprofile_cpu_type = "ppc/e500",
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.oprofile_type = PPC_OPROFILE_BOOKE,
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.oprofile_type = PPC_OPROFILE_FSL_EMB,
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.machine_check = machine_check_e500,
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.platform = "ppc8548",
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},
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@ -26,7 +26,7 @@
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static void dummy_perf(struct pt_regs *regs)
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{
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#if defined(CONFIG_FSL_BOOKE) && !defined(CONFIG_E200)
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#if defined(CONFIG_FSL_EMB_PERFMON)
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mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE);
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#elif defined(CONFIG_PPC64) || defined(CONFIG_6xx)
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if (cur_cpu_spec->pmc_type == PPC_PMC_IBM)
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@ -15,5 +15,5 @@ oprofile-$(CONFIG_OPROFILE_CELL) += op_model_cell.o \
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cell/spu_profiler.o cell/vma_map.o \
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cell/spu_task_sync.o
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oprofile-$(CONFIG_PPC64) += op_model_rs64.o op_model_power4.o op_model_pa6t.o
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oprofile-$(CONFIG_FSL_BOOKE) += op_model_fsl_booke.o
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oprofile-$(CONFIG_FSL_EMB_PERFMON) += op_model_fsl_emb.o
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oprofile-$(CONFIG_6xx) += op_model_7450.o
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@ -202,9 +202,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
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model = &op_model_7450;
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break;
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#endif
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#ifdef CONFIG_FSL_BOOKE
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case PPC_OPROFILE_BOOKE:
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model = &op_model_fsl_booke;
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#if defined(CONFIG_FSL_EMB_PERFMON)
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case PPC_OPROFILE_FSL_EMB:
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model = &op_model_fsl_emb;
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break;
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#endif
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default:
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@ -1,7 +1,5 @@
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/*
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* arch/powerpc/oprofile/op_model_fsl_booke.c
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*
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* Freescale Book-E oprofile support, based on ppc64 oprofile support
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* Freescale Embedded oprofile support, based on ppc64 oprofile support
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* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* Copyright (c) 2004 Freescale Semiconductor, Inc
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@ -22,7 +20,7 @@
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/reg_booke.h>
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#include <asm/reg_fsl_emb.h>
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#include <asm/page.h>
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#include <asm/pmc.h>
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#include <asm/oprofile_impl.h>
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@ -244,7 +242,7 @@ static void dump_pmcs(void)
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mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3));
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}
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static int fsl_booke_cpu_setup(struct op_counter_config *ctr)
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static int fsl_emb_cpu_setup(struct op_counter_config *ctr)
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{
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int i;
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@ -262,7 +260,7 @@ static int fsl_booke_cpu_setup(struct op_counter_config *ctr)
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return 0;
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}
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static int fsl_booke_reg_setup(struct op_counter_config *ctr,
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static int fsl_emb_reg_setup(struct op_counter_config *ctr,
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struct op_system_config *sys,
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int num_ctrs)
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{
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@ -281,7 +279,7 @@ static int fsl_booke_reg_setup(struct op_counter_config *ctr,
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return 0;
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}
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static int fsl_booke_start(struct op_counter_config *ctr)
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static int fsl_emb_start(struct op_counter_config *ctr)
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{
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int i;
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@ -315,7 +313,7 @@ static int fsl_booke_start(struct op_counter_config *ctr)
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return 0;
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}
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static void fsl_booke_stop(void)
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static void fsl_emb_stop(void)
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{
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/* freeze counters */
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pmc_stop_ctrs();
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@ -329,7 +327,7 @@ static void fsl_booke_stop(void)
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}
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static void fsl_booke_handle_interrupt(struct pt_regs *regs,
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static void fsl_emb_handle_interrupt(struct pt_regs *regs,
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struct op_counter_config *ctr)
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{
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unsigned long pc;
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@ -362,10 +360,10 @@ static void fsl_booke_handle_interrupt(struct pt_regs *regs,
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pmc_start_ctrs(1);
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}
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struct op_powerpc_model op_model_fsl_booke = {
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.reg_setup = fsl_booke_reg_setup,
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.cpu_setup = fsl_booke_cpu_setup,
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.start = fsl_booke_start,
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.stop = fsl_booke_stop,
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.handle_interrupt = fsl_booke_handle_interrupt,
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struct op_powerpc_model op_model_fsl_emb = {
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.reg_setup = fsl_emb_reg_setup,
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.cpu_setup = fsl_emb_cpu_setup,
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.start = fsl_emb_start,
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.stop = fsl_emb_stop,
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.handle_interrupt = fsl_emb_handle_interrupt,
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};
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@ -94,6 +94,7 @@ config 8xx
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bool
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config E500
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select FSL_EMB_PERFMON
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bool
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config PPC_FPU
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@ -115,6 +116,9 @@ config FSL_BOOKE
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depends on E200 || E500
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default y
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config FSL_EMB_PERFMON
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bool
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config PTE_64BIT
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bool
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depends on 44x || E500
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@ -46,7 +46,7 @@ enum powerpc_oprofile_type {
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PPC_OPROFILE_RS64 = 1,
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PPC_OPROFILE_POWER4 = 2,
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PPC_OPROFILE_G4 = 3,
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PPC_OPROFILE_BOOKE = 4,
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PPC_OPROFILE_FSL_EMB = 4,
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PPC_OPROFILE_CELL = 5,
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PPC_OPROFILE_PA6T = 6,
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};
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@ -54,7 +54,7 @@ struct op_powerpc_model {
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int num_counters;
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};
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extern struct op_powerpc_model op_model_fsl_booke;
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extern struct op_powerpc_model op_model_fsl_emb;
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extern struct op_powerpc_model op_model_rs64;
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extern struct op_powerpc_model op_model_power4;
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extern struct op_powerpc_model op_model_7450;
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@ -18,6 +18,10 @@
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#include <asm/reg_booke.h>
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#endif /* CONFIG_BOOKE || CONFIG_40x */
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#ifdef CONFIG_FSL_EMB_PERFMON
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#include <asm/reg_fsl_emb.h>
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#endif
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#ifdef CONFIG_8xx
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#include <asm/reg_8xx.h>
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#endif /* CONFIG_8xx */
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@ -9,68 +9,6 @@
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#ifndef __ASM_POWERPC_REG_BOOKE_H__
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#define __ASM_POWERPC_REG_BOOKE_H__
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#ifndef __ASSEMBLY__
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/* Performance Monitor Registers */
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#define mfpmr(rn) ({unsigned int rval; \
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asm volatile("mfpmr %0," __stringify(rn) \
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: "=r" (rval)); rval;})
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#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
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#endif /* __ASSEMBLY__ */
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/* Freescale Book E Performance Monitor APU Registers */
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#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
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#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
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#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
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#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
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#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
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#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
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#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
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#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
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#define PMLCA_FC 0x80000000 /* Freeze Counter */
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#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
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#define PMLCA_FCU 0x20000000 /* Freeze in User */
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#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
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#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
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#define PMLCA_CE 0x04000000 /* Condition Enable */
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#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
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#define PMLCA_EVENT_SHIFT 16
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#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
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#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
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#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
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#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
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#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
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#define PMLCB_THRESHMUL_SHIFT 8
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#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
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#define PMLCB_THRESHOLD_SHIFT 0
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#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
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#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
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#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
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#define PMGC0_FCECE 0x20000000 /* Freeze countes on
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Enabled Condition or
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Event */
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#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
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#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
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#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
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#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
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#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
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#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
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#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
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#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
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#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
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#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
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#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
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#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
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#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
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/* Machine State Register (MSR) Fields */
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#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
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#define MSR_SPE (1<<25) /* Enable SPE */
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@ -0,0 +1,72 @@
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/*
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* Contains register definitions for the Freescale Embedded Performance
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* Monitor.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_POWERPC_REG_FSL_EMB_H__
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#define __ASM_POWERPC_REG_FSL_EMB_H__
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#ifndef __ASSEMBLY__
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/* Performance Monitor Registers */
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#define mfpmr(rn) ({unsigned int rval; \
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asm volatile("mfpmr %0," __stringify(rn) \
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: "=r" (rval)); rval;})
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#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
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#endif /* __ASSEMBLY__ */
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/* Freescale Book E Performance Monitor APU Registers */
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#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
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#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
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#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
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#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
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#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
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#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
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#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
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#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
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#define PMLCA_FC 0x80000000 /* Freeze Counter */
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#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
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#define PMLCA_FCU 0x20000000 /* Freeze in User */
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#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
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#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
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#define PMLCA_CE 0x04000000 /* Condition Enable */
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#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
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#define PMLCA_EVENT_SHIFT 16
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#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
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#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
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#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
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#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
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#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
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#define PMLCB_THRESHMUL_SHIFT 8
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#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
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#define PMLCB_THRESHOLD_SHIFT 0
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#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
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#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
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#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
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#define PMGC0_FCECE 0x20000000 /* Freeze countes on
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Enabled Condition or
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Event */
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#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
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#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
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#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
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#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
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#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
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#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
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#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
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#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
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#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
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#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
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#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
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#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
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#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
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#endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
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#endif /* __KERNEL__ */
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