Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung' and 'clk-allwinner' into clk-next
- Allow the COMMON_CLK config to be selectable
* clk-selectable:
clk: Move HAVE_CLK config out of architecture layer
MIPS: Loongson64: Drop asm/clock.h include
ARM: mmp: Remove legacy clk code
clk: Allow the common clk framework to be selectable
mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF
MIPS: Remove redundant CLKDEV_LOOKUP selects
h8300: Remove redundant CLKDEV_LOOKUP selects
arm64: tegra: Remove redundant CLKDEV_LOOKUP selects
ARM: Remove redundant CLKDEV_LOOKUP selects
ARM: Remove redundant COMMON_CLK selects
* clk-amlogic:
clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
clk: meson: meson8b: Fix the polarity of the RESET_N lines
clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
clk: meson: g12a: Prepare the GPU clock tree to change at runtime
clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
clk: meson: meson8b: make the hdmi_sys clock tree mutable
clk: meson8b: export the HDMI system clock
* clk-renesas:
dt-bindings: clock: renesas: mstp: Convert to json-schema
dt-bindings: clock: renesas: div6: Convert to json-schema
clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects
clk: renesas: cpg-mssr: Add R8A7742 support
dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
clk: renesas: Add r8a7742 CPG Core Clock Definitions
dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
MAINTAINERS: Add DT Bindings for Renesas Clock Generators
clk: renesas: r9a06g032: Fix some typo in comments
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support
* clk-samsung:
clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;
clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical
* clk-allwinner:
clk: sunxi: Fix incorrect usage of round_down()
This commit is contained in:
Stephen Boyd
Коммит
3a57530b7d
|
|
@ -0,0 +1,60 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas CPG DIV6 Clock
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description:
|
||||
The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
|
||||
Generator (CPG). Their clock input is divided by a configurable factor from 1
|
||||
to 64.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r8a73a4-div6-clock # R-Mobile APE6
|
||||
- renesas,r8a7740-div6-clock # R-Mobile A1
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||||
- renesas,sh73a0-div6-clock # SH-Mobile AG5
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||||
- const: renesas,cpg-div6-clock
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
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||||
oneOf:
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||||
- maxItems: 1
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||||
- maxItems: 4
|
||||
- maxItems: 8
|
||||
description:
|
||||
For clocks with multiple parents, invalid settings must be specified as
|
||||
"<0>".
|
||||
|
||||
'#clock-cells':
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||||
const: 0
|
||||
|
||||
clock-output-names: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a73a4-clock.h>
|
||||
sdhi2_clk: sdhi2_clk@e615007c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0xe615007c 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
|
||||
<&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
* Renesas CPG DIV6 Clock
|
||||
|
||||
The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
|
||||
Generator (CPG). Their clock input is divided by a configurable factor from 1
|
||||
to 64.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
|
||||
- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
|
||||
- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
|
||||
- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
|
||||
- "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
|
||||
- "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
|
||||
- "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
|
||||
and "renesas,cpg-div6-clock" as a fallback.
|
||||
- reg: Base address and length of the memory resource used by the DIV6 clock
|
||||
- clocks: Reference to the parent clock(s); either one, four, or eight
|
||||
clocks must be specified. For clocks with multiple parents, invalid
|
||||
settings must be specified as "<0>".
|
||||
- #clock-cells: Must be 0
|
||||
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- clock-output-names: The name of the clock as a free-form string
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
sdhi2_clk: sdhi2_clk@e615007c {
|
||||
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615007c 0 4>;
|
||||
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
|
||||
<0>, <&extal2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sdhi2ck";
|
||||
};
|
||||
|
|
@ -25,6 +25,7 @@ properties:
|
|||
compatible:
|
||||
enum:
|
||||
- renesas,r7s9210-cpg-mssr # RZ/A2
|
||||
- renesas,r8a7742-cpg-mssr # RZ/G1H
|
||||
- renesas,r8a7743-cpg-mssr # RZ/G1M
|
||||
- renesas,r8a7744-cpg-mssr # RZ/G1N
|
||||
- renesas,r8a7745-cpg-mssr # RZ/G1E
|
||||
|
|
|
|||
|
|
@ -1,60 +0,0 @@
|
|||
* Renesas CPG Module Stop (MSTP) Clocks
|
||||
|
||||
The CPG can gate SoC device clocks. The gates are organized in groups of up to
|
||||
32 gates.
|
||||
|
||||
This device tree binding describes a single 32 gate clocks group per node.
|
||||
Clocks are referenced by user nodes by the MSTP node phandle and the clock
|
||||
index in the group, from 0 to 31.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
|
||||
- "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
|
||||
- "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
|
||||
- "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
|
||||
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
|
||||
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
|
||||
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
|
||||
- "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks
|
||||
- "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
|
||||
- "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
|
||||
- "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
|
||||
and "renesas,cpg-mstp-clocks" as a fallback.
|
||||
- reg: Base address and length of the I/O mapped registers used by the MSTP
|
||||
clocks. The first register is the clock control register and is mandatory.
|
||||
The second register is the clock status register and is optional when not
|
||||
implemented in hardware.
|
||||
- clocks: Reference to the parent clocks, one per output clock. The parents
|
||||
must appear in the same order as the output clocks.
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The name of the clocks as free-form strings
|
||||
- clock-indices: Indices of the gate clocks into the group (0 to 31)
|
||||
|
||||
The clocks, clock-output-names and clock-indices properties contain one entry
|
||||
per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
|
||||
clocks must not be declared.
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
#include <dt-bindings/clock/r8a7790-clock.h>
|
||||
|
||||
mstp3_clks: mstp3_clks@e615013c {
|
||||
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
||||
clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
|
||||
<&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
|
||||
<&mmc0_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names =
|
||||
"tpu0", "mmcif1", "sdhi3", "sdhi2",
|
||||
"sdhi1", "sdhi0", "mmcif0";
|
||||
clock-indices = <
|
||||
R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
|
||||
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
|
||||
R8A7790_CLK_MMCIF0
|
||||
>;
|
||||
};
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description:
|
||||
The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
|
||||
organized in groups of up to 32 gates.
|
||||
|
||||
This device tree binding describes a single 32 gate clocks group per node.
|
||||
Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
|
||||
and the clock index in the group, from 0 to 31.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r7s72100-mstp-clocks # RZ/A1
|
||||
- renesas,r8a73a4-mstp-clocks # R-Mobile APE6
|
||||
- renesas,r8a7740-mstp-clocks # R-Mobile A1
|
||||
- renesas,r8a7778-mstp-clocks # R-Car M1
|
||||
- renesas,r8a7779-mstp-clocks # R-Car H1
|
||||
- renesas,sh73a0-mstp-clocks # SH-Mobile AG5
|
||||
- const: renesas,cpg-mstp-clocks
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Module Stop Control Register (MSTPCR)
|
||||
- description: Module Stop Status Register (MSTPSR)
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clock-indices:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
clock-output-names:
|
||||
minItems: 1
|
||||
maxItems: 32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- clock-indices
|
||||
- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a73a4-clock.h>
|
||||
mstp2_clks: mstp2_clks@e6150138 {
|
||||
compatible = "renesas,r8a73a4-mstp-clocks",
|
||||
"renesas,cpg-mstp-clocks";
|
||||
reg = <0xe6150138 4>, <0xe6150040 4>;
|
||||
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
||||
<&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
|
||||
R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
|
||||
R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
|
||||
R8A73A4_CLK_DMAC
|
||||
>;
|
||||
clock-output-names =
|
||||
"scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",
|
||||
"dmac";
|
||||
};
|
||||
|
|
@ -27,7 +27,9 @@ Required properties:
|
|||
- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
|
||||
an R8A7795 SoC.
|
||||
"renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
|
||||
an R8A7796 SoC.
|
||||
an R8A77960 SoC.
|
||||
"renesas,r8a77961-rcar-usb2-clock-sel" if the device if a part of
|
||||
an R8A77961 SoC.
|
||||
"renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
|
||||
compatible device.
|
||||
|
||||
|
|
|
|||
|
|
@ -14334,6 +14334,7 @@ M: Geert Uytterhoeven <geert+renesas@glider.be>
|
|||
L: linux-renesas-soc@vger.kernel.org
|
||||
S: Supported
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git clk-renesas
|
||||
F: Documentation/devicetree/bindings/clock/renesas,*
|
||||
F: drivers/clk/renesas/
|
||||
|
||||
RENESAS EMEV2 I2C DRIVER
|
||||
|
|
|
|||
|
|
@ -3702,7 +3702,9 @@ static struct clk_regmap g12a_hdmi = {
|
|||
|
||||
/*
|
||||
* The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
|
||||
* muxed by a glitch-free switch.
|
||||
* muxed by a glitch-free switch. The CCF can manage this glitch-free
|
||||
* mux because it does top-to-bottom updates the each clock tree and
|
||||
* switches to the "inactive" one when CLK_SET_RATE_GATE is set.
|
||||
*/
|
||||
static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
|
||||
{ .fw_name = "xtal", },
|
||||
|
|
@ -3726,7 +3728,13 @@ static struct clk_regmap g12a_mali_0_sel = {
|
|||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_data = g12a_mali_0_1_parent_data,
|
||||
.num_parents = 8,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
/*
|
||||
* Don't request the parent to change the rate because
|
||||
* all GPU frequencies can be derived from the fclk_*
|
||||
* clocks and one special GP0_PLL setting. This is
|
||||
* important because we need the MPLL clocks for audio.
|
||||
*/
|
||||
.flags = 0,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -3743,7 +3751,7 @@ static struct clk_regmap g12a_mali_0_div = {
|
|||
&g12a_mali_0_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -3759,7 +3767,7 @@ static struct clk_regmap g12a_mali_0 = {
|
|||
&g12a_mali_0_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -3774,7 +3782,13 @@ static struct clk_regmap g12a_mali_1_sel = {
|
|||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_data = g12a_mali_0_1_parent_data,
|
||||
.num_parents = 8,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
/*
|
||||
* Don't request the parent to change the rate because
|
||||
* all GPU frequencies can be derived from the fclk_*
|
||||
* clocks and one special GP0_PLL setting. This is
|
||||
* important because we need the MPLL clocks for audio.
|
||||
*/
|
||||
.flags = 0,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -3791,7 +3805,7 @@ static struct clk_regmap g12a_mali_1_div = {
|
|||
&g12a_mali_1_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -3807,7 +3821,7 @@ static struct clk_regmap g12a_mali_1 = {
|
|||
&g12a_mali_1_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -3827,7 +3841,7 @@ static struct clk_regmap g12a_mali = {
|
|||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = g12a_mali_parent_hws,
|
||||
.num_parents = 2,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -957,7 +957,9 @@ static struct clk_regmap gxbb_sar_adc_clk = {
|
|||
|
||||
/*
|
||||
* The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
|
||||
* muxed by a glitch-free switch.
|
||||
* muxed by a glitch-free switch. The CCF can manage this glitch-free
|
||||
* mux because it does top-to-bottom updates the each clock tree and
|
||||
* switches to the "inactive" one when CLK_SET_RATE_GATE is set.
|
||||
*/
|
||||
|
||||
static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
|
||||
|
|
@ -980,14 +982,15 @@ static struct clk_regmap gxbb_mali_0_sel = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali_0_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
/*
|
||||
* bits 10:9 selects from 8 possible parents:
|
||||
* xtal, gp0_pll, mpll2, mpll1, fclk_div7,
|
||||
* fclk_div4, fclk_div3, fclk_div5
|
||||
*/
|
||||
.parent_data = gxbb_mali_0_1_parent_data,
|
||||
.num_parents = 8,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
/*
|
||||
* Don't request the parent to change the rate because
|
||||
* all GPU frequencies can be derived from the fclk_*
|
||||
* clocks and one special GP0_PLL setting. This is
|
||||
* important because we need the MPLL clocks for audio.
|
||||
*/
|
||||
.flags = 0,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1004,7 +1007,7 @@ static struct clk_regmap gxbb_mali_0_div = {
|
|||
&gxbb_mali_0_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1020,7 +1023,7 @@ static struct clk_regmap gxbb_mali_0 = {
|
|||
&gxbb_mali_0_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1033,14 +1036,15 @@ static struct clk_regmap gxbb_mali_1_sel = {
|
|||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mali_1_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
/*
|
||||
* bits 10:9 selects from 8 possible parents:
|
||||
* xtal, gp0_pll, mpll2, mpll1, fclk_div7,
|
||||
* fclk_div4, fclk_div3, fclk_div5
|
||||
*/
|
||||
.parent_data = gxbb_mali_0_1_parent_data,
|
||||
.num_parents = 8,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
/*
|
||||
* Don't request the parent to change the rate because
|
||||
* all GPU frequencies can be derived from the fclk_*
|
||||
* clocks and one special GP0_PLL setting. This is
|
||||
* important because we need the MPLL clocks for audio.
|
||||
*/
|
||||
.flags = 0,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1057,7 +1061,7 @@ static struct clk_regmap gxbb_mali_1_div = {
|
|||
&gxbb_mali_1_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1073,7 +1077,7 @@ static struct clk_regmap gxbb_mali_1 = {
|
|||
&gxbb_mali_1_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1093,7 +1097,7 @@ static struct clk_regmap gxbb_mali = {
|
|||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_hws = gxbb_mali_parent_hws,
|
||||
.num_parents = 2,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1077,7 +1077,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
|
|||
* Meson8m2: vid2_pll
|
||||
*/
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_hdmi_pll_dco.hw
|
||||
&meson8b_hdmi_pll_lvds_out.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
|
|
@ -1213,7 +1213,7 @@ static struct clk_regmap meson8b_vclk_in_en = {
|
|||
|
||||
static struct clk_regmap meson8b_vclk_div1_gate = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_DIV,
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 0,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
|
|
@ -1243,7 +1243,7 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = {
|
|||
|
||||
static struct clk_regmap meson8b_vclk_div2_div_gate = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_DIV,
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 1,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
|
|
@ -1273,7 +1273,7 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = {
|
|||
|
||||
static struct clk_regmap meson8b_vclk_div4_div_gate = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_DIV,
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 2,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
|
|
@ -1303,7 +1303,7 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = {
|
|||
|
||||
static struct clk_regmap meson8b_vclk_div6_div_gate = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_DIV,
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 3,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
|
|
@ -1333,7 +1333,7 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = {
|
|||
|
||||
static struct clk_regmap meson8b_vclk_div12_div_gate = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_VID_CLK_DIV,
|
||||
.offset = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 4,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
|
|
@ -1725,7 +1725,7 @@ static struct clk_regmap meson8b_hdmi_sys_sel = {
|
|||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_sys_sel",
|
||||
.ops = &clk_regmap_mux_ro_ops,
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
/* FIXME: all other parents are unknown */
|
||||
.parent_data = &(const struct clk_parent_data) {
|
||||
.fw_name = "xtal",
|
||||
|
|
@ -1745,7 +1745,7 @@ static struct clk_regmap meson8b_hdmi_sys_div = {
|
|||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "hdmi_sys_div",
|
||||
.ops = &clk_regmap_divider_ro_ops,
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_hdmi_sys_sel.hw
|
||||
},
|
||||
|
|
@ -1761,7 +1761,7 @@ static struct clk_regmap meson8b_hdmi_sys = {
|
|||
},
|
||||
.hw.init = &(struct clk_init_data) {
|
||||
.name = "hdmi_sys",
|
||||
.ops = &clk_regmap_gate_ro_ops,
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&meson8b_hdmi_sys_div.hw
|
||||
},
|
||||
|
|
@ -1918,6 +1918,13 @@ static struct clk_regmap meson8b_mali = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct reg_sequence meson8m2_gp_pll_init_regs[] = {
|
||||
{ .reg = HHI_GP_PLL_CNTL2, .def = 0x59c88000 },
|
||||
{ .reg = HHI_GP_PLL_CNTL3, .def = 0xca463823 },
|
||||
{ .reg = HHI_GP_PLL_CNTL4, .def = 0x0286a027 },
|
||||
{ .reg = HHI_GP_PLL_CNTL5, .def = 0x00003000 },
|
||||
};
|
||||
|
||||
static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
|
||||
PLL_PARAMS(182, 3),
|
||||
{ /* sentinel */ },
|
||||
|
|
@ -1951,6 +1958,8 @@ static struct clk_regmap meson8m2_gp_pll_dco = {
|
|||
.width = 1,
|
||||
},
|
||||
.table = meson8m2_gp_pll_params_table,
|
||||
.init_regs = meson8m2_gp_pll_init_regs,
|
||||
.init_count = ARRAY_SIZE(meson8m2_gp_pll_init_regs),
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gp_pll_dco",
|
||||
|
|
@ -2063,7 +2072,7 @@ static struct clk_regmap meson8b_vpu_0 = {
|
|||
&meson8b_vpu_0_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -2134,10 +2143,18 @@ static struct clk_regmap meson8b_vpu_1 = {
|
|||
&meson8b_vpu_1_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* The VPU clock has two two identical clock trees (vpu_0 and vpu_1)
|
||||
* muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
|
||||
* actually manage this glitch-free mux because it does top-to-bottom
|
||||
* updates the each clock tree and switches to the "inactive" one when
|
||||
* CLK_SET_RATE_GATE is set.
|
||||
* Meson8 only has vpu_0 and no glitch-free mux.
|
||||
*/
|
||||
static struct clk_regmap meson8b_vpu = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_VPU_CLK_CNTL,
|
||||
|
|
@ -2152,7 +2169,7 @@ static struct clk_regmap meson8b_vpu = {
|
|||
&meson8b_vpu_1.hw,
|
||||
},
|
||||
.num_parents = 2,
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -3506,54 +3523,87 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
|
|||
static const struct meson8b_clk_reset_line {
|
||||
u32 reg;
|
||||
u8 bit_idx;
|
||||
bool active_low;
|
||||
} meson8b_clk_reset_bits[] = {
|
||||
[CLKC_RESET_L2_CACHE_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.bit_idx = 30,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.bit_idx = 29,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_SCU_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.bit_idx = 28,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_CPU3_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.bit_idx = 27,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_CPU2_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.bit_idx = 26,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_CPU1_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.bit_idx = 25,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_CPU0_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.bit_idx = 24,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_A5_GLOBAL_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.bit_idx = 18,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_A5_AXI_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.bit_idx = 17,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_A5_ABP_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.bit_idx = 16,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
|
||||
.reg = HHI_SYS_CPU_CLK_CNTL1,
|
||||
.bit_idx = 30,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
|
||||
.reg = HHI_VID_CLK_CNTL, .bit_idx = 15
|
||||
.reg = HHI_VID_CLK_CNTL,
|
||||
.bit_idx = 15,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
|
||||
.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
|
||||
.reg = HHI_VID_DIVIDER_CNTL,
|
||||
.bit_idx = 7,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
|
||||
.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
|
||||
.reg = HHI_VID_DIVIDER_CNTL,
|
||||
.bit_idx = 3,
|
||||
.active_low = false,
|
||||
},
|
||||
[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
|
||||
.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
|
||||
.reg = HHI_VID_DIVIDER_CNTL,
|
||||
.bit_idx = 1,
|
||||
.active_low = true,
|
||||
},
|
||||
[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
|
||||
.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
|
||||
.reg = HHI_VID_DIVIDER_CNTL,
|
||||
.bit_idx = 0,
|
||||
.active_low = true,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -3562,22 +3612,22 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
|
|||
{
|
||||
struct meson8b_clk_reset *meson8b_clk_reset =
|
||||
container_of(rcdev, struct meson8b_clk_reset, reset);
|
||||
unsigned long flags;
|
||||
const struct meson8b_clk_reset_line *reset;
|
||||
unsigned int value = 0;
|
||||
unsigned long flags;
|
||||
|
||||
if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
|
||||
return -EINVAL;
|
||||
|
||||
reset = &meson8b_clk_reset_bits[id];
|
||||
|
||||
if (assert != reset->active_low)
|
||||
value = BIT(reset->bit_idx);
|
||||
|
||||
spin_lock_irqsave(&meson_clk_lock, flags);
|
||||
|
||||
if (assert)
|
||||
regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
|
||||
BIT(reset->bit_idx), BIT(reset->bit_idx));
|
||||
else
|
||||
regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
|
||||
BIT(reset->bit_idx), 0);
|
||||
regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
|
||||
BIT(reset->bit_idx), value);
|
||||
|
||||
spin_unlock_irqrestore(&meson_clk_lock, flags);
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,10 @@
|
|||
* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
|
||||
*/
|
||||
#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
|
||||
#define HHI_GP_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
|
||||
#define HHI_GP_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
|
||||
#define HHI_GP_PLL_CNTL4 0x4C /* 0x13 offset in data sheet */
|
||||
#define HHI_GP_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
|
||||
#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
|
||||
#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
|
||||
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
|
||||
|
|
@ -146,7 +150,6 @@
|
|||
#define CLKID_CTS_VDAC0 171
|
||||
#define CLKID_HDMI_SYS_SEL 172
|
||||
#define CLKID_HDMI_SYS_DIV 173
|
||||
#define CLKID_HDMI_SYS 174
|
||||
#define CLKID_MALI_0_SEL 175
|
||||
#define CLKID_MALI_0_DIV 176
|
||||
#define CLKID_MALI_0 177
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ config CLK_RENESAS
|
|||
select CLK_R7S9210 if ARCH_R7S9210
|
||||
select CLK_R8A73A4 if ARCH_R8A73A4
|
||||
select CLK_R8A7740 if ARCH_R8A7740
|
||||
select CLK_R8A7742 if ARCH_R8A7742
|
||||
select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
|
||||
select CLK_R8A7745 if ARCH_R8A7745
|
||||
select CLK_R8A77470 if ARCH_R8A77470
|
||||
|
|
@ -55,6 +56,10 @@ config CLK_R8A7740
|
|||
select CLK_RENESAS_CPG_MSTP
|
||||
select CLK_RENESAS_DIV6
|
||||
|
||||
config CLK_R8A7742
|
||||
bool "RZ/G1H clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN2_CPG
|
||||
|
||||
config CLK_R8A7743
|
||||
bool "RZ/G1M clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN2_CPG
|
||||
|
|
@ -90,12 +95,10 @@ config CLK_R8A7779
|
|||
config CLK_R8A7790
|
||||
bool "R-Car H2 clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN2_CPG
|
||||
select CLK_RENESAS_DIV6
|
||||
|
||||
config CLK_R8A7791
|
||||
bool "R-Car M2-W/N clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN2_CPG
|
||||
select CLK_RENESAS_DIV6
|
||||
|
||||
config CLK_R8A7792
|
||||
bool "R-Car V2H clock support" if COMPILE_TEST
|
||||
|
|
@ -104,7 +107,6 @@ config CLK_R8A7792
|
|||
config CLK_R8A7794
|
||||
bool "R-Car E2 clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN2_CPG
|
||||
select CLK_RENESAS_DIV6
|
||||
|
||||
config CLK_R8A7795
|
||||
bool "R-Car H3 clock support" if COMPILE_TEST
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ obj-$(CONFIG_CLK_RZA1) += clk-rz.o
|
|||
obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
|
||||
obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
|
||||
obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,275 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a7742 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen2-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7742_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_USB_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL1_DIV2,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7742_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7742_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
|
||||
DEF_BASE("lb", R8A7742_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7742_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7742_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
DEF_BASE("sd1", R8A7742_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7742_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
DEF_BASE("rcan", R8A7742_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
|
||||
|
||||
DEF_FIXED("z2", R8A7742_CLK_Z2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("zg", R8A7742_CLK_ZG, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zx", R8A7742_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("zs", R8A7742_CLK_ZS, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("hp", R8A7742_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("b", R8A7742_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("p", R8A7742_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7742_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7742_CLK_M2, CLK_PLL1, 8, 1),
|
||||
DEF_FIXED("zb3", R8A7742_CLK_ZB3, CLK_PLL3, 4, 1),
|
||||
DEF_FIXED("zb3d2", R8A7742_CLK_ZB3D2, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("ddr", R8A7742_CLK_DDR, CLK_PLL3, 8, 1),
|
||||
DEF_FIXED("mp", R8A7742_CLK_MP, CLK_PLL1_DIV2, 15, 1),
|
||||
DEF_FIXED("cp", R8A7742_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("r", R8A7742_CLK_R, CLK_PLL1, 49152, 1),
|
||||
DEF_FIXED("osc", R8A7742_CLK_OSC, CLK_PLL1, 12288, 1),
|
||||
|
||||
DEF_DIV6P1("sd2", R8A7742_CLK_SD2, CLK_PLL1_DIV2, 0x078),
|
||||
DEF_DIV6P1("sd3", R8A7742_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
|
||||
DEF_DIV6P1("mmc0", R8A7742_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
|
||||
DEF_DIV6P1("mmc1", R8A7742_CLK_MMC1, CLK_PLL1_DIV2, 0x244),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = {
|
||||
DEF_MOD("msiof0", 0, R8A7742_CLK_MP),
|
||||
DEF_MOD("vcp1", 100, R8A7742_CLK_ZS),
|
||||
DEF_MOD("vcp0", 101, R8A7742_CLK_ZS),
|
||||
DEF_MOD("vpc1", 102, R8A7742_CLK_ZS),
|
||||
DEF_MOD("vpc0", 103, R8A7742_CLK_ZS),
|
||||
DEF_MOD("tmu1", 111, R8A7742_CLK_P),
|
||||
DEF_MOD("3dg", 112, R8A7742_CLK_ZG),
|
||||
DEF_MOD("2d-dmac", 115, R8A7742_CLK_ZS),
|
||||
DEF_MOD("fdp1-2", 117, R8A7742_CLK_ZS),
|
||||
DEF_MOD("fdp1-1", 118, R8A7742_CLK_ZS),
|
||||
DEF_MOD("fdp1-0", 119, R8A7742_CLK_ZS),
|
||||
DEF_MOD("tmu3", 121, R8A7742_CLK_P),
|
||||
DEF_MOD("tmu2", 122, R8A7742_CLK_P),
|
||||
DEF_MOD("cmt0", 124, R8A7742_CLK_R),
|
||||
DEF_MOD("tmu0", 125, R8A7742_CLK_CP),
|
||||
DEF_MOD("vsp1du1", 127, R8A7742_CLK_ZS),
|
||||
DEF_MOD("vsp1du0", 128, R8A7742_CLK_ZS),
|
||||
DEF_MOD("vsp1-sy", 131, R8A7742_CLK_ZS),
|
||||
DEF_MOD("scifa2", 202, R8A7742_CLK_MP),
|
||||
DEF_MOD("scifa1", 203, R8A7742_CLK_MP),
|
||||
DEF_MOD("scifa0", 204, R8A7742_CLK_MP),
|
||||
DEF_MOD("msiof2", 205, R8A7742_CLK_MP),
|
||||
DEF_MOD("scifb0", 206, R8A7742_CLK_MP),
|
||||
DEF_MOD("scifb1", 207, R8A7742_CLK_MP),
|
||||
DEF_MOD("msiof1", 208, R8A7742_CLK_MP),
|
||||
DEF_MOD("msiof3", 215, R8A7742_CLK_MP),
|
||||
DEF_MOD("scifb2", 216, R8A7742_CLK_MP),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7742_CLK_ZS),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7742_CLK_ZS),
|
||||
DEF_MOD("iic2", 300, R8A7742_CLK_HP),
|
||||
DEF_MOD("tpu0", 304, R8A7742_CLK_CP),
|
||||
DEF_MOD("mmcif1", 305, R8A7742_CLK_MMC1),
|
||||
DEF_MOD("scif2", 310, R8A7742_CLK_P),
|
||||
DEF_MOD("sdhi3", 311, R8A7742_CLK_SD3),
|
||||
DEF_MOD("sdhi2", 312, R8A7742_CLK_SD2),
|
||||
DEF_MOD("sdhi1", 313, R8A7742_CLK_SD1),
|
||||
DEF_MOD("sdhi0", 314, R8A7742_CLK_SD0),
|
||||
DEF_MOD("mmcif0", 315, R8A7742_CLK_MMC0),
|
||||
DEF_MOD("iic0", 318, R8A7742_CLK_HP),
|
||||
DEF_MOD("pciec", 319, R8A7742_CLK_MP),
|
||||
DEF_MOD("iic1", 323, R8A7742_CLK_HP),
|
||||
DEF_MOD("usb3.0", 328, R8A7742_CLK_MP),
|
||||
DEF_MOD("cmt1", 329, R8A7742_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7742_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7742_CLK_HP),
|
||||
DEF_MOD("rwdt", 402, R8A7742_CLK_R),
|
||||
DEF_MOD("irqc", 407, R8A7742_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7742_CLK_ZS),
|
||||
DEF_MOD("audio-dmac1", 501, R8A7742_CLK_HP),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7742_CLK_HP),
|
||||
DEF_MOD("thermal", 522, CLK_EXTAL),
|
||||
DEF_MOD("pwm", 523, R8A7742_CLK_P),
|
||||
DEF_MOD("usb-ehci", 703, R8A7742_CLK_MP),
|
||||
DEF_MOD("usbhs", 704, R8A7742_CLK_HP),
|
||||
DEF_MOD("hscif1", 716, R8A7742_CLK_ZS),
|
||||
DEF_MOD("hscif0", 717, R8A7742_CLK_ZS),
|
||||
DEF_MOD("scif1", 720, R8A7742_CLK_P),
|
||||
DEF_MOD("scif0", 721, R8A7742_CLK_P),
|
||||
DEF_MOD("du2", 722, R8A7742_CLK_ZX),
|
||||
DEF_MOD("du1", 723, R8A7742_CLK_ZX),
|
||||
DEF_MOD("du0", 724, R8A7742_CLK_ZX),
|
||||
DEF_MOD("lvds1", 725, R8A7742_CLK_ZX),
|
||||
DEF_MOD("lvds0", 726, R8A7742_CLK_ZX),
|
||||
DEF_MOD("r-gp2d", 807, R8A7742_CLK_ZX),
|
||||
DEF_MOD("vin3", 808, R8A7742_CLK_ZG),
|
||||
DEF_MOD("vin2", 809, R8A7742_CLK_ZG),
|
||||
DEF_MOD("vin1", 810, R8A7742_CLK_ZG),
|
||||
DEF_MOD("vin0", 811, R8A7742_CLK_ZG),
|
||||
DEF_MOD("etheravb", 812, R8A7742_CLK_HP),
|
||||
DEF_MOD("ether", 813, R8A7742_CLK_P),
|
||||
DEF_MOD("sata1", 814, R8A7742_CLK_ZS),
|
||||
DEF_MOD("sata0", 815, R8A7742_CLK_ZS),
|
||||
DEF_MOD("imr-x2-1", 820, R8A7742_CLK_ZG),
|
||||
DEF_MOD("imr-x2-0", 821, R8A7742_CLK_HP),
|
||||
DEF_MOD("imr-lsx2-1", 822, R8A7742_CLK_P),
|
||||
DEF_MOD("imr-lsx2-0", 823, R8A7742_CLK_ZS),
|
||||
DEF_MOD("gpio5", 907, R8A7742_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7742_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7742_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7742_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7742_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7742_CLK_CP),
|
||||
DEF_MOD("can1", 915, R8A7742_CLK_P),
|
||||
DEF_MOD("can0", 916, R8A7742_CLK_P),
|
||||
DEF_MOD("qspi_mod", 917, R8A7742_CLK_QSPI),
|
||||
DEF_MOD("iicdvfs", 926, R8A7742_CLK_CP),
|
||||
DEF_MOD("i2c3", 928, R8A7742_CLK_HP),
|
||||
DEF_MOD("i2c2", 929, R8A7742_CLK_HP),
|
||||
DEF_MOD("i2c1", 930, R8A7742_CLK_HP),
|
||||
DEF_MOD("i2c0", 931, R8A7742_CLK_HP),
|
||||
DEF_MOD("ssi-all", 1005, R8A7742_CLK_P),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7742_CLK_P),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a7742_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(402), /* RWDT */
|
||||
MOD_CLK_ID(408), /* INTC-SYS (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *1
|
||||
*---------------------------------------------------
|
||||
* 0 0 0 15 x172/2 x208/2 x106
|
||||
* 0 0 1 15 x172/2 x208/2 x88
|
||||
* 0 1 0 20 x130/2 x156/2 x80
|
||||
* 0 1 1 20 x130/2 x156/2 x66
|
||||
* 1 0 0 26 / 2 x200/2 x240/2 x122
|
||||
* 1 0 1 26 / 2 x200/2 x240/2 x102
|
||||
* 1 1 0 30 / 2 x172/2 x208/2 x106
|
||||
* 1 1 1 30 / 2 x172/2 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
|
||||
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
|
||||
/* EXTAL div PLL1 mult PLL3 mult */
|
||||
{ 1, 208, 106, },
|
||||
{ 1, 208, 88, },
|
||||
{ 1, 156, 80, },
|
||||
{ 1, 156, 66, },
|
||||
{ 2, 240, 122, },
|
||||
{ 2, 240, 102, },
|
||||
{ 2, 208, 106, },
|
||||
{ 2, 208, 88, },
|
||||
};
|
||||
|
||||
static int __init r8a7742_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
|
||||
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a7742_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a7742_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a7742_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a7742_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a7742_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a7742_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a7742_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a7742_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen2_cpg_clk_register,
|
||||
};
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* R9A09G032 clock driver
|
||||
* R9A06G032 clock driver
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Europe Limited
|
||||
*
|
||||
|
|
@ -338,8 +338,8 @@ clk_rdesc_get(struct r9a06g032_priv *clocks,
|
|||
}
|
||||
|
||||
/*
|
||||
* This implements the R9A09G032 clock gate 'driver'. We cannot use the system's
|
||||
* clock gate framework as the gates on the R9A09G032 have a special enabling
|
||||
* This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
|
||||
* clock gate framework as the gates on the R9A06G032 have a special enabling
|
||||
* sequence, therefore we use this little proxy.
|
||||
*/
|
||||
struct r9a06g032_clk_gate {
|
||||
|
|
|
|||
|
|
@ -673,6 +673,12 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.data = &r7s9210_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A7742
|
||||
{
|
||||
.compatible = "renesas,r8a7742-cpg-mssr",
|
||||
.data = &r8a7742_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A7743
|
||||
{
|
||||
.compatible = "renesas,r8a7743-cpg-mssr",
|
||||
|
|
@ -812,7 +818,8 @@ static int cpg_mssr_suspend_noirq(struct device *dev)
|
|||
/* Save module registers with bits under our control */
|
||||
for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
|
||||
if (priv->smstpcr_saved[reg].mask)
|
||||
priv->smstpcr_saved[reg].val =
|
||||
priv->smstpcr_saved[reg].val = priv->stbyctrl ?
|
||||
readb(priv->base + STBCR(reg)) :
|
||||
readl(priv->base + SMSTPCR(reg));
|
||||
}
|
||||
|
||||
|
|
@ -872,8 +879,9 @@ static int cpg_mssr_resume_noirq(struct device *dev)
|
|||
}
|
||||
|
||||
if (!i)
|
||||
dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n",
|
||||
priv->base + SMSTPCR(reg), oldval & mask);
|
||||
dev_warn(dev, "Failed to enable %s%u[0x%x]\n",
|
||||
priv->stbyctrl ? "STB" : "SMSTP", reg,
|
||||
oldval & mask);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -155,6 +155,7 @@ struct cpg_mssr_info {
|
|||
};
|
||||
|
||||
extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7742_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
|
||||
|
|
|
|||
|
|
@ -540,7 +540,7 @@ static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
|
|||
|
||||
static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
|
||||
GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
|
||||
GATE_BUS_TOP, 24, 0, 0),
|
||||
GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0),
|
||||
GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
|
||||
GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
|
||||
};
|
||||
|
|
@ -943,25 +943,25 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
|
|||
GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
|
||||
GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
|
||||
GATE_BUS_TOP, 5, 0, 0),
|
||||
GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0),
|
||||
GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
|
||||
GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
|
||||
GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
|
||||
GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
|
||||
GATE_BUS_TOP, 8, 0, 0),
|
||||
GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0),
|
||||
GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
|
||||
GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
|
||||
GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
|
||||
GATE_BUS_TOP, 13, 0, 0),
|
||||
GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0),
|
||||
GATE(0, "aclk166", "mout_user_aclk166",
|
||||
GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
|
||||
GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
|
||||
GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
|
||||
GATE_BUS_TOP, 16, 0, 0),
|
||||
GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0),
|
||||
GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
|
||||
GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
|
||||
GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
|
||||
|
|
@ -1161,9 +1161,11 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
|
|||
GATE_IP_GSCL1, 3, 0, 0),
|
||||
GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
|
||||
GATE_IP_GSCL1, 4, 0, 0),
|
||||
GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
|
||||
GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
|
||||
GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
|
||||
GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12,
|
||||
CLK_IS_CRITICAL, 0),
|
||||
GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13,
|
||||
CLK_IS_CRITICAL, 0),
|
||||
GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3", "dout_gscl_blk_333",
|
||||
GATE_IP_GSCL1, 16, 0, 0),
|
||||
GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
|
||||
GATE_IP_GSCL1, 17, 0, 0),
|
||||
|
|
|
|||
|
|
@ -1706,7 +1706,8 @@ static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
|
|||
GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
|
||||
ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
|
||||
ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
|
||||
ENABLE_SCLK_PERIC, 6,
|
||||
CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
|
||||
GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
|
||||
5, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
|
||||
|
|
|
|||
|
|
@ -387,7 +387,7 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
|
|||
ARRAY_SIZE(s3c2450_gates));
|
||||
samsung_clk_register_alias(ctx, s3c2450_aliases,
|
||||
ARRAY_SIZE(s3c2450_aliases));
|
||||
/* fall through - as s3c2450 extends the s3c2416 clocks */
|
||||
fallthrough; /* as s3c2450 extends the s3c2416 clocks */
|
||||
case S3C2416:
|
||||
samsung_clk_register_div(ctx, s3c2416_dividers,
|
||||
ARRAY_SIZE(s3c2416_dividers));
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ static void sun6i_a31_get_pll1_factors(struct factors_request *req)
|
|||
* Round down the frequency to the closest multiple of either
|
||||
* 6 or 16
|
||||
*/
|
||||
u32 round_freq_6 = round_down(freq_mhz, 6);
|
||||
u32 round_freq_6 = rounddown(freq_mhz, 6);
|
||||
u32 round_freq_16 = round_down(freq_mhz, 16);
|
||||
|
||||
if (round_freq_6 > round_freq_16)
|
||||
|
|
|
|||
|
|
@ -435,8 +435,7 @@ static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
|
|||
* fall through to the write state, as we will need to
|
||||
* send a byte as well
|
||||
*/
|
||||
/* Fall through */
|
||||
|
||||
fallthrough;
|
||||
case STATE_WRITE:
|
||||
/*
|
||||
* we are writing data to the device... check for the
|
||||
|
|
|
|||
|
|
@ -107,6 +107,7 @@
|
|||
#define CLKID_PERIPH 126
|
||||
#define CLKID_AXI 128
|
||||
#define CLKID_L2_DRAM 130
|
||||
#define CLKID_HDMI_SYS 174
|
||||
#define CLKID_VPU 190
|
||||
#define CLKID_VDEC_1 196
|
||||
#define CLKID_VDEC_HCODEC 199
|
||||
|
|
|
|||
|
|
@ -0,0 +1,42 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a7742 CPG Core Clocks */
|
||||
#define R8A7742_CLK_Z 0
|
||||
#define R8A7742_CLK_Z2 1
|
||||
#define R8A7742_CLK_ZG 2
|
||||
#define R8A7742_CLK_ZTR 3
|
||||
#define R8A7742_CLK_ZTRD2 4
|
||||
#define R8A7742_CLK_ZT 5
|
||||
#define R8A7742_CLK_ZX 6
|
||||
#define R8A7742_CLK_ZS 7
|
||||
#define R8A7742_CLK_HP 8
|
||||
#define R8A7742_CLK_B 9
|
||||
#define R8A7742_CLK_LB 10
|
||||
#define R8A7742_CLK_P 11
|
||||
#define R8A7742_CLK_CL 12
|
||||
#define R8A7742_CLK_M2 13
|
||||
#define R8A7742_CLK_ZB3 14
|
||||
#define R8A7742_CLK_ZB3D2 15
|
||||
#define R8A7742_CLK_DDR 16
|
||||
#define R8A7742_CLK_SDH 17
|
||||
#define R8A7742_CLK_SD0 18
|
||||
#define R8A7742_CLK_SD1 19
|
||||
#define R8A7742_CLK_SD2 20
|
||||
#define R8A7742_CLK_SD3 21
|
||||
#define R8A7742_CLK_MMC0 22
|
||||
#define R8A7742_CLK_MMC1 23
|
||||
#define R8A7742_CLK_MP 24
|
||||
#define R8A7742_CLK_QSPI 25
|
||||
#define R8A7742_CLK_CP 26
|
||||
#define R8A7742_CLK_RCAN 27
|
||||
#define R8A7742_CLK_R 28
|
||||
#define R8A7742_CLK_OSC 29
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A7742_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A7742_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A7742_PD_CA15_CPU0 0
|
||||
#define R8A7742_PD_CA15_CPU1 1
|
||||
#define R8A7742_PD_CA15_CPU2 2
|
||||
#define R8A7742_PD_CA15_CPU3 3
|
||||
#define R8A7742_PD_CA7_CPU0 5
|
||||
#define R8A7742_PD_CA7_CPU1 6
|
||||
#define R8A7742_PD_CA7_CPU2 7
|
||||
#define R8A7742_PD_CA7_CPU3 8
|
||||
#define R8A7742_PD_CA15_SCU 12
|
||||
#define R8A7742_PD_RGX 20
|
||||
#define R8A7742_PD_CA7_SCU 21
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A7742_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7742_SYSC_H__ */
|
||||
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