powerpc: introduce the ePAPR embedded hypervisor vmpic driver
The Freescale ePAPR reference hypervisor provides interrupt controller
services via a hypercall interface, instead of emulating the MPIC
controller. This is called the VMPIC.
The ePAPR "virtual interrupt controller" provides interrupt controller
services for external interrupts. External interrupts received by a
partition can come from two sources:
- Hardware interrupts - hardware interrupts come from external
interrupt lines or on-chip I/O devices.
- Virtual interrupts - virtual interrupts are generated by the hypervisor
as part of some hypervisor service or hypervisor-created virtual device.
Both types of interrupts are processed using the same programming model and
same set of hypercalls.
Signed-off-by: Ashish Kalra <ashish.kalra@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Ashish Kalra
Kumar Gala
Родитель
bd497fc978
Коммит
3a93261f70
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@ -0,0 +1,40 @@
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/*
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* EHV_PIC private definitions and structure.
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*
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef __EHV_PIC_H__
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#define __EHV_PIC_H__
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#include <linux/irq.h>
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#define NR_EHV_PIC_INTS 1024
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#define EHV_PIC_INFO(name) EHV_PIC_##name
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#define EHV_PIC_VECPRI_POLARITY_NEGATIVE 0
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#define EHV_PIC_VECPRI_POLARITY_POSITIVE 1
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#define EHV_PIC_VECPRI_SENSE_EDGE 0
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#define EHV_PIC_VECPRI_SENSE_LEVEL 0x2
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#define EHV_PIC_VECPRI_POLARITY_MASK 0x1
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#define EHV_PIC_VECPRI_SENSE_MASK 0x2
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struct ehv_pic {
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/* The remapper for this EHV_PIC */
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struct irq_host *irqhost;
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/* The "linux" controller struct */
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struct irq_chip hc_irq;
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/* core int flag */
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int coreint_flag;
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};
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void ehv_pic_init(void);
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unsigned int ehv_pic_get_irq(void);
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#endif /* __EHV_PIC_H__ */
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@ -78,6 +78,10 @@ config MPIC
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bool
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default n
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config PPC_EPAPR_HV_PIC
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bool
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default n
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config MPIC_WEIRD
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bool
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default n
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@ -4,6 +4,7 @@ ccflags-$(CONFIG_PPC64) := -mno-minimal-toc
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mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
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obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
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obj-$(CONFIG_PPC_EPAPR_HV_PIC) += ehv_pic.o
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fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o
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obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o
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@ -0,0 +1,302 @@
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/*
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* Driver for ePAPR Embedded Hypervisor PIC
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*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* Author: Ashish Kalra <ashish.kalra@freescale.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/smp.h>
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#include <asm/machdep.h>
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#include <asm/ehv_pic.h>
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#include <asm/fsl_hcalls.h>
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#include "../../../kernel/irq/settings.h"
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static struct ehv_pic *global_ehv_pic;
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static DEFINE_SPINLOCK(ehv_pic_lock);
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static u32 hwirq_intspec[NR_EHV_PIC_INTS];
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static u32 __iomem *mpic_percpu_base_vaddr;
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#define IRQ_TYPE_MPIC_DIRECT 4
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#define MPIC_EOI 0x00B0
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/*
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* Linux descriptor level callbacks
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*/
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void ehv_pic_unmask_irq(struct irq_data *d)
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{
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unsigned int src = virq_to_hw(d->irq);
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ev_int_set_mask(src, 0);
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}
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void ehv_pic_mask_irq(struct irq_data *d)
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{
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unsigned int src = virq_to_hw(d->irq);
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ev_int_set_mask(src, 1);
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}
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void ehv_pic_end_irq(struct irq_data *d)
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{
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unsigned int src = virq_to_hw(d->irq);
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ev_int_eoi(src);
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}
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void ehv_pic_direct_end_irq(struct irq_data *d)
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{
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out_be32(mpic_percpu_base_vaddr + MPIC_EOI / 4, 0);
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}
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int ehv_pic_set_affinity(struct irq_data *d, const struct cpumask *dest,
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bool force)
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{
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unsigned int src = virq_to_hw(d->irq);
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unsigned int config, prio, cpu_dest;
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int cpuid = irq_choose_cpu(dest);
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unsigned long flags;
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spin_lock_irqsave(&ehv_pic_lock, flags);
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ev_int_get_config(src, &config, &prio, &cpu_dest);
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ev_int_set_config(src, config, prio, cpuid);
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spin_unlock_irqrestore(&ehv_pic_lock, flags);
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return 0;
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}
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static unsigned int ehv_pic_type_to_vecpri(unsigned int type)
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{
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/* Now convert sense value */
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
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EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_EDGE_BOTH:
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return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
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EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
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case IRQ_TYPE_LEVEL_HIGH:
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return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
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EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
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case IRQ_TYPE_LEVEL_LOW:
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default:
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return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
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EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
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}
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}
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int ehv_pic_set_irq_type(struct irq_data *d, unsigned int flow_type)
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{
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unsigned int src = virq_to_hw(d->irq);
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struct irq_desc *desc = irq_to_desc(d->irq);
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unsigned int vecpri, vold, vnew, prio, cpu_dest;
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unsigned long flags;
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if (flow_type == IRQ_TYPE_NONE)
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flow_type = IRQ_TYPE_LEVEL_LOW;
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irq_settings_clr_level(desc);
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irq_settings_set_trigger_mask(desc, flow_type);
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if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
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irq_settings_set_level(desc);
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vecpri = ehv_pic_type_to_vecpri(flow_type);
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spin_lock_irqsave(&ehv_pic_lock, flags);
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ev_int_get_config(src, &vold, &prio, &cpu_dest);
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vnew = vold & ~(EHV_PIC_INFO(VECPRI_POLARITY_MASK) |
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EHV_PIC_INFO(VECPRI_SENSE_MASK));
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vnew |= vecpri;
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/*
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* TODO : Add specific interface call for platform to set
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* individual interrupt priorities.
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* platform currently using static/default priority for all ints
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*/
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prio = 8;
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ev_int_set_config(src, vecpri, prio, cpu_dest);
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spin_unlock_irqrestore(&ehv_pic_lock, flags);
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return 0;
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}
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static struct irq_chip ehv_pic_irq_chip = {
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.irq_mask = ehv_pic_mask_irq,
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.irq_unmask = ehv_pic_unmask_irq,
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.irq_eoi = ehv_pic_end_irq,
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.irq_set_type = ehv_pic_set_irq_type,
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};
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static struct irq_chip ehv_pic_direct_eoi_irq_chip = {
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.irq_mask = ehv_pic_mask_irq,
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.irq_unmask = ehv_pic_unmask_irq,
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.irq_eoi = ehv_pic_direct_end_irq,
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.irq_set_type = ehv_pic_set_irq_type,
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};
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/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
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unsigned int ehv_pic_get_irq(void)
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{
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int irq;
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BUG_ON(global_ehv_pic == NULL);
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if (global_ehv_pic->coreint_flag)
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irq = mfspr(SPRN_EPR); /* if core int mode */
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else
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ev_int_iack(0, &irq); /* legacy mode */
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if (irq == 0xFFFF) /* 0xFFFF --> no irq is pending */
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return NO_IRQ;
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/*
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* this will also setup revmap[] in the slow path for the first
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* time, next calls will always use fast path by indexing revmap
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*/
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return irq_linear_revmap(global_ehv_pic->irqhost, irq);
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}
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static int ehv_pic_host_match(struct irq_host *h, struct device_node *node)
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{
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/* Exact match, unless ehv_pic node is NULL */
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return h->of_node == NULL || h->of_node == node;
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}
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static int ehv_pic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct ehv_pic *ehv_pic = h->host_data;
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struct irq_chip *chip;
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/* Default chip */
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chip = &ehv_pic->hc_irq;
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if (mpic_percpu_base_vaddr)
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if (hwirq_intspec[hw] & IRQ_TYPE_MPIC_DIRECT)
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chip = &ehv_pic_direct_eoi_irq_chip;
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irq_set_chip_data(virq, chip);
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/*
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* using handle_fasteoi_irq as our irq handler, this will
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* only call the eoi callback and suitable for the MPIC
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* controller which set ISR/IPR automatically and clear the
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* highest priority active interrupt in ISR/IPR when we do
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* a specific eoi
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*/
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irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
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/* Set default irq type */
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irq_set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static int ehv_pic_host_xlate(struct irq_host *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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/*
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* interrupt sense values coming from the guest device tree
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* interrupt specifiers can have four possible sense and
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* level encoding information and they need to
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* be translated between firmware type & linux type.
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*/
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static unsigned char map_of_senses_to_linux_irqtype[4] = {
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IRQ_TYPE_EDGE_FALLING,
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IRQ_TYPE_EDGE_RISING,
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IRQ_TYPE_LEVEL_LOW,
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IRQ_TYPE_LEVEL_HIGH,
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};
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*out_hwirq = intspec[0];
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if (intsize > 1) {
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hwirq_intspec[intspec[0]] = intspec[1];
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*out_flags = map_of_senses_to_linux_irqtype[intspec[1] &
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~IRQ_TYPE_MPIC_DIRECT];
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} else {
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*out_flags = IRQ_TYPE_NONE;
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}
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return 0;
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}
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static struct irq_host_ops ehv_pic_host_ops = {
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.match = ehv_pic_host_match,
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.map = ehv_pic_host_map,
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.xlate = ehv_pic_host_xlate,
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};
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void __init ehv_pic_init(void)
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{
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struct device_node *np, *np2;
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struct ehv_pic *ehv_pic;
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int coreint_flag = 1;
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np = of_find_compatible_node(NULL, NULL, "epapr,hv-pic");
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if (!np) {
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pr_err("ehv_pic_init: could not find epapr,hv-pic node\n");
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return;
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}
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if (!of_find_property(np, "has-external-proxy", NULL))
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coreint_flag = 0;
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ehv_pic = kzalloc(sizeof(struct ehv_pic), GFP_KERNEL);
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if (!ehv_pic) {
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of_node_put(np);
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return;
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}
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ehv_pic->irqhost = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
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NR_EHV_PIC_INTS, &ehv_pic_host_ops, 0);
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if (!ehv_pic->irqhost) {
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of_node_put(np);
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return;
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}
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np2 = of_find_compatible_node(NULL, NULL, "fsl,hv-mpic-per-cpu");
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if (np2) {
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mpic_percpu_base_vaddr = of_iomap(np2, 0);
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if (!mpic_percpu_base_vaddr)
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pr_err("ehv_pic_init: of_iomap failed\n");
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of_node_put(np2);
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}
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ehv_pic->irqhost->host_data = ehv_pic;
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ehv_pic->hc_irq = ehv_pic_irq_chip;
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ehv_pic->hc_irq.irq_set_affinity = ehv_pic_set_affinity;
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ehv_pic->coreint_flag = coreint_flag;
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global_ehv_pic = ehv_pic;
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irq_set_default_host(global_ehv_pic->irqhost);
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}
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