tg3: Add function tg3_phy_shdw_write()

For consistency with other register access functions, add shadow
register access function of the type (register/val).

Signed-off-by: Nithin Nayak Sujir <nsujir@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Nithin Sujir 2013-09-20 16:46:55 -07:00 коммит произвёл David S. Miller
Родитель 8dda204164
Коммит 3ab7107133
1 изменённых файлов: 10 добавлений и 8 удалений

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@ -1326,6 +1326,12 @@ static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
return err;
}
static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
{
return tg3_writephy(tp, MII_TG3_MISC_SHDW,
reg | val | MII_TG3_MISC_SHDW_WREN);
}
static int tg3_bmcr_reset(struct tg3 *tp)
{
u32 phy_control;
@ -2218,25 +2224,21 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
return;
}
reg = MII_TG3_MISC_SHDW_WREN |
MII_TG3_MISC_SHDW_SCR5_SEL |
MII_TG3_MISC_SHDW_SCR5_LPED |
reg = MII_TG3_MISC_SHDW_SCR5_LPED |
MII_TG3_MISC_SHDW_SCR5_DLPTLM |
MII_TG3_MISC_SHDW_SCR5_SDTL |
MII_TG3_MISC_SHDW_SCR5_C125OE;
if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
reg = MII_TG3_MISC_SHDW_WREN |
MII_TG3_MISC_SHDW_APD_SEL |
MII_TG3_MISC_SHDW_APD_WKTM_84MS;
reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
if (enable)
reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
}
static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)