tg3: Add function tg3_phy_shdw_write()
For consistency with other register access functions, add shadow register access function of the type (register/val). Signed-off-by: Nithin Nayak Sujir <nsujir@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1326,6 +1326,12 @@ static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
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return err;
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}
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static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
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{
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return tg3_writephy(tp, MII_TG3_MISC_SHDW,
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reg | val | MII_TG3_MISC_SHDW_WREN);
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}
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static int tg3_bmcr_reset(struct tg3 *tp)
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{
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u32 phy_control;
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@ -2218,25 +2224,21 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
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return;
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}
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reg = MII_TG3_MISC_SHDW_WREN |
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MII_TG3_MISC_SHDW_SCR5_SEL |
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MII_TG3_MISC_SHDW_SCR5_LPED |
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reg = MII_TG3_MISC_SHDW_SCR5_LPED |
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MII_TG3_MISC_SHDW_SCR5_DLPTLM |
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MII_TG3_MISC_SHDW_SCR5_SDTL |
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MII_TG3_MISC_SHDW_SCR5_C125OE;
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if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
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reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
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tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
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tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
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reg = MII_TG3_MISC_SHDW_WREN |
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MII_TG3_MISC_SHDW_APD_SEL |
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MII_TG3_MISC_SHDW_APD_WKTM_84MS;
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reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
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if (enable)
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reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
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tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
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tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
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}
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static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
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