netxen: remove netxen_nic_niu.c
Consolidate all MAC/PHY access functions into netxen_nic_hw.c Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dhananjay Phadke
David S. Miller
Родитель
c9517e5893
Коммит
3ad4467ca4
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@ -31,4 +31,4 @@
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obj-$(CONFIG_NETXEN_NIC) := netxen_nic.o
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netxen_nic-y := netxen_nic_hw.o netxen_nic_main.o netxen_nic_init.o \
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netxen_nic_ethtool.o netxen_nic_niu.o netxen_nic_ctx.o
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netxen_nic_ethtool.o netxen_nic_ctx.o
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@ -684,7 +684,19 @@ struct netxen_recv_context {
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#define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
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#define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
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#define NX_CDRP_CMD_SET_MTU 0x00000012
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#define NX_CDRP_CMD_MAX 0x00000013
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#define NX_CDRP_CMD_READ_PHY 0x00000013
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#define NX_CDRP_CMD_WRITE_PHY 0x00000014
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#define NX_CDRP_CMD_READ_HW_REG 0x00000015
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#define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016
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#define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017
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#define NX_CDRP_CMD_READ_MAX_MTU 0x00000018
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#define NX_CDRP_CMD_READ_MAX_LRO 0x00000019
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#define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a
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#define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b
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#define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
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#define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
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#define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
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#define NX_CDRP_CMD_MAX 0x0000001f
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#define NX_RCODE_SUCCESS 0
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#define NX_RCODE_NO_HOST_MEM 1
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@ -1152,8 +1164,8 @@ struct netxen_adapter {
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int (*set_mtu) (struct netxen_adapter *, int);
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int (*set_promisc) (struct netxen_adapter *, u32);
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void (*set_multi) (struct net_device *);
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int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
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int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
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int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *);
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int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val);
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int (*init_port) (struct netxen_adapter *, int);
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int (*stop_port) (struct netxen_adapter *);
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@ -1185,15 +1197,11 @@ struct netxen_adapter {
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const struct firmware *fw;
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};
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int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
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u32 mode);
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int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
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int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
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int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
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__u32 * readval);
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int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
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long reg, __u32 val);
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int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val);
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int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val);
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/* Functions available from netxen_nic_hw.c */
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int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
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@ -1313,6 +1321,7 @@ int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
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void netxen_p2_nic_set_multi(struct net_device *netdev);
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void netxen_p3_nic_set_multi(struct net_device *netdev);
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void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
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int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode);
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int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
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int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
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int netxen_config_rss(struct netxen_adapter *adapter, int enable);
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@ -380,6 +380,44 @@ nx_fw_cmd_destroy_tx_ctx(struct netxen_adapter *adapter)
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}
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}
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int
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nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val)
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{
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u32 rcode;
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rcode = netxen_issue_cmd(adapter,
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adapter->ahw.pci_func,
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NXHAL_VERSION,
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reg,
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0,
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0,
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NX_CDRP_CMD_READ_PHY);
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if (rcode != NX_RCODE_SUCCESS)
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return -EIO;
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return NXRD32(adapter, NX_ARG1_CRB_OFFSET);
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}
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int
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nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val)
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{
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u32 rcode;
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rcode = netxen_issue_cmd(adapter,
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adapter->ahw.pci_func,
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NXHAL_VERSION,
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reg,
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val,
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0,
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NX_CDRP_CMD_WRITE_PHY);
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if (rcode != NX_RCODE_SUCCESS)
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return -EIO;
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return 0;
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}
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static u64 ctx_addr_sig_regs[][3] = {
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{NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
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{NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
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@ -348,6 +348,35 @@ netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
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val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
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}
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int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
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{
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if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
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NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
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NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
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}
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return 0;
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}
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/* Disable an XG interface */
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int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
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{
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__u32 mac_cfg;
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u32 port = adapter->physical_port;
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if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
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return 0;
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if (port > NETXEN_NIU_MAX_XG_PORTS)
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return -EINVAL;
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mac_cfg = 0;
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if (NXWR32(adapter,
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NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
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return -EIO;
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return 0;
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}
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#define NETXEN_UNICAST_ADDR(port, index) \
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(NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
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#define NETXEN_MCAST_ADDR(port, index) \
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@ -357,6 +386,56 @@ netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
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#define MAC_LO(addr) \
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((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
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int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
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{
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__u32 reg;
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u32 port = adapter->physical_port;
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if (port > NETXEN_NIU_MAX_XG_PORTS)
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return -EINVAL;
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reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
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if (mode == NETXEN_NIU_PROMISC_MODE)
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reg = (reg | 0x2000UL);
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else
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reg = (reg & ~0x2000UL);
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if (mode == NETXEN_NIU_ALLMULTI_MODE)
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reg = (reg | 0x1000UL);
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else
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reg = (reg & ~0x1000UL);
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NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
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return 0;
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}
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int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
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{
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u32 mac_hi, mac_lo;
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u32 reg_hi, reg_lo;
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u8 phy = adapter->physical_port;
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if (phy >= NETXEN_NIU_MAX_XG_PORTS)
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return -EINVAL;
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mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
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mac_hi = addr[2] | ((u32)addr[3] << 8) |
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((u32)addr[4] << 16) | ((u32)addr[5] << 24);
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reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
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reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
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/* write twice to flush */
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if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
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return -EIO;
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if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
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return -EIO;
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return 0;
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}
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static int
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netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
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{
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@ -328,17 +328,17 @@ void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
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adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
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adapter->set_multi = netxen_p2_nic_set_multi;
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adapter->set_mtu = netxen_nic_set_mtu_xgb;
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adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
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adapter->set_promisc = netxen_p2_nic_set_promisc;
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} else {
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adapter->set_mtu = nx_fw_cmd_set_mtu;
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adapter->set_promisc = netxen_p3_nic_set_promisc;
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adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
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adapter->set_multi = netxen_p3_nic_set_multi;
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}
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if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
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adapter->phy_read = netxen_niu_gbe_phy_read;
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adapter->phy_write = netxen_niu_gbe_phy_write;
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if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
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adapter->phy_read = nx_fw_cmd_query_phy;
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adapter->phy_write = nx_fw_cmd_set_phy;
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}
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}
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}
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@ -1,275 +0,0 @@
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/*
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* Copyright (C) 2003 - 2009 NetXen, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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* MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.
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*
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* Contact Information:
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* info@netxen.com
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* NetXen Inc,
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* 18922 Forge Drive
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* Cupertino, CA 95014-0701
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*
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*/
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#include "netxen_nic.h"
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/*
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* netxen_niu_gbe_phy_read - read a register from the GbE PHY via
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* mii management interface.
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*
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* Note: The MII management interface goes through port 0.
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* Individual phys are addressed as follows:
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* @param phy [15:8] phy id
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* @param reg [7:0] register number
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*
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* @returns 0 on success
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* -1 on error
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*
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*/
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int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
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__u32 * readval)
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{
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long timeout = 0;
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long result = 0;
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long restore = 0;
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long phy = adapter->physical_port;
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__u32 address;
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__u32 command;
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__u32 status;
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__u32 mac_cfg0;
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if (netxen_phy_lock(adapter) != 0)
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return -1;
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/*
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* MII mgmt all goes through port 0 MAC interface,
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* so it cannot be in reset
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*/
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mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
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if (netxen_gb_get_soft_reset(mac_cfg0)) {
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__u32 temp;
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temp = 0;
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netxen_gb_tx_reset_pb(temp);
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netxen_gb_rx_reset_pb(temp);
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netxen_gb_tx_reset_mac(temp);
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netxen_gb_rx_reset_mac(temp);
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if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
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return -EIO;
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restore = 1;
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}
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address = 0;
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netxen_gb_mii_mgmt_reg_addr(address, reg);
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netxen_gb_mii_mgmt_phy_addr(address, phy);
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
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return -EIO;
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command = 0; /* turn off any prior activity */
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
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return -EIO;
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/* send read command */
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netxen_gb_mii_mgmt_set_read_cycle(command);
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
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return -EIO;
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status = 0;
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do {
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status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
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timeout++;
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} while ((netxen_get_gb_mii_mgmt_busy(status)
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|| netxen_get_gb_mii_mgmt_notvalid(status))
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&& (timeout++ < NETXEN_NIU_PHY_WAITMAX));
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if (timeout < NETXEN_NIU_PHY_WAITMAX) {
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*readval = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_STATUS(0));
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result = 0;
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} else
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result = -1;
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if (restore)
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if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
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return -EIO;
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netxen_phy_unlock(adapter);
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return result;
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}
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/*
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* netxen_niu_gbe_phy_write - write a register to the GbE PHY via
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* mii management interface.
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*
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* Note: The MII management interface goes through port 0.
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* Individual phys are addressed as follows:
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* @param phy [15:8] phy id
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* @param reg [7:0] register number
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*
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* @returns 0 on success
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* -1 on error
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*
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*/
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int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
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__u32 val)
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{
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long timeout = 0;
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long result = 0;
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long restore = 0;
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long phy = adapter->physical_port;
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__u32 address;
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__u32 command;
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__u32 status;
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__u32 mac_cfg0;
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/*
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* MII mgmt all goes through port 0 MAC interface, so it
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* cannot be in reset
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*/
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mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
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if (netxen_gb_get_soft_reset(mac_cfg0)) {
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__u32 temp;
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temp = 0;
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netxen_gb_tx_reset_pb(temp);
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netxen_gb_rx_reset_pb(temp);
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netxen_gb_tx_reset_mac(temp);
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netxen_gb_rx_reset_mac(temp);
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if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
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return -EIO;
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restore = 1;
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}
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command = 0; /* turn off any prior activity */
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
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return -EIO;
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address = 0;
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netxen_gb_mii_mgmt_reg_addr(address, reg);
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netxen_gb_mii_mgmt_phy_addr(address, phy);
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
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return -EIO;
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if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0), val))
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return -EIO;
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status = 0;
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do {
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status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
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timeout++;
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} while ((netxen_get_gb_mii_mgmt_busy(status))
|
||||
&& (timeout++ < NETXEN_NIU_PHY_WAITMAX));
|
||||
|
||||
if (timeout < NETXEN_NIU_PHY_WAITMAX)
|
||||
result = 0;
|
||||
else
|
||||
result = -EIO;
|
||||
|
||||
/* restore the state of port 0 MAC in case we tampered with it */
|
||||
if (restore)
|
||||
if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
|
||||
return -EIO;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
|
||||
{
|
||||
if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
|
||||
NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
|
||||
NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Disable an XG interface */
|
||||
int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
|
||||
{
|
||||
__u32 mac_cfg;
|
||||
u32 port = adapter->physical_port;
|
||||
|
||||
if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
|
||||
return 0;
|
||||
|
||||
if (port > NETXEN_NIU_MAX_XG_PORTS)
|
||||
return -EINVAL;
|
||||
|
||||
mac_cfg = 0;
|
||||
if (NXWR32(adapter,
|
||||
NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
|
||||
return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
|
||||
u32 mode)
|
||||
{
|
||||
__u32 reg;
|
||||
u32 port = adapter->physical_port;
|
||||
|
||||
if (port > NETXEN_NIU_MAX_XG_PORTS)
|
||||
return -EINVAL;
|
||||
|
||||
reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
|
||||
if (mode == NETXEN_NIU_PROMISC_MODE)
|
||||
reg = (reg | 0x2000UL);
|
||||
else
|
||||
reg = (reg & ~0x2000UL);
|
||||
|
||||
if (mode == NETXEN_NIU_ALLMULTI_MODE)
|
||||
reg = (reg | 0x1000UL);
|
||||
else
|
||||
reg = (reg & ~0x1000UL);
|
||||
|
||||
NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
|
||||
{
|
||||
u32 mac_hi, mac_lo;
|
||||
u32 reg_hi, reg_lo;
|
||||
|
||||
u8 phy = adapter->physical_port;
|
||||
u8 phy_count = (adapter->ahw.port_type == NETXEN_NIC_XGBE) ?
|
||||
NETXEN_NIU_MAX_XG_PORTS : NETXEN_NIU_MAX_GBE_PORTS;
|
||||
|
||||
if (phy >= phy_count)
|
||||
return -EINVAL;
|
||||
|
||||
mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
|
||||
mac_hi = addr[2] | ((u32)addr[3] << 8) |
|
||||
((u32)addr[4] << 16) | ((u32)addr[5] << 24);
|
||||
|
||||
if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
|
||||
reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
|
||||
reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
|
||||
} else {
|
||||
reg_lo = NETXEN_NIU_GB_STATION_ADDR_1(phy);
|
||||
reg_hi = NETXEN_NIU_GB_STATION_ADDR_0(phy);
|
||||
}
|
||||
|
||||
/* write twice to flush */
|
||||
if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
|
||||
return -EIO;
|
||||
if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
|
||||
return -EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
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