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clk: sprd: mark the local clock symbols static 

There's a few pll gate clocks which were not marked with static, and
those clock are used only in the current file, so add static key word
for them.

Fixes: 0e4b8a2349 ("clk: sprd: add clocks support for SC9863A")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200519030036.1785-1-zhang.lyra@gmail.com
Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Chunyan Zhang 2020-05-19 11:00:35 +08:00 коммит произвёл Stephen Boyd
Родитель 8f3d9f3542
Коммит 3aff9b5492
1 изменённых файлов: 16 добавлений и 16 удалений
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32
drivers/clk/sprd/sc9863a-clk.c
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@ -23,22 +23,22 @@
#include "pll.h" #include "pll.h"
/* mpll*_gate clocks control cpu cores, they were enabled by default */ /* mpll*_gate clocks control cpu cores, they were enabled by default */
SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94, static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98, static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
0x1000, BIT(0), 0, 0, 240); 0x1000, BIT(0), 0, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c, static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
0x1000, BIT(0), 0, 0, 240); 0x1000, BIT(0), 0, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8, static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
0x1000, BIT(0), 0, 0, 240); 0x1000, BIT(0), 0, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc, static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
0x1000, BIT(0), 0, 0, 240); 0x1000, BIT(0), 0, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0, static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4, static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m", 0x1e8, static SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m",
0x1000, BIT(0), 0, 0, 240); 0x1e8, 0x1000, BIT(0), 0, 0, 240);
static struct sprd_clk_common *sc9863a_pmu_gate_clks[] = { static struct sprd_clk_common *sc9863a_pmu_gate_clks[] = {
/* address base is 0x402b0000 */ /* address base is 0x402b0000 */