ARM: Merge next-samsung-s3c2443-clock
Merge branch 'next-samsung-s3c2443-clock' into next-samsung
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Коммит
3b05007e43
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@ -42,23 +42,14 @@
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#define S3C2443_PLLCON_OFF (1<<24)
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#define S3C2443_CLKSRC_I2S_EXT (1<<14)
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#define S3C2443_CLKSRC_I2S_EPLLDIV (0<<14)
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#define S3C2443_CLKSRC_I2S_EPLLREF (2<<14)
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#define S3C2443_CLKSRC_I2S_EPLLREF3 (3<<14)
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#define S3C2443_CLKSRC_I2S_MASK (3<<14)
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#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
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#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7)
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#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7)
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#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
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#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
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#define S3C2443_CLKSRC_ESYSCLK_EPLL (1<<6)
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#define S3C2443_CLKSRC_MSYSCLK_MPLL (1<<4)
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#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
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#define S3C2443_CLKDIV0_DVS (1<<13)
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#define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
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#define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
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@ -81,28 +72,7 @@
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#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
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#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
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/* S3C2443_CLKDIV1 */
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#define S3C2443_CLKDIV1_CAMDIV_MASK (15<<26)
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#define S3C2443_CLKDIV1_CAMDIV_SHIFT (26)
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#define S3C2443_CLKDIV1_HSSPIDIV_MASK (3<<24)
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#define S3C2443_CLKDIV1_HSSPIDIV_SHIFT (24)
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#define S3C2443_CLKDIV1_DISPDIV_MASK (0xff<<16)
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#define S3C2443_CLKDIV1_DISPDIV_SHIFT (16)
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#define S3C2443_CLKDIV1_I2SDIV_MASK (15<<12)
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#define S3C2443_CLKDIV1_I2SDIV_SHIFT (12)
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#define S3C2443_CLKDIV1_UARTDIV_MASK (15<<8)
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#define S3C2443_CLKDIV1_UARTDIV_SHIFT (8)
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#define S3C2443_CLKDIV1_HSMMCDIV_MASK (3<<6)
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#define S3C2443_CLKDIV1_HSMMCDIV_SHIFT (6)
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#define S3C2443_CLKDIV1_USBHOSTDIV_MASK (3<<4)
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#define S3C2443_CLKDIV1_USBHOSTDIV_SHIFT (4)
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/* S3C2443_CLKDIV1 removed, only used in clock.c code */
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#define S3C2443_CLKCON_NAND
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@ -7,6 +7,7 @@ config CPU_S3C2443
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depends on ARCH_S3C2410
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select S3C2443_DMA if S3C2410_DMA
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select CPU_LLSERIAL_S3C2440
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select SAMSUNG_CLKSRC
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help
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Support for the S3C2443 SoC from the S3C24XX line
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