Merge branch 'for_tony_a_2.6.39rc' of git://git.pwsan.com/linux-2.6 into devel-fixes
This commit is contained in:
Коммит
3b1fb2ffec
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@ -3116,14 +3116,9 @@ static struct omap_clk omap44xx_clks[] = {
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CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
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CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X),
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CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X),
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CLK("omapdss_dss", "dss_clk", &dss_dss_clk, CK_443X),
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CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X),
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CLK("omapdss_dss", "fck", &dss_fck, CK_443X),
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/*
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* On OMAP4, DSS ick is a dummy clock; this is needed for compatibility
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* with OMAP2/3.
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*/
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CLK("omapdss_dss", "ick", &dummy_ck, CK_443X),
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CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X),
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CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
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CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
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CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
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CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
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@ -247,6 +247,7 @@ struct omap3_cm_regs {
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u32 per_cm_clksel;
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u32 emu_cm_clksel;
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u32 emu_cm_clkstctrl;
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u32 pll_cm_autoidle;
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u32 pll_cm_autoidle2;
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u32 pll_cm_clksel4;
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u32 pll_cm_clksel5;
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@ -319,6 +320,15 @@ void omap3_cm_save_context(void)
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omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
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cm_context.emu_cm_clkstctrl =
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omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
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/*
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* As per erratum i671, ROM code does not respect the PER DPLL
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* programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
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* In this case, even though this register has been saved in
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* scratchpad contents, we need to restore AUTO_PERIPH_DPLL
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* by ourselves. So, we need to save it anyway.
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*/
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cm_context.pll_cm_autoidle =
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omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
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cm_context.pll_cm_autoidle2 =
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omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
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cm_context.pll_cm_clksel4 =
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@ -441,6 +451,13 @@ void omap3_cm_restore_context(void)
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CM_CLKSEL1);
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omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
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OMAP2_CM_CLKSTCTRL);
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/*
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* As per erratum i671, ROM code does not respect the PER DPLL
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* programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
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* In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
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*/
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omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
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CM_AUTOIDLE);
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omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
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CM_AUTOIDLE2);
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omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
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@ -316,8 +316,14 @@ void omap3_save_scratchpad_contents(void)
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omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
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prcm_block_contents.cm_clken_pll =
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omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
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/*
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* As per erratum i671, ROM code does not respect the PER DPLL
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* programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
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* Then, in anycase, clear these bits to avoid extra latencies.
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*/
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prcm_block_contents.cm_autoidle_pll =
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omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
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omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
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~OMAP3430_AUTO_PERIPH_DPLL_MASK;
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prcm_block_contents.cm_clksel1_pll =
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omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
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prcm_block_contents.cm_clksel2_pll =
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@ -1639,6 +1639,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
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static struct omap_hwmod omap2420_gpio1_hwmod = {
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.name = "gpio1",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap242x_gpio1_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
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.main_clk = "gpios_fck",
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@ -1669,6 +1670,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
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static struct omap_hwmod omap2420_gpio2_hwmod = {
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.name = "gpio2",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap242x_gpio2_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
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.main_clk = "gpios_fck",
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@ -1699,6 +1701,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
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static struct omap_hwmod omap2420_gpio3_hwmod = {
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.name = "gpio3",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap242x_gpio3_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
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.main_clk = "gpios_fck",
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@ -1729,6 +1732,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
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static struct omap_hwmod omap2420_gpio4_hwmod = {
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.name = "gpio4",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap242x_gpio4_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
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.main_clk = "gpios_fck",
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@ -1782,7 +1786,7 @@ static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
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static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
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{
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.pa_start = 0x48056000,
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.pa_end = 0x4a0560ff,
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.pa_end = 0x48056fff,
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.flags = ADDR_TYPE_RT
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},
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};
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@ -1742,6 +1742,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
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static struct omap_hwmod omap2430_gpio1_hwmod = {
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.name = "gpio1",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap243x_gpio1_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
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.main_clk = "gpios_fck",
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@ -1772,6 +1773,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
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static struct omap_hwmod omap2430_gpio2_hwmod = {
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.name = "gpio2",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap243x_gpio2_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
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.main_clk = "gpios_fck",
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@ -1802,6 +1804,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
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static struct omap_hwmod omap2430_gpio3_hwmod = {
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.name = "gpio3",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap243x_gpio3_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
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.main_clk = "gpios_fck",
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@ -1832,6 +1835,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
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static struct omap_hwmod omap2430_gpio4_hwmod = {
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.name = "gpio4",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap243x_gpio4_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
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.main_clk = "gpios_fck",
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@ -1862,6 +1866,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
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static struct omap_hwmod omap2430_gpio5_hwmod = {
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.name = "gpio5",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap243x_gpio5_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
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.main_clk = "gpio5_fck",
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@ -1915,7 +1920,7 @@ static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
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static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
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{
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.pa_start = 0x48056000,
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.pa_end = 0x4a0560ff,
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.pa_end = 0x48056fff,
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.flags = ADDR_TYPE_RT
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},
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};
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@ -2141,6 +2141,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
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static struct omap_hwmod omap3xxx_gpio1_hwmod = {
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.name = "gpio1",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap3xxx_gpio1_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
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.main_clk = "gpio1_ick",
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@ -2177,6 +2178,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
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static struct omap_hwmod omap3xxx_gpio2_hwmod = {
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.name = "gpio2",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap3xxx_gpio2_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
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.main_clk = "gpio2_ick",
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@ -2213,6 +2215,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
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static struct omap_hwmod omap3xxx_gpio3_hwmod = {
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.name = "gpio3",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap3xxx_gpio3_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
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.main_clk = "gpio3_ick",
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@ -2249,6 +2252,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
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static struct omap_hwmod omap3xxx_gpio4_hwmod = {
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.name = "gpio4",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap3xxx_gpio4_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
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.main_clk = "gpio4_ick",
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@ -2285,6 +2289,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
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static struct omap_hwmod omap3xxx_gpio5_hwmod = {
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.name = "gpio5",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap3xxx_gpio5_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
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.main_clk = "gpio5_ick",
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@ -2321,6 +2326,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
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static struct omap_hwmod omap3xxx_gpio6_hwmod = {
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.name = "gpio6",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.mpu_irqs = omap3xxx_gpio6_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
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.main_clk = "gpio6_ick",
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@ -2386,7 +2392,7 @@ static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
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static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
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{
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.pa_start = 0x48056000,
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.pa_end = 0x4a0560ff,
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.pa_end = 0x48056fff,
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.flags = ADDR_TYPE_RT
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},
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};
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@ -885,7 +885,7 @@ static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
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static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
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{
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.pa_start = 0x4a056000,
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.pa_end = 0x4a0560ff,
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.pa_end = 0x4a056fff,
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.flags = ADDR_TYPE_RT
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},
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};
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