dmaengine: PL08x: Add cyclic transfer support
Many audio interface drivers require support of cyclic transfers to work correctly, for example Samsung ASoC DMA driver. This patch adds support for cyclic transfers to the amba-pl08x driver. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> [tfiga: Rebase and slightly beautify the original patch.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Alban Bedel
Vinod Koul
Родитель
f3287a5206
Коммит
3b24c20b20
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@ -173,6 +173,7 @@ struct pl08x_sg {
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* @ccfg: config reg values for current txd
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* @done: this marks completed descriptors, which should not have their
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* mux released.
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* @cyclic: indicate cyclic transfers
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*/
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struct pl08x_txd {
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struct virt_dma_desc vd;
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@ -187,6 +188,7 @@ struct pl08x_txd {
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*/
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u32 ccfg;
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bool done;
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bool cyclic;
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};
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/**
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@ -574,9 +576,9 @@ static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
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bytes += get_bytes_in_cctl(llis_va[PL080_LLI_CCTL]);
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/*
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* A LLI pointer of 0 terminates the LLI list
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* A LLI pointer going backward terminates the LLI list
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*/
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if (!llis_va[PL080_LLI_LLI])
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if (llis_va[PL080_LLI_LLI] <= clli)
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break;
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}
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@ -1125,10 +1127,16 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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llis_va = txd->llis_va;
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last_lli = llis_va + (num_llis - 1) * pl08x->lli_words;
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/* The final LLI terminates the LLI. */
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last_lli[PL080_LLI_LLI] = 0;
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/* The final LLI element shall also fire an interrupt. */
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last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN;
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if (txd->cyclic) {
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/* Link back to the first LLI. */
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last_lli[PL080_LLI_LLI] = txd->llis_bus | bd.lli_bus;
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} else {
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/* The final LLI terminates the LLI. */
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last_lli[PL080_LLI_LLI] = 0;
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/* The final LLI element shall also fire an interrupt. */
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last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN;
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}
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pl08x_dump_lli(pl08x, llis_va, num_llis);
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@ -1513,25 +1521,19 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
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return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
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}
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static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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static struct pl08x_txd *pl08x_init_txd(
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struct dma_chan *chan,
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enum dma_transfer_direction direction,
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dma_addr_t *slave_addr)
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{
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struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
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struct pl08x_driver_data *pl08x = plchan->host;
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struct pl08x_txd *txd;
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struct pl08x_sg *dsg;
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struct scatterlist *sg;
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enum dma_slave_buswidth addr_width;
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dma_addr_t slave_addr;
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int ret, tmp;
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u8 src_buses, dst_buses;
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u32 maxburst, cctl;
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dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
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__func__, sg_dma_len(sgl), plchan->name);
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txd = pl08x_get_txd(plchan);
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if (!txd) {
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dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
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@ -1545,14 +1547,14 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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*/
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if (direction == DMA_MEM_TO_DEV) {
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cctl = PL080_CONTROL_SRC_INCR;
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slave_addr = plchan->cfg.dst_addr;
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*slave_addr = plchan->cfg.dst_addr;
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addr_width = plchan->cfg.dst_addr_width;
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maxburst = plchan->cfg.dst_maxburst;
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src_buses = pl08x->mem_buses;
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dst_buses = plchan->cd->periph_buses;
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} else if (direction == DMA_DEV_TO_MEM) {
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cctl = PL080_CONTROL_DST_INCR;
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slave_addr = plchan->cfg.src_addr;
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*slave_addr = plchan->cfg.src_addr;
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addr_width = plchan->cfg.src_addr_width;
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maxburst = plchan->cfg.src_maxburst;
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src_buses = plchan->cd->periph_buses;
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@ -1601,24 +1603,107 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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else
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txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
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return txd;
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}
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static int pl08x_tx_add_sg(struct pl08x_txd *txd,
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enum dma_transfer_direction direction,
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dma_addr_t slave_addr,
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dma_addr_t buf_addr,
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unsigned int len)
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{
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struct pl08x_sg *dsg;
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dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
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if (!dsg)
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return -ENOMEM;
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list_add_tail(&dsg->node, &txd->dsg_list);
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dsg->len = len;
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if (direction == DMA_MEM_TO_DEV) {
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dsg->src_addr = buf_addr;
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dsg->dst_addr = slave_addr;
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} else {
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dsg->src_addr = slave_addr;
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dsg->dst_addr = buf_addr;
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}
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return 0;
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}
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static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
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struct pl08x_driver_data *pl08x = plchan->host;
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struct pl08x_txd *txd;
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struct scatterlist *sg;
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int ret, tmp;
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dma_addr_t slave_addr;
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dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
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__func__, sg_dma_len(sgl), plchan->name);
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txd = pl08x_init_txd(chan, direction, &slave_addr);
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if (!txd)
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return NULL;
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for_each_sg(sgl, sg, sg_len, tmp) {
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dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
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if (!dsg) {
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ret = pl08x_tx_add_sg(txd, direction, slave_addr,
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sg_dma_address(sg),
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sg_dma_len(sg));
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if (ret) {
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pl08x_release_mux(plchan);
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pl08x_free_txd(pl08x, txd);
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dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
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__func__);
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return NULL;
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}
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list_add_tail(&dsg->node, &txd->dsg_list);
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}
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dsg->len = sg_dma_len(sg);
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if (direction == DMA_MEM_TO_DEV) {
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dsg->src_addr = sg_dma_address(sg);
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dsg->dst_addr = slave_addr;
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} else {
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dsg->src_addr = slave_addr;
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dsg->dst_addr = sg_dma_address(sg);
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ret = pl08x_fill_llis_for_desc(plchan->host, txd);
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if (!ret) {
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pl08x_release_mux(plchan);
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pl08x_free_txd(pl08x, txd);
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return NULL;
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}
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return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
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}
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static struct dma_async_tx_descriptor *pl08x_prep_dma_cyclic(
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struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
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size_t period_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
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struct pl08x_driver_data *pl08x = plchan->host;
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struct pl08x_txd *txd;
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int ret, tmp;
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dma_addr_t slave_addr;
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dev_dbg(&pl08x->adev->dev,
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"%s prepare cyclic transaction of %d/%d bytes %s %s\n",
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__func__, period_len, buf_len,
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direction == DMA_MEM_TO_DEV ? "to" : "from",
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plchan->name);
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txd = pl08x_init_txd(chan, direction, &slave_addr);
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if (!txd)
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return NULL;
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txd->cyclic = true;
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txd->cctl |= PL080_CONTROL_TC_IRQ_EN;
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for (tmp = 0; tmp < buf_len; tmp += period_len) {
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ret = pl08x_tx_add_sg(txd, direction, slave_addr,
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buf_addr + tmp, period_len);
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if (ret) {
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pl08x_release_mux(plchan);
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pl08x_free_txd(pl08x, txd);
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return NULL;
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}
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}
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@ -1761,7 +1846,9 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
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spin_lock(&plchan->vc.lock);
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tx = plchan->at;
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if (tx) {
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if (tx && tx->cyclic) {
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vchan_cyclic_callback(&tx->vd);
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} else if (tx) {
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plchan->at = NULL;
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/*
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* This descriptor is done, release its mux
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@ -1983,6 +2070,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
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/* Initialize slave engine */
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dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
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dma_cap_set(DMA_CYCLIC, pl08x->slave.cap_mask);
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pl08x->slave.dev = &adev->dev;
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pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
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pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
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@ -1990,6 +2078,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
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pl08x->slave.device_tx_status = pl08x_dma_tx_status;
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pl08x->slave.device_issue_pending = pl08x_issue_pending;
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pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
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pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic;
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pl08x->slave.device_control = pl08x_control;
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/* Get the platform data */
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