spi: ti-qspi: one only one interrupt handler
The here used irq and threaded irq handler is a complete non-sense. After the status register is read and the source disabled it schedules a thread (the irq thread) to read the status from the variable, invoke complete() and then renable the interrupt. Again: schedule a thread which invokes _only_ complete(). This patch removes this non-sense and we remain with one handler which invokes complete() if needed. The device remove path should now disable the interupts. This has been compile time tested. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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Родитель
633795b992
Коммит
3b3a80019f
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@ -41,9 +41,6 @@ struct ti_qspi_regs {
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struct ti_qspi {
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struct completion transfer_complete;
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/* IRQ synchronization */
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spinlock_t lock;
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/* list synchronization */
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struct mutex list_lock;
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@ -57,7 +54,6 @@ struct ti_qspi {
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u32 spi_max_frequency;
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u32 cmd;
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u32 dc;
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u32 stat;
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};
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#define QSPI_PID (0x0)
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@ -397,13 +393,12 @@ static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
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{
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struct ti_qspi *qspi = dev_id;
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u16 int_stat;
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u32 stat;
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irqreturn_t ret = IRQ_HANDLED;
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spin_lock(&qspi->lock);
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int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
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qspi->stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
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stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
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if (!int_stat) {
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dev_dbg(qspi->dev, "No IRQ triggered\n");
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@ -411,33 +406,12 @@ static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
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goto out;
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}
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ret = IRQ_WAKE_THREAD;
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ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
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ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
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QSPI_INTR_STATUS_ENABLED_CLEAR);
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out:
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spin_unlock(&qspi->lock);
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return ret;
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}
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static irqreturn_t ti_qspi_threaded_isr(int this_irq, void *dev_id)
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{
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struct ti_qspi *qspi = dev_id;
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unsigned long flags;
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spin_lock_irqsave(&qspi->lock, flags);
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if (qspi->stat & WC)
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if (stat & WC)
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complete(&qspi->transfer_complete);
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spin_unlock_irqrestore(&qspi->lock, flags);
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ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
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return IRQ_HANDLED;
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out:
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return ret;
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}
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static int ti_qspi_runtime_resume(struct device *dev)
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@ -499,7 +473,6 @@ static int ti_qspi_probe(struct platform_device *pdev)
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return irq;
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}
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spin_lock_init(&qspi->lock);
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mutex_init(&qspi->list_lock);
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qspi->base = devm_ioremap_resource(&pdev->dev, r);
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@ -508,8 +481,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
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goto free_master;
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}
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ret = devm_request_threaded_irq(&pdev->dev, irq, ti_qspi_isr,
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ti_qspi_threaded_isr, 0,
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ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
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dev_name(&pdev->dev), qspi);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
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@ -547,6 +519,7 @@ static int ti_qspi_remove(struct platform_device *pdev)
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{
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struct ti_qspi *qspi = platform_get_drvdata(pdev);
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ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
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spi_unregister_master(qspi->master);
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return 0;
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