da8xx-fb: cleanup LCDC configurations
Configure below LCDC configurations to optimal values, also have an option configure these optional parameters for platform. 1) AC bias configuration: Required only for passive panels 2) Dma_burst_size: 3) FIFO_DMA_DELAY: 4) FIFO threshold: Does not apply for da830 LCDC. Patch is verified for 16bpp and 24bpp configurations on da830, da850 and am335x EVMs. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Manjunathappa, Prakash
Tomi Valkeinen
Родитель
f772fabdf7
Коммит
3b43ad201d
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@ -518,29 +518,9 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
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}
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}
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static const struct display_panel disp_panel = {
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QVGA,
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16,
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16,
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COLOR_ACTIVE,
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};
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static struct lcd_ctrl_config lcd_cfg = {
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&disp_panel,
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.ac_bias = 255,
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.ac_bias_intrpt = 0,
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.dma_burst_sz = 16,
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.panel_shade = COLOR_ACTIVE,
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.bpp = 16,
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.fdd = 255,
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.tft_alt_mode = 0,
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.stn_565_mode = 0,
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.mono_8bit_mode = 0,
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.invert_line_clock = 1,
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.invert_frm_clock = 1,
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.sync_edge = 0,
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.sync_ctrl = 1,
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.raster_order = 0,
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.fifo_th = 6,
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};
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struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
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@ -226,7 +226,8 @@ static struct fb_videomode known_lcd_panels[] = {
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.lower_margin = 2,
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.hsync_len = 0,
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.vsync_len = 0,
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.sync = FB_SYNC_CLK_INVERT,
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.sync = FB_SYNC_CLK_INVERT |
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FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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},
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/* Sharp LK043T1DG01 */
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[1] = {
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@ -240,7 +241,7 @@ static struct fb_videomode known_lcd_panels[] = {
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.lower_margin = 2,
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.hsync_len = 41,
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.vsync_len = 10,
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.sync = 0,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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.flag = 0,
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},
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[2] = {
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@ -255,7 +256,7 @@ static struct fb_videomode known_lcd_panels[] = {
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.lower_margin = 10,
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.hsync_len = 10,
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.vsync_len = 10,
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.sync = 0,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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.flag = 0,
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},
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};
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@ -387,10 +388,9 @@ static int lcd_cfg_dma(int burst_size, int fifo_th)
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reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
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break;
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case 16:
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default:
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reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
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break;
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default:
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return -EINVAL;
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}
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reg |= (fifo_th << 8);
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@ -435,7 +435,8 @@ static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
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lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
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}
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static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
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static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
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struct fb_videomode *panel)
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{
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u32 reg;
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u32 reg_int;
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@ -444,7 +445,7 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
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LCD_MONO_8BIT_MODE |
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LCD_MONOCHROME_MODE);
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switch (cfg->p_disp_panel->panel_shade) {
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switch (cfg->panel_shade) {
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case MONOCHROME:
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reg |= LCD_MONOCHROME_MODE;
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if (cfg->mono_8bit_mode)
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@ -457,7 +458,9 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
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break;
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case COLOR_PASSIVE:
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if (cfg->stn_565_mode)
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/* AC bias applicable only for Pasive panels */
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lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
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if (cfg->bpp == 12 && cfg->stn_565_mode)
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reg |= LCD_STN_565_ENABLE;
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break;
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@ -478,22 +481,19 @@ static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
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reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
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if (cfg->sync_ctrl)
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reg |= LCD_SYNC_CTRL;
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else
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reg &= ~LCD_SYNC_CTRL;
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if (cfg->sync_edge)
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reg |= LCD_SYNC_EDGE;
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else
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reg &= ~LCD_SYNC_EDGE;
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if (cfg->invert_line_clock)
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if (panel->sync & FB_SYNC_HOR_HIGH_ACT)
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reg |= LCD_INVERT_LINE_CLOCK;
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else
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reg &= ~LCD_INVERT_LINE_CLOCK;
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if (cfg->invert_frm_clock)
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if (panel->sync & FB_SYNC_VERT_HIGH_ACT)
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reg |= LCD_INVERT_FRAME_CLOCK;
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else
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reg &= ~LCD_INVERT_FRAME_CLOCK;
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@ -738,9 +738,6 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
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if (ret < 0)
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return ret;
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/* Configure the AC bias properties. */
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lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
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/* Configure the vertical and horizontal sync properties. */
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lcd_cfg_vertical_sync(panel->lower_margin, panel->vsync_len,
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panel->upper_margin);
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@ -748,18 +745,12 @@ static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
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panel->left_margin);
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/* Configure for disply */
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ret = lcd_cfg_display(cfg);
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ret = lcd_cfg_display(cfg, panel);
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if (ret < 0)
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return ret;
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if (QVGA != cfg->p_disp_panel->panel_type)
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return -EINVAL;
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if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
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cfg->bpp >= cfg->p_disp_panel->min_bpp)
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bpp = cfg->bpp;
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else
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bpp = cfg->p_disp_panel->max_bpp;
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if (bpp == 12)
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bpp = 16;
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ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
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@ -1381,7 +1372,7 @@ static int __devinit fb_probe(struct platform_device *device)
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da8xx_fb_var.yres_virtual = lcdc_info->yres * LCD_NUM_BUFFERS;
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da8xx_fb_var.grayscale =
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lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
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lcd_cfg->panel_shade == MONOCHROME ? 1 : 0;
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da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
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da8xx_fb_var.hsync_len = lcdc_info->hsync_len;
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@ -12,10 +12,6 @@
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#ifndef DA8XX_FB_H
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#define DA8XX_FB_H
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enum panel_type {
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QVGA = 0
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};
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enum panel_shade {
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MONOCHROME = 0,
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COLOR_ACTIVE,
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@ -27,13 +23,6 @@ enum raster_load_mode {
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LOAD_PALETTE,
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};
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struct display_panel {
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enum panel_type panel_type; /* QVGA */
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int max_bpp;
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int min_bpp;
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enum panel_shade panel_shade;
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};
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struct da8xx_lcdc_platform_data {
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const char manu_name[10];
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void *controller_data;
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@ -42,7 +31,7 @@ struct da8xx_lcdc_platform_data {
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};
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struct lcd_ctrl_config {
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const struct display_panel *p_disp_panel;
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enum panel_shade panel_shade;
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/* AC Bias Pin Frequency */
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int ac_bias;
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@ -68,18 +57,9 @@ struct lcd_ctrl_config {
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/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
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unsigned char mono_8bit_mode;
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/* Invert line clock */
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unsigned char invert_line_clock;
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/* Invert frame clock */
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unsigned char invert_frm_clock;
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/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
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unsigned char sync_edge;
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/* Horizontal and Vertical Sync: Control: 0=ignore */
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unsigned char sync_ctrl;
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/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
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unsigned char raster_order;
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