Fix for arch/sh build regression with newer binutils, removal of SH5,
fixes for module exports, and misc cleanup. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABAgAGBQJe28l0AAoJELcQ+SIFb8HaKFMH/0T7tHfWit4+efmeDLhfrewd Fq9lLnEGmLy82AZqmd730gvD2ckbjUCm0ikKC79sCd14r3bIB1RCDKfXbY6rB3uI EDijbkzsjfOYG9ZAiDYTIbyrM2u2/1PzFiYTxHVDtPLbCPGfacbcfrDL+u143IXP ez/RHGLE6uYDvKi0Y0/VDKgMCW9bNlcEkL2/tKFVg2cipDi2Lfmi3Jss/id+5uOI N8XeZoyHjyWr7GeRZwN/hNPLDvLY//Uf5q6RB9VrTsN4Vrja7kjWMZkgsGkmGbNo f6BbLenq+KMfOSJrIzS3MgTRinoqRF5S518pkbGtgRQn0rZKfd6h85DG15RlPGk= =Ktnp -----END PGP SIGNATURE----- Merge tag 'sh-for-5.8' of git://git.libc.org/linux-sh Pull arch/sh updates from Rich Felker: "Fix for arch/sh build regression with newer binutils, removal of SH5, fixes for module exports, and misc cleanup" * tag 'sh-for-5.8' of git://git.libc.org/linux-sh: sh: remove sh5 support sh: add missing EXPORT_SYMBOL() for __delay sh: Convert ins[bwl]/outs[bwl] macros to inline functions sh: Convert iounmap() macros to inline functions sh: Add missing DECLARE_EXPORT() for __ashiftrt_r4_xx sh: configs: Cleanup old Kconfig IO scheduler options arch/sh: vmlinux.scr sh: Replace CONFIG_MTD_M25P80 with CONFIG_MTD_SPI_NOR in sh7757lcr_defconfig sh: sh4a: Bring back tmu3_device early device
This commit is contained in:
Linus Torvalds
Коммит
3b69e8b457
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@ -53,15 +53,6 @@ config SUPERH
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select HAVE_NMI
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select NEED_SG_DMA_LENGTH
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select ARCH_HAS_GIGANTIC_PAGE
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help
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The SuperH is a RISC processor targeted for use in embedded systems
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and consumer electronics; it was also used in the Sega Dreamcast
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gaming console. The SuperH port has a home page at
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<http://www.linux-sh.org/>.
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config SUPERH32
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def_bool "$(ARCH)" = "sh"
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select ARCH_32BIT_OFF_T
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select GUP_GET_PTE_LOW_HIGH if X2TLB
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select HAVE_KPROBES
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@ -79,19 +70,15 @@ config SUPERH32
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select ARCH_HIBERNATION_POSSIBLE if MMU
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select SPARSE_IRQ
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select HAVE_STACKPROTECTOR
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config SUPERH64
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def_bool "$(ARCH)" = "sh64"
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select HAVE_EXIT_THREAD
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select KALLSYMS
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help
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The SuperH is a RISC processor targeted for use in embedded systems
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and consumer electronics; it was also used in the Sega Dreamcast
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gaming console. The SuperH port has a home page at
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<http://www.linux-sh.org/>.
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config GENERIC_BUG
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def_bool y
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depends on BUG && SUPERH32
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config GENERIC_CSUM
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def_bool y
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depends on SUPERH64
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depends on BUG
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config GENERIC_HWEIGHT
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def_bool y
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@ -201,12 +188,6 @@ config CPU_SH4AL_DSP
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select CPU_SH4A
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select CPU_HAS_DSP
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config CPU_SH5
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bool
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select CPU_HAS_FPU
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select SYS_SUPPORTS_SH_TMU
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select SYS_SUPPORTS_HUGETLBFS if MMU
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config CPU_SHX2
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bool
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@ -226,8 +207,6 @@ config CPU_HAS_PMU
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default y
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bool
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if SUPERH32
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choice
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prompt "Processor sub-type selection"
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@ -516,27 +495,6 @@ config CPU_SUBTYPE_SH7366
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endchoice
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endif
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if SUPERH64
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choice
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prompt "Processor sub-type selection"
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# SH-5 Processor Support
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config CPU_SUBTYPE_SH5_101
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bool "Support SH5-101 processor"
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select CPU_SH5
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config CPU_SUBTYPE_SH5_103
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bool "Support SH5-103 processor"
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select CPU_SH5
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endchoice
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endif
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source "arch/sh/mm/Kconfig"
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source "arch/sh/Kconfig.cpu"
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@ -590,7 +548,7 @@ source "kernel/Kconfig.hz"
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config KEXEC
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bool "kexec system call (EXPERIMENTAL)"
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depends on SUPERH32 && MMU
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depends on MMU
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select KEXEC_CORE
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help
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kexec is a system call that implements the ability to shutdown your
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@ -608,7 +566,7 @@ config KEXEC
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config CRASH_DUMP
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bool "kernel crash dumps (EXPERIMENTAL)"
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depends on SUPERH32 && BROKEN_ON_SMP
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depends on BROKEN_ON_SMP
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help
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Generate crash dump after being started by kexec.
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This should be normally only set in special crash dump kernels
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@ -622,7 +580,7 @@ config CRASH_DUMP
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config KEXEC_JUMP
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bool "kexec jump (EXPERIMENTAL)"
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depends on SUPERH32 && KEXEC && HIBERNATION
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depends on KEXEC && HIBERNATION
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help
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Jump between original kernel and kexeced kernel and invoke
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code via KEXEC
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@ -699,7 +657,7 @@ config HOTPLUG_CPU
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config GUSA
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def_bool y
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depends on !SMP && SUPERH32
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depends on !SMP
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help
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This enables support for gUSA (general UserSpace Atomicity).
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This is the default implementation for both UP and non-ll/sc
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@ -13,7 +13,6 @@ config CPU_LITTLE_ENDIAN
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config CPU_BIG_ENDIAN
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bool "Big Endian"
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depends on !CPU_SH5
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endchoice
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@ -27,10 +26,6 @@ config SH_FPU
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This option must be set in order to enable the FPU.
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config SH64_FPU_DENORM_FLUSH
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bool "Flush floating point denorms to zero"
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depends on SH_FPU && SUPERH64
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config SH_FPU_EMU
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def_bool n
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prompt "FPU emulation support"
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@ -77,10 +72,6 @@ config SPECULATIVE_EXECUTION
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If unsure, say N.
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config SH64_ID2815_WORKAROUND
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bool "Include workaround for SH5-101 cut2 silicon defect ID2815"
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depends on CPU_SUBTYPE_SH5_101
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config CPU_HAS_INTEVT
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bool
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@ -5,7 +5,6 @@ config TRACE_IRQFLAGS_SUPPORT
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config SH_STANDARD_BIOS
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bool "Use LinuxSH standard BIOS"
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depends on SUPERH32
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help
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Say Y here if your target has the gdb-sh-stub
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package from www.m17n.org (or any conforming standard LinuxSH BIOS)
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@ -19,7 +18,7 @@ config SH_STANDARD_BIOS
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config STACK_DEBUG
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bool "Check for stack overflows"
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depends on DEBUG_KERNEL && SUPERH32
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depends on DEBUG_KERNEL
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help
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This option will cause messages to be printed if free stack space
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drops below a certain limit. Saying Y here will add overhead to
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@ -38,7 +37,7 @@ config 4KSTACKS
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config IRQSTACKS
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bool "Use separate kernel stacks when processing interrupts"
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depends on DEBUG_KERNEL && SUPERH32 && BROKEN
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depends on DEBUG_KERNEL && BROKEN
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help
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If you say Y here the kernel will use separate kernel stacks
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for handling hard and soft interrupts. This can help avoid
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@ -46,7 +45,7 @@ config IRQSTACKS
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config DUMP_CODE
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bool "Show disassembly of nearby code in register dumps"
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depends on DEBUG_KERNEL && SUPERH32
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depends on DEBUG_KERNEL
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default y if DEBUG_BUGVERBOSE
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default n
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help
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@ -59,7 +58,6 @@ config DUMP_CODE
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config DWARF_UNWINDER
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bool "Enable the DWARF unwinder for stacktraces"
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select FRAME_POINTER
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depends on SUPERH32
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default n
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help
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Enabling this option will make stacktraces more accurate, at
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@ -77,11 +75,6 @@ config SH_NO_BSS_INIT
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For all other cases, say N. If this option seems perplexing, or
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you aren't sure, say N.
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config SH64_SR_WATCH
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bool "Debug: set SR.WATCH to enable hardware watchpoints and trace"
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depends on SUPERH64
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config MCOUNT
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def_bool y
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depends on SUPERH32
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depends on STACK_DEBUG || FUNCTION_TRACER
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@ -11,7 +11,7 @@
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#
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ifneq ($(SUBARCH),$(ARCH))
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ifeq ($(CROSS_COMPILE),)
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CROSS_COMPILE := $(call cc-cross-prefix, $(UTS_MACHINE)-linux- $(UTS_MACHINE)-linux-gnu- $(UTS_MACHINE)-unknown-linux-gnu-)
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CROSS_COMPILE := $(call cc-cross-prefix, sh-linux- sh-linux-gnu- sh-unknown-linux-gnu-)
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endif
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endif
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@ -29,12 +29,9 @@ isa-$(CONFIG_CPU_SH3) := sh3
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isa-$(CONFIG_CPU_SH4) := sh4
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isa-$(CONFIG_CPU_SH4A) := sh4a
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isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al
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isa-$(CONFIG_CPU_SH5) := shmedia
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ifeq ($(CONFIG_SUPERH32),y)
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isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp
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isa-y := $(isa-y)-up
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endif
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cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,)
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cflags-$(CONFIG_CPU_J2) += $(call cc-option,-mj2,)
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@ -47,7 +44,6 @@ cflags-$(CONFIG_CPU_SH4) := $(call cc-option,-m4,) \
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cflags-$(CONFIG_CPU_SH4A) += $(call cc-option,-m4a,) \
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$(call cc-option,-m4a-nofpu,)
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cflags-$(CONFIG_CPU_SH4AL_DSP) += $(call cc-option,-m4al,)
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cflags-$(CONFIG_CPU_SH5) := $(call cc-option,-m5-32media-nofpu,)
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ifeq ($(cflags-y),)
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#
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@ -88,7 +84,7 @@ OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \
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-R .stab -R .stabstr -S
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# Give the various platforms the opportunity to set default image types
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defaultimage-$(CONFIG_SUPERH32) := zImage
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defaultimage-y := zImage
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defaultimage-$(CONFIG_SH_SH7785LCR) := uImage
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defaultimage-$(CONFIG_SH_RSK) := uImage
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defaultimage-$(CONFIG_SH_URQUELL) := uImage
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@ -107,31 +103,22 @@ KBUILD_IMAGE := $(boot)/$(defaultimage-y)
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# Choosing incompatible machines durings configuration will result in
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# error messages during linking.
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#
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ifdef CONFIG_SUPERH32
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UTS_MACHINE := sh
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BITS := 32
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LDFLAGS_vmlinux += -e _stext
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else
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UTS_MACHINE := sh64
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BITS := 64
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LDFLAGS_vmlinux += --defsym phys_stext=_stext-$(CONFIG_PAGE_OFFSET) \
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--defsym phys_stext_shmedia=phys_stext+1 \
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-e phys_stext_shmedia
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endif
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ifdef CONFIG_CPU_LITTLE_ENDIAN
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ld-bfd := elf32-$(UTS_MACHINE)-linux
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ld-bfd := elf32-sh-linux
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LDFLAGS_vmlinux += --defsym jiffies=jiffies_64 --oformat $(ld-bfd)
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KBUILD_LDFLAGS += -EL
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else
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ld-bfd := elf32-$(UTS_MACHINE)big-linux
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ld-bfd := elf32-shbig-linux
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LDFLAGS_vmlinux += --defsym jiffies=jiffies_64+4 --oformat $(ld-bfd)
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KBUILD_LDFLAGS += -EB
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endif
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export ld-bfd BITS
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export ld-bfd
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head-y := arch/sh/kernel/head_$(BITS).o
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head-y := arch/sh/kernel/head_32.o
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core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/
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core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
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@ -185,7 +172,6 @@ cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2
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cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3
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cpuincdir-$(CONFIG_CPU_SH4A) += cpu-sh4a
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cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4
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cpuincdir-$(CONFIG_CPU_SH5) += cpu-sh5
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cpuincdir-y += cpu-common # Must be last
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drivers-y += arch/sh/drivers/
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@ -206,8 +192,7 @@ ifeq ($(CONFIG_DWARF_UNWINDER),y)
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KBUILD_CFLAGS += -fasynchronous-unwind-tables
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endif
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libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y)
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libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y)
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libs-y := arch/sh/lib/ $(libs-y)
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BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.xz uImage.lzo \
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uImage.srec uImage.bin zImage vmlinux.bin vmlinux.srec \
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|
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@ -8,9 +8,9 @@
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targets := vmlinux vmlinux.bin vmlinux.bin.gz \
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vmlinux.bin.bz2 vmlinux.bin.lzma \
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vmlinux.bin.xz vmlinux.bin.lzo \
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head_$(BITS).o misc.o piggy.o
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head_32.o misc.o piggy.o
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OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/cache.o
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OBJECTS = $(obj)/head_32.o $(obj)/misc.o $(obj)/cache.o
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GCOV_PROFILE := n
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@ -39,15 +39,11 @@ LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext $(IMAGE_OFFSET) -e startup \
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#
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# Pull in the necessary libgcc bits from the in-kernel implementation.
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#
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lib1funcs-$(CONFIG_SUPERH32) := ashiftrt.S ashldi3.c ashrsi3.S ashlsi3.S \
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lshrsi3.S
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lib1funcs-obj := \
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lib1funcs-y := ashiftrt.S ashldi3.c ashrsi3.S ashlsi3.S lshrsi3.S
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lib1funcs-obj := \
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$(addsuffix .o, $(basename $(addprefix $(obj)/, $(lib1funcs-y))))
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lib1funcs-dir := $(srctree)/arch/$(SRCARCH)/lib
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ifeq ($(BITS),64)
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lib1funcs-dir := $(addsuffix $(BITS), $(lib1funcs-dir))
|
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endif
|
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|
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KBUILD_CFLAGS += -I$(lib1funcs-dir) -DDISABLE_BRANCH_PROFILING
|
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|
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|
|
|
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|
|
@ -116,11 +116,7 @@ void ftrace_stub(void)
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{
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}
|
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|
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#ifdef CONFIG_SUPERH64
|
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#define stackalign 8
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#else
|
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#define stackalign 4
|
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#endif
|
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|
||||
#define STACK_SIZE (4096)
|
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long __attribute__ ((aligned(stackalign))) user_stack[STACK_SIZE];
|
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|
|
@ -130,13 +126,9 @@ void decompress_kernel(void)
|
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{
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unsigned long output_addr;
|
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|
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#ifdef CONFIG_SUPERH64
|
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output_addr = (CONFIG_MEMORY_START + 0x2000);
|
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#else
|
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output_addr = __pa((unsigned long)&_text+PAGE_SIZE);
|
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#if defined(CONFIG_29BIT)
|
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output_addr |= P2SEG;
|
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#endif
|
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#endif
|
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|
||||
output = (unsigned char *)output_addr;
|
||||
|
|
|
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|
|
@ -1,6 +1,6 @@
|
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SECTIONS
|
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{
|
||||
.rodata..compressed : {
|
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.rodata..compressed : ALIGN(8) {
|
||||
input_len = .;
|
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LONG(input_data_end - input_data) input_data = .;
|
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*(.data)
|
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|
|
|
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|
|
@ -20,7 +20,8 @@ CONFIG_PROFILING=y
|
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CONFIG_MODULES=y
|
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CONFIG_MODULE_UNLOAD=y
|
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# CONFIG_BLK_DEV_BSG is not set
|
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CONFIG_CFQ_GROUP_IOSCHED=y
|
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CONFIG_IOSCHED_BFQ=y
|
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CONFIG_BFQ_GROUP_IOSCHED=y
|
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CONFIG_CPU_SUBTYPE_SH7786=y
|
||||
CONFIG_MEMORY_SIZE=0x10000000
|
||||
CONFIG_HUGETLB_PAGE_SIZE_1MB=y
|
||||
|
|
|
|||
|
|
@ -10,8 +10,6 @@ CONFIG_SLAB=y
|
|||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7724=y
|
||||
CONFIG_MEMORY_SIZE=0x08000000
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
|
|
|
|||
|
|
@ -14,8 +14,6 @@ CONFIG_MODULE_UNLOAD=y
|
|||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_MODULE_SRCVERSION_ALL=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7720=y
|
||||
CONFIG_MEMORY_START=0x0C000000
|
||||
CONFIG_MEMORY_SIZE=0x03F00000
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ CONFIG_MODULES=y
|
|||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7709=y
|
||||
CONFIG_MEMORY_START=0x0C000000
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
|
|
|
|||
|
|
@ -12,8 +12,6 @@ CONFIG_OPROFILE=m
|
|||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7780=y
|
||||
CONFIG_MEMORY_SIZE=0x08000000
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
|
|
|
|||
|
|
@ -15,8 +15,6 @@ CONFIG_KPROBES=y
|
|||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7785=y
|
||||
CONFIG_MEMORY_SIZE=0x08000000
|
||||
CONFIG_HUGETLB_PAGE_SIZE_1MB=y
|
||||
|
|
|
|||
|
|
@ -15,8 +15,6 @@ CONFIG_PROFILING=y
|
|||
CONFIG_OPROFILE=y
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7201=y
|
||||
CONFIG_MEMORY_SIZE=0x01000000
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
|
|
|
|||
|
|
@ -16,8 +16,6 @@ CONFIG_PROFILING=y
|
|||
CONFIG_OPROFILE=y
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7203=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_MEMORY_SIZE=0x01000000
|
||||
|
|
|
|||
|
|
@ -17,8 +17,6 @@ CONFIG_MMAP_ALLOW_UNINITIALIZED=y
|
|||
CONFIG_PROFILING=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7264=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
|
|
|
|||
|
|
@ -4,8 +4,6 @@ CONFIG_EMBEDDED=y
|
|||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_SWAP_IO_SPACE=y
|
||||
CONFIG_CPU_SUBTYPE_SH7269=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
|
|
|
|||
|
|
@ -39,7 +39,8 @@ CONFIG_OPROFILE=m
|
|||
CONFIG_KPROBES=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_CFQ_GROUP_IOSCHED=y
|
||||
CONFIG_IOSCHED_BFQ=y
|
||||
CONFIG_BFQ_GROUP_IOSCHED=y
|
||||
CONFIG_CPU_SUBTYPE_SH7786=y
|
||||
CONFIG_MEMORY_START=0x40000000
|
||||
CONFIG_MEMORY_SIZE=0x20000000
|
||||
|
|
|
|||
|
|
@ -28,8 +28,6 @@ CONFIG_OPROFILE=y
|
|||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7206=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@ CONFIG_MODULES=y
|
|||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7343=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_MEMORY_SIZE=0x01000000
|
||||
|
|
|
|||
|
|
@ -11,8 +11,6 @@ CONFIG_LOG_BUF_SHIFT=14
|
|||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
CONFIG_CPU_BIG_ENDIAN=y
|
||||
|
|
|
|||
|
|
@ -8,8 +8,6 @@ CONFIG_BLK_DEV_INITRD=y
|
|||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7705=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_MEMORY_SIZE=0x02000000
|
||||
|
|
|
|||
|
|
@ -12,8 +12,6 @@ CONFIG_KALLSYMS_ALL=y
|
|||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7712=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_MEMORY_SIZE=0x02000000
|
||||
|
|
|
|||
|
|
@ -12,8 +12,6 @@ CONFIG_KALLSYMS_ALL=y
|
|||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7721=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_MEMORY_SIZE=0x02000000
|
||||
|
|
|
|||
|
|
@ -8,8 +8,6 @@ CONFIG_PROFILING=y
|
|||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7722=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_NUMA=y
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@ CONFIG_LOG_BUF_SHIFT=14
|
|||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7780=y
|
||||
CONFIG_MEMORY_SIZE=0x08000000
|
||||
CONFIG_SH_7780_SOLUTION_ENGINE=y
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@ CONFIG_MODULES=y
|
|||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7710=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_MEMORY_SIZE=0x00800000
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ CONFIG_IPV6=y
|
|||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
|
|
|
|||
|
|
@ -12,8 +12,6 @@ CONFIG_LOG_BUF_SHIFT=14
|
|||
# CONFIG_SHMEM is not set
|
||||
CONFIG_SLOB=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7706=y
|
||||
CONFIG_MEMORY_START=0x0c000000
|
||||
CONFIG_MEMORY_SIZE=0x00800000
|
||||
|
|
|
|||
|
|
@ -8,8 +8,6 @@ CONFIG_PROFILING=y
|
|||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_CPU_SUBTYPE_SH7366=y
|
||||
CONFIG_MEMORY_SIZE=0x01f00000
|
||||
CONFIG_NUMA=y
|
||||
|
|
|
|||
|
|
@ -10,7 +10,6 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o
|
|||
obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7786) += pcie-sh7786.o ops-sh7786.o
|
||||
obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
|
||||
|
||||
obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
|
||||
pci-dreamcast.o
|
||||
|
|
|
|||
|
|
@ -1,65 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Support functions for the SH5 PCI hardware.
|
||||
*
|
||||
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
|
||||
* Copyright (C) 2003, 2004 Paul Mundt
|
||||
* Copyright (C) 2004 Richard Curnow
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/io.h>
|
||||
#include "pci-sh5.h"
|
||||
|
||||
static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
||||
int size, u32 *val)
|
||||
{
|
||||
SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
*val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3));
|
||||
break;
|
||||
case 2:
|
||||
*val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2));
|
||||
break;
|
||||
case 4:
|
||||
*val = SH5PCI_READ(PDR);
|
||||
break;
|
||||
}
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
||||
int size, u32 val)
|
||||
{
|
||||
SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
|
||||
break;
|
||||
case 2:
|
||||
SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
|
||||
break;
|
||||
case 4:
|
||||
SH5PCI_WRITE(PDR, val);
|
||||
break;
|
||||
}
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
struct pci_ops sh5_pci_ops = {
|
||||
.read = sh5pci_read,
|
||||
.write = sh5pci_write,
|
||||
};
|
||||
|
|
@ -1,217 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
|
||||
* Copyright (C) 2003, 2004 Paul Mundt
|
||||
* Copyright (C) 2004 Richard Curnow
|
||||
*
|
||||
* Support functions for the SH5 PCI hardware.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/irq.h>
|
||||
#include <cpu/irq.h>
|
||||
#include <asm/io.h>
|
||||
#include "pci-sh5.h"
|
||||
|
||||
unsigned long pcicr_virt;
|
||||
unsigned long PCI_IO_AREA;
|
||||
|
||||
/* Rounds a number UP to the nearest power of two. Used for
|
||||
* sizing the PCI window.
|
||||
*/
|
||||
static u32 __init r2p2(u32 num)
|
||||
{
|
||||
int i = 31;
|
||||
u32 tmp = num;
|
||||
|
||||
if (num == 0)
|
||||
return 0;
|
||||
|
||||
do {
|
||||
if (tmp & (1 << 31))
|
||||
break;
|
||||
i--;
|
||||
tmp <<= 1;
|
||||
} while (i >= 0);
|
||||
|
||||
tmp = 1 << i;
|
||||
/* If the original number isn't a power of 2, round it up */
|
||||
if (tmp != num)
|
||||
tmp <<= 1;
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static irqreturn_t pcish5_err_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct pt_regs *regs = get_irq_regs();
|
||||
unsigned pci_int, pci_air, pci_cir, pci_aint;
|
||||
|
||||
pci_int = SH5PCI_READ(INT);
|
||||
pci_cir = SH5PCI_READ(CIR);
|
||||
pci_air = SH5PCI_READ(AIR);
|
||||
|
||||
if (pci_int) {
|
||||
printk("PCI INTERRUPT (at %08llx)!\n", regs->pc);
|
||||
printk("PCI INT -> 0x%x\n", pci_int & 0xffff);
|
||||
printk("PCI AIR -> 0x%x\n", pci_air);
|
||||
printk("PCI CIR -> 0x%x\n", pci_cir);
|
||||
SH5PCI_WRITE(INT, ~0);
|
||||
}
|
||||
|
||||
pci_aint = SH5PCI_READ(AINT);
|
||||
if (pci_aint) {
|
||||
printk("PCI ARB INTERRUPT!\n");
|
||||
printk("PCI AINT -> 0x%x\n", pci_aint);
|
||||
printk("PCI AIR -> 0x%x\n", pci_air);
|
||||
printk("PCI CIR -> 0x%x\n", pci_cir);
|
||||
SH5PCI_WRITE(AINT, ~0);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
|
||||
{
|
||||
printk("SERR IRQ\n");
|
||||
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static struct resource sh5_pci_resources[2];
|
||||
|
||||
static struct pci_channel sh5pci_controller = {
|
||||
.pci_ops = &sh5_pci_ops,
|
||||
.resources = sh5_pci_resources,
|
||||
.nr_resources = ARRAY_SIZE(sh5_pci_resources),
|
||||
.mem_offset = 0x00000000,
|
||||
.io_offset = 0x00000000,
|
||||
};
|
||||
|
||||
static int __init sh5pci_init(void)
|
||||
{
|
||||
unsigned long memStart = __pa(memory_start);
|
||||
unsigned long memSize = __pa(memory_end) - memStart;
|
||||
u32 lsr0;
|
||||
u32 uval;
|
||||
|
||||
if (request_irq(IRQ_ERR, pcish5_err_irq,
|
||||
0, "PCI Error",NULL) < 0) {
|
||||
printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (request_irq(IRQ_SERR, pcish5_serr_irq,
|
||||
0, "PCI SERR interrupt", NULL) < 0) {
|
||||
printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pcicr_virt = (unsigned long)ioremap(SH5PCI_ICR_BASE, 1024);
|
||||
if (!pcicr_virt) {
|
||||
panic("Unable to remap PCICR\n");
|
||||
}
|
||||
|
||||
PCI_IO_AREA = (unsigned long)ioremap(SH5PCI_IO_BASE, 0x10000);
|
||||
if (!PCI_IO_AREA) {
|
||||
panic("Unable to remap PCIIO\n");
|
||||
}
|
||||
|
||||
/* Clear snoop registers */
|
||||
SH5PCI_WRITE(CSCR0, 0);
|
||||
SH5PCI_WRITE(CSCR1, 0);
|
||||
|
||||
/* Switch off interrupts */
|
||||
SH5PCI_WRITE(INTM, 0);
|
||||
SH5PCI_WRITE(AINTM, 0);
|
||||
SH5PCI_WRITE(PINTM, 0);
|
||||
|
||||
/* Set bus active, take it out of reset */
|
||||
uval = SH5PCI_READ(CR);
|
||||
|
||||
/* Set command Register */
|
||||
SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE |
|
||||
CR_PFCS | CR_BMAM);
|
||||
|
||||
uval=SH5PCI_READ(CR);
|
||||
|
||||
/* Allow it to be a master */
|
||||
/* NB - WE DISABLE I/O ACCESS to stop overlap */
|
||||
/* set WAIT bit to enable stepping, an attempt to improve stability */
|
||||
SH5PCI_WRITE_SHORT(CSR_CMD,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_WAIT);
|
||||
|
||||
/*
|
||||
** Set translation mapping memory in order to convert the address
|
||||
** used for the main bus, to the PCI internal address.
|
||||
*/
|
||||
SH5PCI_WRITE(MBR,0x40000000);
|
||||
|
||||
/* Always set the max size 512M */
|
||||
SH5PCI_WRITE(MBMR, PCISH5_MEM_SIZCONV(512*1024*1024));
|
||||
|
||||
/*
|
||||
** I/O addresses are mapped at internal PCI specific address
|
||||
** as is described into the configuration bridge table.
|
||||
** These are changed to 0, to allow cards that have legacy
|
||||
** io such as vga to function correctly. We set the SH5 IOBAR to
|
||||
** 256K, which is a bit big as we can only have 64K of address space
|
||||
*/
|
||||
|
||||
SH5PCI_WRITE(IOBR,0x0);
|
||||
|
||||
/* Set up a 256K window. Totally pointless waste of address space */
|
||||
SH5PCI_WRITE(IOBMR,0);
|
||||
|
||||
/* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec.
|
||||
* Ideally, we would want to map the I/O region somewhere, but it
|
||||
* is so big this is not that easy!
|
||||
*/
|
||||
SH5PCI_WRITE(CSR_IBAR0,~0);
|
||||
/* Set memory size value */
|
||||
memSize = memory_end - memory_start;
|
||||
|
||||
/* Now we set up the mbars so the PCI bus can see the memory of
|
||||
* the machine */
|
||||
if (memSize < (1024 * 1024)) {
|
||||
printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%lx?\n",
|
||||
memSize);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Set LSR 0 */
|
||||
lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 :
|
||||
((r2p2(memSize) - 0x100000) | 0x1);
|
||||
SH5PCI_WRITE(LSR0, lsr0);
|
||||
|
||||
/* Set MBAR 0 */
|
||||
SH5PCI_WRITE(CSR_MBAR0, memory_start);
|
||||
SH5PCI_WRITE(LAR0, memory_start);
|
||||
|
||||
SH5PCI_WRITE(CSR_MBAR1,0);
|
||||
SH5PCI_WRITE(LAR1,0);
|
||||
SH5PCI_WRITE(LSR1,0);
|
||||
|
||||
/* Enable the PCI interrupts on the device */
|
||||
SH5PCI_WRITE(INTM, ~0);
|
||||
SH5PCI_WRITE(AINTM, ~0);
|
||||
SH5PCI_WRITE(PINTM, ~0);
|
||||
|
||||
sh5_pci_resources[0].start = PCI_IO_AREA;
|
||||
sh5_pci_resources[0].end = PCI_IO_AREA + 0x10000;
|
||||
|
||||
sh5_pci_resources[1].start = memStart;
|
||||
sh5_pci_resources[1].end = memStart + memSize;
|
||||
|
||||
return register_pci_controller(&sh5pci_controller);
|
||||
}
|
||||
arch_initcall(sh5pci_init);
|
||||
|
|
@ -1,108 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
|
||||
*
|
||||
* Definitions for the SH5 PCI hardware.
|
||||
*/
|
||||
#ifndef __PCI_SH5_H
|
||||
#define __PCI_SH5_H
|
||||
|
||||
/* Product ID */
|
||||
#define PCISH5_PID 0x350d
|
||||
|
||||
/* vendor ID */
|
||||
#define PCISH5_VID 0x1054
|
||||
|
||||
/* Configuration types */
|
||||
#define ST_TYPE0 0x00 /* Configuration cycle type 0 */
|
||||
#define ST_TYPE1 0x01 /* Configuration cycle type 1 */
|
||||
|
||||
/* VCR data */
|
||||
#define PCISH5_VCR_STATUS 0x00
|
||||
#define PCISH5_VCR_VERSION 0x08
|
||||
|
||||
/*
|
||||
** ICR register offsets and bits
|
||||
*/
|
||||
#define PCISH5_ICR_CR 0x100 /* PCI control register values */
|
||||
#define CR_PBAM (1<<12)
|
||||
#define CR_PFCS (1<<11)
|
||||
#define CR_FTO (1<<10)
|
||||
#define CR_PFE (1<<9)
|
||||
#define CR_TBS (1<<8)
|
||||
#define CR_SPUE (1<<7)
|
||||
#define CR_BMAM (1<<6)
|
||||
#define CR_HOST (1<<5)
|
||||
#define CR_CLKEN (1<<4)
|
||||
#define CR_SOCS (1<<3)
|
||||
#define CR_IOCS (1<<2)
|
||||
#define CR_RSTCTL (1<<1)
|
||||
#define CR_CFINT (1<<0)
|
||||
#define CR_LOCK_MASK 0xa5000000
|
||||
|
||||
#define PCISH5_ICR_INT 0x114 /* Interrupt registert values */
|
||||
#define INT_MADIM (1<<2)
|
||||
|
||||
#define PCISH5_ICR_LSR0 0X104 /* Local space register values */
|
||||
#define PCISH5_ICR_LSR1 0X108 /* Local space register values */
|
||||
#define PCISH5_ICR_LAR0 0x10c /* Local address register values */
|
||||
#define PCISH5_ICR_LAR1 0x110 /* Local address register values */
|
||||
#define PCISH5_ICR_INTM 0x118 /* Interrupt mask register values */
|
||||
#define PCISH5_ICR_AIR 0x11c /* Interrupt error address information register values */
|
||||
#define PCISH5_ICR_CIR 0x120 /* Interrupt error command information register values */
|
||||
#define PCISH5_ICR_AINT 0x130 /* Interrupt error arbiter interrupt register values */
|
||||
#define PCISH5_ICR_AINTM 0x134 /* Interrupt error arbiter interrupt mask register values */
|
||||
#define PCISH5_ICR_BMIR 0x138 /* Interrupt error info register of bus master values */
|
||||
#define PCISH5_ICR_PAR 0x1c0 /* Pio address register values */
|
||||
#define PCISH5_ICR_MBR 0x1c4 /* Memory space bank register values */
|
||||
#define PCISH5_ICR_IOBR 0x1c8 /* I/O space bank register values */
|
||||
#define PCISH5_ICR_PINT 0x1cc /* power management interrupt register values */
|
||||
#define PCISH5_ICR_PINTM 0x1d0 /* power management interrupt mask register values */
|
||||
#define PCISH5_ICR_MBMR 0x1d8 /* memory space bank mask register values */
|
||||
#define PCISH5_ICR_IOBMR 0x1dc /* I/O space bank mask register values */
|
||||
#define PCISH5_ICR_CSCR0 0x210 /* PCI cache snoop control register 0 */
|
||||
#define PCISH5_ICR_CSCR1 0x214 /* PCI cache snoop control register 1 */
|
||||
#define PCISH5_ICR_PDR 0x220 /* Pio data register values */
|
||||
|
||||
/* These are configs space registers */
|
||||
#define PCISH5_ICR_CSR_VID 0x000 /* Vendor id */
|
||||
#define PCISH5_ICR_CSR_DID 0x002 /* Device id */
|
||||
#define PCISH5_ICR_CSR_CMD 0x004 /* Command register */
|
||||
#define PCISH5_ICR_CSR_STATUS 0x006 /* Stautus */
|
||||
#define PCISH5_ICR_CSR_IBAR0 0x010 /* I/O base address register */
|
||||
#define PCISH5_ICR_CSR_MBAR0 0x014 /* First Memory base address register */
|
||||
#define PCISH5_ICR_CSR_MBAR1 0x018 /* Second Memory base address register */
|
||||
|
||||
/* Base address of registers */
|
||||
#define SH5PCI_ICR_BASE (PHYS_PCI_BLOCK + 0x00040000)
|
||||
#define SH5PCI_IO_BASE (PHYS_PCI_BLOCK + 0x00800000)
|
||||
/* #define SH5PCI_VCR_BASE (P2SEG_PCICB_BLOCK + P2SEG) */
|
||||
|
||||
extern unsigned long pcicr_virt;
|
||||
/* Register selection macro */
|
||||
#define PCISH5_ICR_REG(x) ( pcicr_virt + (PCISH5_ICR_##x))
|
||||
/* #define PCISH5_VCR_REG(x) ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */
|
||||
|
||||
/* Write I/O functions */
|
||||
#define SH5PCI_WRITE(reg,val) __raw_writel((u32)(val),PCISH5_ICR_REG(reg))
|
||||
#define SH5PCI_WRITE_SHORT(reg,val) __raw_writew((u16)(val),PCISH5_ICR_REG(reg))
|
||||
#define SH5PCI_WRITE_BYTE(reg,val) __raw_writeb((u8)(val),PCISH5_ICR_REG(reg))
|
||||
|
||||
/* Read I/O functions */
|
||||
#define SH5PCI_READ(reg) __raw_readl(PCISH5_ICR_REG(reg))
|
||||
#define SH5PCI_READ_SHORT(reg) __raw_readw(PCISH5_ICR_REG(reg))
|
||||
#define SH5PCI_READ_BYTE(reg) __raw_readb(PCISH5_ICR_REG(reg))
|
||||
|
||||
/* Set PCI config bits */
|
||||
#define SET_CONFIG_BITS(bus,devfn,where) ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000)
|
||||
|
||||
/* Set PCI command register */
|
||||
#define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where)
|
||||
|
||||
/* Size converters */
|
||||
#define PCISH5_MEM_SIZCONV(x) (((x / 0x40000) - 1) << 18)
|
||||
#define PCISH5_IO_SIZCONV(x) (((x / 0x40000) - 1) << 18)
|
||||
|
||||
extern struct pci_ops sh5_pci_ops;
|
||||
|
||||
#endif /* __PCI_SH5_H */
|
||||
|
|
@ -6,7 +6,7 @@
|
|||
#ifndef __ASM_SH_BARRIER_H
|
||||
#define __ASM_SH_BARRIER_H
|
||||
|
||||
#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
|
||||
#if defined(CONFIG_CPU_SH4A)
|
||||
#include <asm/cache_insns.h>
|
||||
#endif
|
||||
|
||||
|
|
@ -24,7 +24,7 @@
|
|||
* Historically we have only done this type of barrier for the MMUCR, but
|
||||
* it's also necessary for the CCR, so we make it generic here instead.
|
||||
*/
|
||||
#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
|
||||
#if defined(CONFIG_CPU_SH4A)
|
||||
#define mb() __asm__ __volatile__ ("synco": : :"memory")
|
||||
#define rmb() mb()
|
||||
#define wmb() mb()
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
#include <asm-generic/bitops/non-atomic.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
static inline unsigned long ffz(unsigned long word)
|
||||
{
|
||||
unsigned long result;
|
||||
|
|
@ -60,31 +59,6 @@ static inline unsigned long __ffs(unsigned long word)
|
|||
: "t");
|
||||
return result;
|
||||
}
|
||||
#else
|
||||
static inline unsigned long ffz(unsigned long word)
|
||||
{
|
||||
unsigned long result, __d2, __d3;
|
||||
|
||||
__asm__("gettr tr0, %2\n\t"
|
||||
"pta $+32, tr0\n\t"
|
||||
"andi %1, 1, %3\n\t"
|
||||
"beq %3, r63, tr0\n\t"
|
||||
"pta $+4, tr0\n"
|
||||
"0:\n\t"
|
||||
"shlri.l %1, 1, %1\n\t"
|
||||
"addi %0, 1, %0\n\t"
|
||||
"andi %1, 1, %3\n\t"
|
||||
"beqi %3, 1, tr0\n"
|
||||
"1:\n\t"
|
||||
"ptabs %2, tr0\n\t"
|
||||
: "=r" (result), "=r" (word), "=r" (__d2), "=r" (__d3)
|
||||
: "0" (0L), "1" (word));
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#include <asm-generic/bitops/__ffs.h>
|
||||
#endif
|
||||
|
||||
#include <asm-generic/bitops/find.h>
|
||||
#include <asm-generic/bitops/ffs.h>
|
||||
|
|
|
|||
|
|
@ -1,11 +1,2 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_BL_BIT_H
|
||||
#define __ASM_SH_BL_BIT_H
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
# include <asm/bl_bit_32.h>
|
||||
#else
|
||||
# include <asm/bl_bit_64.h>
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SH_BL_BIT_H */
|
||||
#include <asm/bl_bit_32.h>
|
||||
|
|
|
|||
|
|
@ -1,37 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
* Copyright (C) 2004 Richard Curnow
|
||||
*/
|
||||
#ifndef __ASM_SH_BL_BIT_64_H
|
||||
#define __ASM_SH_BL_BIT_64_H
|
||||
|
||||
#include <asm/processor.h>
|
||||
|
||||
#define SR_BL_LL 0x0000000010000000LL
|
||||
|
||||
static inline void set_bl_bit(void)
|
||||
{
|
||||
unsigned long long __dummy0, __dummy1 = SR_BL_LL;
|
||||
|
||||
__asm__ __volatile__("getcon " __SR ", %0\n\t"
|
||||
"or %0, %1, %0\n\t"
|
||||
"putcon %0, " __SR "\n\t"
|
||||
: "=&r" (__dummy0)
|
||||
: "r" (__dummy1));
|
||||
|
||||
}
|
||||
|
||||
static inline void clear_bl_bit(void)
|
||||
{
|
||||
unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
|
||||
|
||||
__asm__ __volatile__("getcon " __SR ", %0\n\t"
|
||||
"and %0, %1, %0\n\t"
|
||||
"putcon %0, " __SR "\n\t"
|
||||
: "=&r" (__dummy0)
|
||||
: "r" (__dummy1));
|
||||
}
|
||||
|
||||
#endif /* __ASM_SH_BL_BIT_64_H */
|
||||
|
|
@ -53,10 +53,6 @@ static void __init check_bugs(void)
|
|||
*p++ = 's';
|
||||
*p++ = 'p';
|
||||
break;
|
||||
case CPU_FAMILY_SH5:
|
||||
*p++ = '6';
|
||||
*p++ = '4';
|
||||
break;
|
||||
case CPU_FAMILY_UNKNOWN:
|
||||
/*
|
||||
* Specifically use CPU_FAMILY_UNKNOWN rather than
|
||||
|
|
|
|||
|
|
@ -1,12 +1,2 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_CACHE_INSNS_H
|
||||
#define __ASM_SH_CACHE_INSNS_H
|
||||
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
# include <asm/cache_insns_32.h>
|
||||
#else
|
||||
# include <asm/cache_insns_64.h>
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SH_CACHE_INSNS_H */
|
||||
#include <asm/cache_insns_32.h>
|
||||
|
|
|
|||
|
|
@ -1,20 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
* Copyright (C) 2004 Richard Curnow
|
||||
*/
|
||||
#ifndef __ASM_SH_CACHE_INSNS_64_H
|
||||
#define __ASM_SH_CACHE_INSNS_64_H
|
||||
|
||||
#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
|
||||
#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
|
||||
#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
|
||||
#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr))
|
||||
|
||||
static inline reg_size_t register_align(void *val)
|
||||
{
|
||||
return (unsigned long long)(signed long long)(signed long)val;
|
||||
}
|
||||
|
||||
#endif /* __ASM_SH_CACHE_INSNS_64_H */
|
||||
|
|
@ -1,6 +1,2 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifdef CONFIG_SUPERH32
|
||||
# include <asm/checksum_32.h>
|
||||
#else
|
||||
# include <asm-generic/checksum.h>
|
||||
#endif
|
||||
#include <asm/checksum_32.h>
|
||||
|
|
|
|||
|
|
@ -133,28 +133,6 @@ typedef struct user_fpu_struct elf_fpregset_t;
|
|||
|
||||
#define ELF_PLATFORM (utsname()->machine)
|
||||
|
||||
#ifdef __SH5__
|
||||
#define ELF_PLAT_INIT(_r, load_addr) \
|
||||
do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
|
||||
_r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
|
||||
_r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
|
||||
_r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; _r->regs[15]=0; \
|
||||
_r->regs[16]=0; _r->regs[17]=0; _r->regs[18]=0; _r->regs[19]=0; \
|
||||
_r->regs[20]=0; _r->regs[21]=0; _r->regs[22]=0; _r->regs[23]=0; \
|
||||
_r->regs[24]=0; _r->regs[25]=0; _r->regs[26]=0; _r->regs[27]=0; \
|
||||
_r->regs[28]=0; _r->regs[29]=0; _r->regs[30]=0; _r->regs[31]=0; \
|
||||
_r->regs[32]=0; _r->regs[33]=0; _r->regs[34]=0; _r->regs[35]=0; \
|
||||
_r->regs[36]=0; _r->regs[37]=0; _r->regs[38]=0; _r->regs[39]=0; \
|
||||
_r->regs[40]=0; _r->regs[41]=0; _r->regs[42]=0; _r->regs[43]=0; \
|
||||
_r->regs[44]=0; _r->regs[45]=0; _r->regs[46]=0; _r->regs[47]=0; \
|
||||
_r->regs[48]=0; _r->regs[49]=0; _r->regs[50]=0; _r->regs[51]=0; \
|
||||
_r->regs[52]=0; _r->regs[53]=0; _r->regs[54]=0; _r->regs[55]=0; \
|
||||
_r->regs[56]=0; _r->regs[57]=0; _r->regs[58]=0; _r->regs[59]=0; \
|
||||
_r->regs[60]=0; _r->regs[61]=0; _r->regs[62]=0; \
|
||||
_r->tregs[0]=0; _r->tregs[1]=0; _r->tregs[2]=0; _r->tregs[3]=0; \
|
||||
_r->tregs[4]=0; _r->tregs[5]=0; _r->tregs[6]=0; _r->tregs[7]=0; \
|
||||
_r->sr = SR_FD | SR_MMU; } while (0)
|
||||
#else
|
||||
#define ELF_PLAT_INIT(_r, load_addr) \
|
||||
do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
|
||||
_r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
|
||||
|
|
@ -182,7 +160,6 @@ do { \
|
|||
_r->regs[14] = 0; \
|
||||
_r->sr = SR_FD; \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#define SET_PERSONALITY(ex) \
|
||||
set_personality(PER_LINUX_32BIT | (current->personality & (~PER_MASK)))
|
||||
|
|
|
|||
|
|
@ -4,8 +4,4 @@
|
|||
|
||||
#include <asm-generic/extable.h>
|
||||
|
||||
#if defined(CONFIG_SUPERH64) && defined(CONFIG_MMU)
|
||||
#define ARCH_HAS_SEARCH_EXTABLE
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -83,11 +83,7 @@ extern void __clear_fixmap(enum fixed_addresses idx, pgprot_t flags);
|
|||
* the start of the fixmap, and leave one page empty
|
||||
* at the top of mem..
|
||||
*/
|
||||
#ifdef CONFIG_SUPERH32
|
||||
#define FIXADDR_TOP (P4SEG - PAGE_SIZE)
|
||||
#else
|
||||
#define FIXADDR_TOP ((unsigned long)(-PAGE_SIZE))
|
||||
#endif
|
||||
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
|
||||
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
|
||||
|
||||
|
|
|
|||
|
|
@ -115,12 +115,8 @@ static inline void pfx##reads##bwlq(volatile void __iomem *mem, \
|
|||
__BUILD_MEMORY_STRING(__raw_, b, u8)
|
||||
__BUILD_MEMORY_STRING(__raw_, w, u16)
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
void __raw_writesl(void __iomem *addr, const void *data, int longlen);
|
||||
void __raw_readsl(const void __iomem *addr, void *data, int longlen);
|
||||
#else
|
||||
__BUILD_MEMORY_STRING(__raw_, l, u32)
|
||||
#endif
|
||||
|
||||
__BUILD_MEMORY_STRING(__raw_, q, u64)
|
||||
|
||||
|
|
@ -328,7 +324,7 @@ __ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
|
|||
#else
|
||||
#define __ioremap(offset, size, prot) ((void __iomem *)(offset))
|
||||
#define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset))
|
||||
#define iounmap(addr) do { } while (0)
|
||||
static inline void iounmap(void __iomem *addr) {}
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
|
||||
|
|
|
|||
|
|
@ -53,12 +53,34 @@ static inline void ioport_unmap(void __iomem *addr)
|
|||
#define outw_p(x, addr) outw((x), (addr))
|
||||
#define outl_p(x, addr) outl((x), (addr))
|
||||
|
||||
#define insb(a, b, c) BUG()
|
||||
#define insw(a, b, c) BUG()
|
||||
#define insl(a, b, c) BUG()
|
||||
static inline void insb(unsigned long port, void *dst, unsigned long count)
|
||||
{
|
||||
BUG();
|
||||
}
|
||||
|
||||
#define outsb(a, b, c) BUG()
|
||||
#define outsw(a, b, c) BUG()
|
||||
#define outsl(a, b, c) BUG()
|
||||
static inline void insw(unsigned long port, void *dst, unsigned long count)
|
||||
{
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline void insl(unsigned long port, void *dst, unsigned long count)
|
||||
{
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline void outsb(unsigned long port, const void *src, unsigned long count)
|
||||
{
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline void outsw(unsigned long port, const void *src, unsigned long count)
|
||||
{
|
||||
BUG();
|
||||
}
|
||||
|
||||
static inline void outsl(unsigned long port, const void *src, unsigned long count)
|
||||
{
|
||||
BUG();
|
||||
}
|
||||
|
||||
#endif /* __ASM_SH_IO_NOIOPORT_H */
|
||||
|
|
|
|||
|
|
@ -66,8 +66,5 @@ extern void irq_finish(unsigned int irq);
|
|||
#endif
|
||||
|
||||
#include <asm-generic/irq.h>
|
||||
#ifdef CONFIG_CPU_SH5
|
||||
#include <cpu/irq.h>
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SH_IRQ_H */
|
||||
|
|
|
|||
|
|
@ -48,11 +48,7 @@
|
|||
*/
|
||||
#define MMU_VPN_MASK 0xfffff000
|
||||
|
||||
#if defined(CONFIG_SUPERH32)
|
||||
#include <asm/mmu_context_32.h>
|
||||
#else
|
||||
#include <asm/mmu_context_64.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Get MMU context if needed.
|
||||
|
|
@ -74,14 +70,6 @@ static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
|
|||
*/
|
||||
local_flush_tlb_all();
|
||||
|
||||
#ifdef CONFIG_SUPERH64
|
||||
/*
|
||||
* The SH-5 cache uses the ASIDs, requiring both the I and D
|
||||
* cache to be flushed when the ASID is exhausted. Weak.
|
||||
*/
|
||||
flush_cache_all();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Fix version; Note that we avoid version #0
|
||||
* to distinguish NO_CONTEXT.
|
||||
|
|
|
|||
|
|
@ -1,75 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_MMU_CONTEXT_64_H
|
||||
#define __ASM_SH_MMU_CONTEXT_64_H
|
||||
|
||||
/*
|
||||
* sh64-specific mmu_context interface.
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003 - 2007 Paul Mundt
|
||||
*/
|
||||
#include <cpu/registers.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#define SR_ASID_MASK 0xffffffffff00ffffULL
|
||||
#define SR_ASID_SHIFT 16
|
||||
|
||||
/*
|
||||
* Destroy context related info for an mm_struct that is about
|
||||
* to be put to rest.
|
||||
*/
|
||||
static inline void destroy_context(struct mm_struct *mm)
|
||||
{
|
||||
/* Well, at least free TLB entries */
|
||||
flush_tlb_mm(mm);
|
||||
}
|
||||
|
||||
static inline unsigned long get_asid(void)
|
||||
{
|
||||
unsigned long long sr;
|
||||
|
||||
asm volatile ("getcon " __SR ", %0\n\t"
|
||||
: "=r" (sr));
|
||||
|
||||
sr = (sr >> SR_ASID_SHIFT) & MMU_CONTEXT_ASID_MASK;
|
||||
return (unsigned long) sr;
|
||||
}
|
||||
|
||||
/* Set ASID into SR */
|
||||
static inline void set_asid(unsigned long asid)
|
||||
{
|
||||
unsigned long long sr, pc;
|
||||
|
||||
asm volatile ("getcon " __SR ", %0" : "=r" (sr));
|
||||
|
||||
sr = (sr & SR_ASID_MASK) | (asid << SR_ASID_SHIFT);
|
||||
|
||||
/*
|
||||
* It is possible that this function may be inlined and so to avoid
|
||||
* the assembler reporting duplicate symbols we make use of the
|
||||
* gas trick of generating symbols using numerics and forward
|
||||
* reference.
|
||||
*/
|
||||
asm volatile ("movi 1, %1\n\t"
|
||||
"shlli %1, 28, %1\n\t"
|
||||
"or %0, %1, %1\n\t"
|
||||
"putcon %1, " __SR "\n\t"
|
||||
"putcon %0, " __SSR "\n\t"
|
||||
"movi 1f, %1\n\t"
|
||||
"ori %1, 1 , %1\n\t"
|
||||
"putcon %1, " __SPC "\n\t"
|
||||
"rte\n"
|
||||
"1:\n\t"
|
||||
: "=r" (sr), "=r" (pc) : "0" (sr));
|
||||
}
|
||||
|
||||
/* arch/sh/kernel/cpu/sh5/entry.S */
|
||||
extern unsigned long switch_and_save_asid(unsigned long new_asid);
|
||||
|
||||
/* No spare register to twiddle, so use a software cache */
|
||||
extern pgd_t *mmu_pdtp_cache;
|
||||
|
||||
#define set_TTB(pgd) (mmu_pdtp_cache = (pgd))
|
||||
#define get_TTB() (mmu_pdtp_cache)
|
||||
|
||||
#endif /* __ASM_SH_MMU_CONTEXT_64_H */
|
||||
|
|
@ -35,8 +35,6 @@
|
|||
#define HPAGE_SHIFT 22
|
||||
#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
|
||||
#define HPAGE_SHIFT 26
|
||||
#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB)
|
||||
#define HPAGE_SHIFT 29
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HUGETLB_PAGE
|
||||
|
|
@ -82,18 +80,12 @@ typedef struct { unsigned long long pgd; } pgd_t;
|
|||
((x).pte_low | ((unsigned long long)(x).pte_high << 32))
|
||||
#define __pte(x) \
|
||||
({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
|
||||
#elif defined(CONFIG_SUPERH32)
|
||||
#else
|
||||
typedef struct { unsigned long pte_low; } pte_t;
|
||||
typedef struct { unsigned long pgprot; } pgprot_t;
|
||||
typedef struct { unsigned long pgd; } pgd_t;
|
||||
#define pte_val(x) ((x).pte_low)
|
||||
#define __pte(x) ((pte_t) { (x) } )
|
||||
#else
|
||||
typedef struct { unsigned long long pte_low; } pte_t;
|
||||
typedef struct { unsigned long long pgprot; } pgprot_t;
|
||||
typedef struct { unsigned long pgd; } pgd_t;
|
||||
#define pte_val(x) ((x).pte_low)
|
||||
#define __pte(x) ((pte_t) { (x) } )
|
||||
#endif
|
||||
|
||||
#define pgd_val(x) ((x).pgd)
|
||||
|
|
@ -191,15 +183,4 @@ typedef struct page *pgtable_t;
|
|||
*/
|
||||
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
|
||||
|
||||
#ifdef CONFIG_SUPERH64
|
||||
/*
|
||||
* While BYTES_PER_WORD == 4 on the current sh64 ABI, GCC will still
|
||||
* happily generate {ld/st}.q pairs, requiring us to have 8-byte
|
||||
* alignment to avoid traps. The kmalloc alignment is guaranteed by
|
||||
* virtue of L1_CACHE_BYTES, requiring this to only be special cased
|
||||
* for slab caches.
|
||||
*/
|
||||
#define ARCH_SLAB_MINALIGN 8
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SH_PAGE_H */
|
||||
|
|
|
|||
|
|
@ -76,18 +76,10 @@ static inline unsigned long phys_addr_mask(void)
|
|||
#define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK)
|
||||
#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT)
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
#define VMALLOC_START (P3SEG)
|
||||
#else
|
||||
#define VMALLOC_START (0xf0000000)
|
||||
#endif
|
||||
#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
|
||||
|
||||
#if defined(CONFIG_SUPERH32)
|
||||
#include <asm/pgtable_32.h>
|
||||
#else
|
||||
#include <asm/pgtable_64.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
|
||||
|
|
@ -159,15 +151,6 @@ static inline bool pte_access_permitted(pte_t pte, bool write)
|
|||
prot |= _PAGE_EXT(_PAGE_EXT_KERN_WRITE | _PAGE_EXT_USER_WRITE);
|
||||
return __pte_access_permitted(pte, prot);
|
||||
}
|
||||
#elif defined(CONFIG_SUPERH64)
|
||||
static inline bool pte_access_permitted(pte_t pte, bool write)
|
||||
{
|
||||
u64 prot = _PAGE_PRESENT | _PAGE_USER | _PAGE_READ;
|
||||
|
||||
if (write)
|
||||
prot |= _PAGE_WRITE;
|
||||
return __pte_access_permitted(pte, prot);
|
||||
}
|
||||
#else
|
||||
static inline bool pte_access_permitted(pte_t pte, bool write)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,306 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_PGTABLE_64_H
|
||||
#define __ASM_SH_PGTABLE_64_H
|
||||
|
||||
/*
|
||||
* include/asm-sh/pgtable_64.h
|
||||
*
|
||||
* This file contains the functions and defines necessary to modify and use
|
||||
* the SuperH page table tree.
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003, 2004 Paul Mundt
|
||||
* Copyright (C) 2003, 2004 Richard Curnow
|
||||
*/
|
||||
#include <linux/threads.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
/*
|
||||
* Error outputs.
|
||||
*/
|
||||
#define pte_ERROR(e) \
|
||||
printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
|
||||
#define pgd_ERROR(e) \
|
||||
printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
|
||||
|
||||
/*
|
||||
* Table setting routines. Used within arch/mm only.
|
||||
*/
|
||||
#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
|
||||
|
||||
static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
|
||||
{
|
||||
unsigned long long x = ((unsigned long long) pteval.pte_low);
|
||||
unsigned long long *xp = (unsigned long long *) pteptr;
|
||||
/*
|
||||
* Sign-extend based on NPHYS.
|
||||
*/
|
||||
*(xp) = (x & NPHYS_SIGN) ? (x | NPHYS_MASK) : x;
|
||||
}
|
||||
#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
|
||||
|
||||
/*
|
||||
* PGD defines. Top level.
|
||||
*/
|
||||
|
||||
/* To find an entry in a generic PGD. */
|
||||
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
|
||||
#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
|
||||
|
||||
/* To find an entry in a kernel PGD. */
|
||||
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
|
||||
|
||||
#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
|
||||
/* #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) */
|
||||
|
||||
/*
|
||||
* PMD level access routines. Same notes as above.
|
||||
*/
|
||||
#define _PMD_EMPTY 0x0
|
||||
/* Either the PMD is empty or present, it's not paged out */
|
||||
#define pmd_present(pmd_entry) (pmd_val(pmd_entry) & _PAGE_PRESENT)
|
||||
#define pmd_clear(pmd_entry_p) (set_pmd((pmd_entry_p), __pmd(_PMD_EMPTY)))
|
||||
#define pmd_none(pmd_entry) (pmd_val((pmd_entry)) == _PMD_EMPTY)
|
||||
#define pmd_bad(pmd_entry) ((pmd_val(pmd_entry) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
|
||||
|
||||
#define pmd_page_vaddr(pmd_entry) \
|
||||
((unsigned long) __va(pmd_val(pmd_entry) & PAGE_MASK))
|
||||
|
||||
#define pmd_page(pmd) \
|
||||
(virt_to_page(pmd_val(pmd)))
|
||||
|
||||
/* PMD to PTE dereferencing */
|
||||
#define pte_index(address) \
|
||||
((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
|
||||
|
||||
#define __pte_offset(address) pte_index(address)
|
||||
|
||||
#define pte_offset_kernel(dir, addr) \
|
||||
((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr)))
|
||||
|
||||
#define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
|
||||
#define pte_unmap(pte) do { } while (0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/*
|
||||
* PTEL coherent flags.
|
||||
* See Chapter 17 ST50 CPU Core Volume 1, Architecture.
|
||||
*/
|
||||
/* The bits that are required in the SH-5 TLB are placed in the h/w-defined
|
||||
positions, to avoid expensive bit shuffling on every refill. The remaining
|
||||
bits are used for s/w purposes and masked out on each refill.
|
||||
|
||||
Note, the PTE slots are used to hold data of type swp_entry_t when a page is
|
||||
swapped out. Only the _PAGE_PRESENT flag is significant when the page is
|
||||
swapped out, and it must be placed so that it doesn't overlap either the
|
||||
type or offset fields of swp_entry_t. For x86, offset is at [31:8] and type
|
||||
at [6:1], with _PAGE_PRESENT at bit 0 for both pte_t and swp_entry_t. This
|
||||
scheme doesn't map to SH-5 because bit [0] controls cacheability. So bit
|
||||
[2] is used for _PAGE_PRESENT and the type field of swp_entry_t is split
|
||||
into 2 pieces. That is handled by SWP_ENTRY and SWP_TYPE below. */
|
||||
#define _PAGE_WT 0x001 /* CB0: if cacheable, 1->write-thru, 0->write-back */
|
||||
#define _PAGE_DEVICE 0x001 /* CB0: if uncacheable, 1->device (i.e. no write-combining or reordering at bus level) */
|
||||
#define _PAGE_CACHABLE 0x002 /* CB1: uncachable/cachable */
|
||||
#define _PAGE_PRESENT 0x004 /* software: page referenced */
|
||||
#define _PAGE_SIZE0 0x008 /* SZ0-bit : size of page */
|
||||
#define _PAGE_SIZE1 0x010 /* SZ1-bit : size of page */
|
||||
#define _PAGE_SHARED 0x020 /* software: reflects PTEH's SH */
|
||||
#define _PAGE_READ 0x040 /* PR0-bit : read access allowed */
|
||||
#define _PAGE_EXECUTE 0x080 /* PR1-bit : execute access allowed */
|
||||
#define _PAGE_WRITE 0x100 /* PR2-bit : write access allowed */
|
||||
#define _PAGE_USER 0x200 /* PR3-bit : user space access allowed */
|
||||
#define _PAGE_DIRTY 0x400 /* software: page accessed in write */
|
||||
#define _PAGE_ACCESSED 0x800 /* software: page referenced */
|
||||
|
||||
/* Wrapper for extended mode pgprot twiddling */
|
||||
#define _PAGE_EXT(x) ((unsigned long long)(x) << 32)
|
||||
|
||||
/*
|
||||
* We can use the sign-extended bits in the PTEL to get 32 bits of
|
||||
* software flags. This works for now because no implementations uses
|
||||
* anything above the PPN field.
|
||||
*/
|
||||
#define _PAGE_WIRED _PAGE_EXT(0x001) /* software: wire the tlb entry */
|
||||
#define _PAGE_SPECIAL _PAGE_EXT(0x002)
|
||||
|
||||
#define _PAGE_CLEAR_FLAGS (_PAGE_PRESENT | _PAGE_SHARED | \
|
||||
_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_WIRED)
|
||||
|
||||
/* Mask which drops software flags */
|
||||
#define _PAGE_FLAGS_HARDWARE_MASK (NEFF_MASK & ~(_PAGE_CLEAR_FLAGS))
|
||||
|
||||
/*
|
||||
* HugeTLB support
|
||||
*/
|
||||
#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
|
||||
#define _PAGE_SZHUGE (_PAGE_SIZE0)
|
||||
#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
|
||||
#define _PAGE_SZHUGE (_PAGE_SIZE1)
|
||||
#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512MB)
|
||||
#define _PAGE_SZHUGE (_PAGE_SIZE0 | _PAGE_SIZE1)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Stub out _PAGE_SZHUGE if we don't have a good definition for it,
|
||||
* to make pte_mkhuge() happy.
|
||||
*/
|
||||
#ifndef _PAGE_SZHUGE
|
||||
# define _PAGE_SZHUGE (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Default flags for a Kernel page.
|
||||
* This is fundametally also SHARED because the main use of this define
|
||||
* (other than for PGD/PMD entries) is for the VMALLOC pool which is
|
||||
* contextless.
|
||||
*
|
||||
* _PAGE_EXECUTE is required for modules
|
||||
*
|
||||
*/
|
||||
#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
|
||||
_PAGE_EXECUTE | \
|
||||
_PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_DIRTY | \
|
||||
_PAGE_SHARED)
|
||||
|
||||
/* Default flags for a User page */
|
||||
#define _PAGE_TABLE (_KERNPG_TABLE | _PAGE_USER)
|
||||
|
||||
#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
|
||||
_PAGE_SPECIAL)
|
||||
|
||||
/*
|
||||
* We have full permissions (Read/Write/Execute/Shared).
|
||||
*/
|
||||
#define _PAGE_COMMON (_PAGE_PRESENT | _PAGE_USER | \
|
||||
_PAGE_CACHABLE | _PAGE_ACCESSED)
|
||||
|
||||
#define PAGE_NONE __pgprot(_PAGE_CACHABLE | _PAGE_ACCESSED)
|
||||
#define PAGE_SHARED __pgprot(_PAGE_COMMON | _PAGE_READ | _PAGE_WRITE | \
|
||||
_PAGE_SHARED)
|
||||
#define PAGE_EXECREAD __pgprot(_PAGE_COMMON | _PAGE_READ | _PAGE_EXECUTE)
|
||||
|
||||
/*
|
||||
* We need to include PAGE_EXECUTE in PAGE_COPY because it is the default
|
||||
* protection mode for the stack.
|
||||
*/
|
||||
#define PAGE_COPY PAGE_EXECREAD
|
||||
|
||||
#define PAGE_READONLY __pgprot(_PAGE_COMMON | _PAGE_READ)
|
||||
#define PAGE_WRITEONLY __pgprot(_PAGE_COMMON | _PAGE_WRITE)
|
||||
#define PAGE_RWX __pgprot(_PAGE_COMMON | _PAGE_READ | \
|
||||
_PAGE_WRITE | _PAGE_EXECUTE)
|
||||
#define PAGE_KERNEL __pgprot(_KERNPG_TABLE)
|
||||
|
||||
#define PAGE_KERNEL_NOCACHE \
|
||||
__pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
|
||||
_PAGE_EXECUTE | _PAGE_ACCESSED | \
|
||||
_PAGE_DIRTY | _PAGE_SHARED)
|
||||
|
||||
/* Make it a device mapping for maximum safety (e.g. for mapping device
|
||||
registers into user-space via /dev/map). */
|
||||
#define pgprot_noncached(x) __pgprot(((x).pgprot & ~(_PAGE_CACHABLE)) | _PAGE_DEVICE)
|
||||
#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
|
||||
|
||||
/*
|
||||
* PTE level access routines.
|
||||
*
|
||||
* Note1:
|
||||
* It's the tree walk leaf. This is physical address to be stored.
|
||||
*
|
||||
* Note 2:
|
||||
* Regarding the choice of _PTE_EMPTY:
|
||||
|
||||
We must choose a bit pattern that cannot be valid, whether or not the page
|
||||
is present. bit[2]==1 => present, bit[2]==0 => swapped out. If swapped
|
||||
out, bits [31:8], [6:3], [1:0] are under swapper control, so only bit[7] is
|
||||
left for us to select. If we force bit[7]==0 when swapped out, we could use
|
||||
the combination bit[7,2]=2'b10 to indicate an empty PTE. Alternatively, if
|
||||
we force bit[7]==1 when swapped out, we can use all zeroes to indicate
|
||||
empty. This is convenient, because the page tables get cleared to zero
|
||||
when they are allocated.
|
||||
|
||||
*/
|
||||
#define _PTE_EMPTY 0x0
|
||||
#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
|
||||
#define pte_clear(mm,addr,xp) (set_pte_at(mm, addr, xp, __pte(_PTE_EMPTY)))
|
||||
#define pte_none(x) (pte_val(x) == _PTE_EMPTY)
|
||||
|
||||
/*
|
||||
* Some definitions to translate between mem_map, PTEs, and page
|
||||
* addresses:
|
||||
*/
|
||||
|
||||
/*
|
||||
* Given a PTE, return the index of the mem_map[] entry corresponding
|
||||
* to the page frame the PTE. Get the absolute physical address, make
|
||||
* a relative physical address and translate it to an index.
|
||||
*/
|
||||
#define pte_pagenr(x) (((unsigned long) (pte_val(x)) - \
|
||||
__MEMORY_START) >> PAGE_SHIFT)
|
||||
|
||||
/*
|
||||
* Given a PTE, return the "struct page *".
|
||||
*/
|
||||
#define pte_page(x) (mem_map + pte_pagenr(x))
|
||||
|
||||
/*
|
||||
* Return number of (down rounded) MB corresponding to x pages.
|
||||
*/
|
||||
#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
|
||||
|
||||
|
||||
/*
|
||||
* The following have defined behavior only work if pte_present() is true.
|
||||
*/
|
||||
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
|
||||
static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
|
||||
static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
|
||||
static inline int pte_special(pte_t pte){ return pte_val(pte) & _PAGE_SPECIAL; }
|
||||
|
||||
static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_WRITE)); return pte; }
|
||||
static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
|
||||
static inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; }
|
||||
static inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_WRITE)); return pte; }
|
||||
static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
|
||||
static inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
|
||||
static inline pte_t pte_mkhuge(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
|
||||
static inline pte_t pte_mkspecial(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SPECIAL)); return pte; }
|
||||
|
||||
/*
|
||||
* Conversion functions: convert a page and protection to a page entry.
|
||||
*
|
||||
* extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
|
||||
*/
|
||||
#define mk_pte(page,pgprot) \
|
||||
({ \
|
||||
pte_t __pte; \
|
||||
\
|
||||
set_pte(&__pte, __pte((((page)-mem_map) << PAGE_SHIFT) | \
|
||||
__MEMORY_START | pgprot_val((pgprot)))); \
|
||||
__pte; \
|
||||
})
|
||||
|
||||
/*
|
||||
* This takes a (absolute) physical page address that is used
|
||||
* by the remapping functions
|
||||
*/
|
||||
#define mk_pte_phys(physpage, pgprot) \
|
||||
({ pte_t __pte; set_pte(&__pte, __pte(physpage | pgprot_val(pgprot))); __pte; })
|
||||
|
||||
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||||
{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; }
|
||||
|
||||
/* Encode and decode a swap entry */
|
||||
#define __swp_type(x) (((x).val & 3) + (((x).val >> 1) & 0x3c))
|
||||
#define __swp_offset(x) ((x).val >> 8)
|
||||
#define __swp_entry(type, offset) ((swp_entry_t) { ((offset << 8) + ((type & 0x3c) << 1) + (type & 3)) })
|
||||
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
|
||||
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
|
||||
#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
|
||||
|
||||
#endif /* __ASM_SH_PGTABLE_64_H */
|
||||
|
|
@ -1,6 +1,2 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
# ifdef CONFIG_SUPERH32
|
||||
# include <asm/posix_types_32.h>
|
||||
# else
|
||||
# include <asm/posix_types_64.h>
|
||||
# endif
|
||||
#include <asm/posix_types_32.h>
|
||||
|
|
|
|||
|
|
@ -39,9 +39,6 @@ enum cpu_type {
|
|||
/* SH4AL-DSP types */
|
||||
CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,
|
||||
|
||||
/* SH-5 types */
|
||||
CPU_SH5_101, CPU_SH5_103,
|
||||
|
||||
/* Unknown subtype */
|
||||
CPU_SH_NONE
|
||||
};
|
||||
|
|
@ -53,7 +50,6 @@ enum cpu_family {
|
|||
CPU_FAMILY_SH4,
|
||||
CPU_FAMILY_SH4A,
|
||||
CPU_FAMILY_SH4AL_DSP,
|
||||
CPU_FAMILY_SH5,
|
||||
CPU_FAMILY_UNKNOWN,
|
||||
};
|
||||
|
||||
|
|
@ -167,18 +163,12 @@ int vsyscall_init(void);
|
|||
*/
|
||||
#ifdef CONFIG_CPU_SH2A
|
||||
extern unsigned int instruction_size(unsigned int insn);
|
||||
#elif defined(CONFIG_SUPERH32)
|
||||
#define instruction_size(insn) (2)
|
||||
#else
|
||||
#define instruction_size(insn) (4)
|
||||
#define instruction_size(insn) (2)
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
# include <asm/processor_32.h>
|
||||
#else
|
||||
# include <asm/processor_64.h>
|
||||
#endif
|
||||
#include <asm/processor_32.h>
|
||||
|
||||
#endif /* __ASM_SH_PROCESSOR_H */
|
||||
|
|
|
|||
|
|
@ -1,212 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_PROCESSOR_64_H
|
||||
#define __ASM_SH_PROCESSOR_64_H
|
||||
|
||||
/*
|
||||
* include/asm-sh/processor_64.h
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
* Copyright (C) 2004 Richard Curnow
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/types.h>
|
||||
#include <cpu/registers.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* User space process size: 2GB - 4k.
|
||||
*/
|
||||
#define TASK_SIZE 0x7ffff000UL
|
||||
|
||||
#define STACK_TOP TASK_SIZE
|
||||
#define STACK_TOP_MAX STACK_TOP
|
||||
|
||||
/* This decides where the kernel will search for a free chunk of vm
|
||||
* space during mmap's.
|
||||
*/
|
||||
#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
|
||||
|
||||
/*
|
||||
* Bit of SR register
|
||||
*
|
||||
* FD-bit:
|
||||
* When it's set, it means the processor doesn't have right to use FPU,
|
||||
* and it results exception when the floating operation is executed.
|
||||
*
|
||||
* IMASK-bit:
|
||||
* Interrupt level mask
|
||||
*
|
||||
* STEP-bit:
|
||||
* Single step bit
|
||||
*
|
||||
*/
|
||||
#if defined(CONFIG_SH64_SR_WATCH)
|
||||
#define SR_MMU 0x84000000
|
||||
#else
|
||||
#define SR_MMU 0x80000000
|
||||
#endif
|
||||
|
||||
#define SR_IMASK 0x000000f0
|
||||
#define SR_FD 0x00008000
|
||||
#define SR_SSTEP 0x08000000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* FPU structure and data : require 8-byte alignment as we need to access it
|
||||
with fld.p, fst.p
|
||||
*/
|
||||
|
||||
struct sh_fpu_hard_struct {
|
||||
unsigned long fp_regs[64];
|
||||
unsigned int fpscr;
|
||||
/* long status; * software status information */
|
||||
};
|
||||
|
||||
/* Dummy fpu emulator */
|
||||
struct sh_fpu_soft_struct {
|
||||
unsigned long fp_regs[64];
|
||||
unsigned int fpscr;
|
||||
unsigned char lookahead;
|
||||
unsigned long entry_pc;
|
||||
};
|
||||
|
||||
union thread_xstate {
|
||||
struct sh_fpu_hard_struct hardfpu;
|
||||
struct sh_fpu_soft_struct softfpu;
|
||||
/*
|
||||
* The structure definitions only produce 32 bit alignment, yet we need
|
||||
* to access them using 64 bit load/store as well.
|
||||
*/
|
||||
unsigned long long alignment_dummy;
|
||||
};
|
||||
|
||||
struct thread_struct {
|
||||
unsigned long sp;
|
||||
unsigned long pc;
|
||||
|
||||
/* Various thread flags, see SH_THREAD_xxx */
|
||||
unsigned long flags;
|
||||
|
||||
/* This stores the address of the pt_regs built during a context
|
||||
switch, or of the register save area built for a kernel mode
|
||||
exception. It is used for backtracing the stack of a sleeping task
|
||||
or one that traps in kernel mode. */
|
||||
struct pt_regs *kregs;
|
||||
/* This stores the address of the pt_regs constructed on entry from
|
||||
user mode. It is a fixed value over the lifetime of a process, or
|
||||
NULL for a kernel thread. */
|
||||
struct pt_regs *uregs;
|
||||
|
||||
unsigned long address;
|
||||
/* Hardware debugging registers may come here */
|
||||
|
||||
/* floating point info */
|
||||
union thread_xstate *xstate;
|
||||
|
||||
/*
|
||||
* fpu_counter contains the number of consecutive context switches
|
||||
* that the FPU is used. If this is over a threshold, the lazy fpu
|
||||
* saving becomes unlazy to save the trap. This is an unsigned char
|
||||
* so that after 256 times the counter wraps and the behavior turns
|
||||
* lazy again; this to deal with bursty apps that only use FPU for
|
||||
* a short time
|
||||
*/
|
||||
unsigned char fpu_counter;
|
||||
};
|
||||
|
||||
#define INIT_MMAP \
|
||||
{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
|
||||
|
||||
#define INIT_THREAD { \
|
||||
.sp = sizeof(init_stack) + \
|
||||
(long) &init_stack, \
|
||||
.pc = 0, \
|
||||
.kregs = &fake_swapper_regs, \
|
||||
.uregs = NULL, \
|
||||
.address = 0, \
|
||||
.flags = 0, \
|
||||
}
|
||||
|
||||
/*
|
||||
* Do necessary setup to start up a newly executed thread.
|
||||
*/
|
||||
#define SR_USER (SR_MMU | SR_FD)
|
||||
|
||||
#define start_thread(_regs, new_pc, new_sp) \
|
||||
_regs->sr = SR_USER; /* User mode. */ \
|
||||
_regs->pc = new_pc - 4; /* Compensate syscall exit */ \
|
||||
_regs->pc |= 1; /* Set SHmedia ! */ \
|
||||
_regs->regs[18] = 0; \
|
||||
_regs->regs[15] = new_sp
|
||||
|
||||
/* Forward declaration, a strange C thing */
|
||||
struct task_struct;
|
||||
struct mm_struct;
|
||||
|
||||
/* Free all resources held by a thread. */
|
||||
extern void release_thread(struct task_struct *);
|
||||
|
||||
/*
|
||||
* FPU lazy state save handling.
|
||||
*/
|
||||
|
||||
static inline void disable_fpu(void)
|
||||
{
|
||||
unsigned long long __dummy;
|
||||
|
||||
/* Set FD flag in SR */
|
||||
__asm__ __volatile__("getcon " __SR ", %0\n\t"
|
||||
"or %0, %1, %0\n\t"
|
||||
"putcon %0, " __SR "\n\t"
|
||||
: "=&r" (__dummy)
|
||||
: "r" (SR_FD));
|
||||
}
|
||||
|
||||
static inline void enable_fpu(void)
|
||||
{
|
||||
unsigned long long __dummy;
|
||||
|
||||
/* Clear out FD flag in SR */
|
||||
__asm__ __volatile__("getcon " __SR ", %0\n\t"
|
||||
"and %0, %1, %0\n\t"
|
||||
"putcon %0, " __SR "\n\t"
|
||||
: "=&r" (__dummy)
|
||||
: "r" (~SR_FD));
|
||||
}
|
||||
|
||||
/* Round to nearest, no exceptions on inexact, overflow, underflow,
|
||||
zero-divide, invalid. Configure option for whether to flush denorms to
|
||||
zero, or except if a denorm is encountered. */
|
||||
#if defined(CONFIG_SH64_FPU_DENORM_FLUSH)
|
||||
#define FPSCR_INIT 0x00040000
|
||||
#else
|
||||
#define FPSCR_INIT 0x00000000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SH_FPU
|
||||
/* Initialise the FP state of a task */
|
||||
void fpinit(struct sh_fpu_hard_struct *fpregs);
|
||||
#else
|
||||
#define fpinit(fpregs) do { } while (0)
|
||||
#endif
|
||||
|
||||
extern struct task_struct *last_task_used_math;
|
||||
|
||||
/*
|
||||
* Return saved PC of a blocked thread.
|
||||
*/
|
||||
#define thread_saved_pc(tsk) (tsk->thread.pc)
|
||||
|
||||
extern unsigned long get_wchan(struct task_struct *p);
|
||||
|
||||
#define KSTK_EIP(tsk) ((tsk)->thread.pc)
|
||||
#define KSTK_ESP(tsk) ((tsk)->thread.sp)
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_SH_PROCESSOR_64_H */
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_PTRACE_64_H
|
||||
#define __ASM_SH_PTRACE_64_H
|
||||
|
||||
#include <uapi/asm/ptrace_64.h>
|
||||
|
||||
|
||||
#define MAX_REG_OFFSET offsetof(struct pt_regs, tregs[7])
|
||||
static inline long regs_return_value(struct pt_regs *regs)
|
||||
{
|
||||
return regs->regs[3];
|
||||
}
|
||||
|
||||
#endif /* __ASM_SH_PTRACE_64_H */
|
||||
|
|
@ -1,6 +1,2 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifdef CONFIG_SUPERH32
|
||||
# include <asm/string_32.h>
|
||||
#else
|
||||
# include <asm/string_64.h>
|
||||
#endif
|
||||
#include <asm/string_32.h>
|
||||
|
|
|
|||
|
|
@ -1,21 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_STRING_64_H
|
||||
#define __ASM_SH_STRING_64_H
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#define __HAVE_ARCH_MEMSET
|
||||
extern void *memset(void *__s, int __c, size_t __count);
|
||||
|
||||
#define __HAVE_ARCH_MEMCPY
|
||||
extern void *memcpy(void *dest, const void *src, size_t count);
|
||||
|
||||
#define __HAVE_ARCH_STRLEN
|
||||
extern size_t strlen(const char *);
|
||||
|
||||
#define __HAVE_ARCH_STRCPY
|
||||
extern char *strcpy(char *__dest, const char *__src);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ASM_SH_STRING_64_H */
|
||||
|
|
@ -4,13 +4,4 @@
|
|||
* Copyright (C) 2003 Paul Mundt
|
||||
* Copyright (C) 2004 Richard Curnow
|
||||
*/
|
||||
#ifndef __ASM_SH_SWITCH_TO_H
|
||||
#define __ASM_SH_SWITCH_TO_H
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
# include <asm/switch_to_32.h>
|
||||
#else
|
||||
# include <asm/switch_to_64.h>
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SH_SWITCH_TO_H */
|
||||
#include <asm/switch_to_32.h>
|
||||
|
|
|
|||
|
|
@ -1,32 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
* Copyright (C) 2004 Richard Curnow
|
||||
*/
|
||||
#ifndef __ASM_SH_SWITCH_TO_64_H
|
||||
#define __ASM_SH_SWITCH_TO_64_H
|
||||
|
||||
struct thread_struct;
|
||||
struct task_struct;
|
||||
|
||||
/*
|
||||
* switch_to() should switch tasks to task nr n, first
|
||||
*/
|
||||
struct task_struct *sh64_switch_to(struct task_struct *prev,
|
||||
struct thread_struct *prev_thread,
|
||||
struct task_struct *next,
|
||||
struct thread_struct *next_thread);
|
||||
|
||||
#define switch_to(prev,next,last) \
|
||||
do { \
|
||||
if (last_task_used_math != next) { \
|
||||
struct pt_regs *regs = next->thread.uregs; \
|
||||
if (regs) regs->sr |= SR_FD; \
|
||||
} \
|
||||
last = sh64_switch_to(prev, &prev->thread, next, \
|
||||
&next->thread); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#endif /* __ASM_SH_SWITCH_TO_64_H */
|
||||
|
|
@ -4,10 +4,6 @@
|
|||
|
||||
extern const unsigned long sys_call_table[];
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
# include <asm/syscall_32.h>
|
||||
#else
|
||||
# include <asm/syscall_64.h>
|
||||
#endif
|
||||
#include <asm/syscall_32.h>
|
||||
|
||||
#endif /* __ASM_SH_SYSCALL_H */
|
||||
|
|
|
|||
|
|
@ -1,75 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_SYSCALL_64_H
|
||||
#define __ASM_SH_SYSCALL_64_H
|
||||
|
||||
#include <uapi/linux/audit.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/sched.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
/* The system call number is given by the user in R9 */
|
||||
static inline long syscall_get_nr(struct task_struct *task,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
return (regs->syscall_nr >= 0) ? regs->regs[9] : -1L;
|
||||
}
|
||||
|
||||
static inline void syscall_rollback(struct task_struct *task,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
/*
|
||||
* XXX: This needs some thought. On SH we don't
|
||||
* save away the original R9 value anywhere.
|
||||
*/
|
||||
}
|
||||
|
||||
static inline long syscall_get_error(struct task_struct *task,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
return IS_ERR_VALUE(regs->regs[9]) ? regs->regs[9] : 0;
|
||||
}
|
||||
|
||||
static inline long syscall_get_return_value(struct task_struct *task,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
return regs->regs[9];
|
||||
}
|
||||
|
||||
static inline void syscall_set_return_value(struct task_struct *task,
|
||||
struct pt_regs *regs,
|
||||
int error, long val)
|
||||
{
|
||||
if (error)
|
||||
regs->regs[9] = -error;
|
||||
else
|
||||
regs->regs[9] = val;
|
||||
}
|
||||
|
||||
static inline void syscall_get_arguments(struct task_struct *task,
|
||||
struct pt_regs *regs,
|
||||
unsigned long *args)
|
||||
{
|
||||
memcpy(args, ®s->regs[2], 6 * sizeof(args[0]));
|
||||
}
|
||||
|
||||
static inline void syscall_set_arguments(struct task_struct *task,
|
||||
struct pt_regs *regs,
|
||||
const unsigned long *args)
|
||||
{
|
||||
memcpy(®s->regs[2], args, 6 * sizeof(args[0]));
|
||||
}
|
||||
|
||||
static inline int syscall_get_arch(struct task_struct *task)
|
||||
{
|
||||
int arch = AUDIT_ARCH_SH;
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
arch |= __AUDIT_ARCH_64BIT;
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
arch |= __AUDIT_ARCH_LE;
|
||||
#endif
|
||||
|
||||
return arch;
|
||||
}
|
||||
#endif /* __ASM_SH_SYSCALL_64_H */
|
||||
|
|
@ -2,8 +2,6 @@
|
|||
#ifndef __ASM_SH_SYSCALLS_H
|
||||
#define __ASM_SH_SYSCALLS_H
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
asmlinkage int old_mmap(unsigned long addr, unsigned long len,
|
||||
unsigned long prot, unsigned long flags,
|
||||
int fd, unsigned long off);
|
||||
|
|
@ -11,11 +9,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
|
|||
unsigned long prot, unsigned long flags,
|
||||
unsigned long fd, unsigned long pgoff);
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
# include <asm/syscalls_32.h>
|
||||
#else
|
||||
# include <asm/syscalls_64.h>
|
||||
#endif
|
||||
#include <asm/syscalls_32.h>
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASM_SH_SYSCALLS_H */
|
||||
|
|
|
|||
|
|
@ -1,18 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_SYSCALLS_64_H
|
||||
#define __ASM_SH_SYSCALLS_64_H
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct pt_regs;
|
||||
|
||||
/* Misc syscall related bits */
|
||||
asmlinkage long long do_syscall_trace_enter(struct pt_regs *regs);
|
||||
asmlinkage void do_syscall_trace_leave(struct pt_regs *regs);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASM_SH_SYSCALLS_64_H */
|
||||
|
|
@ -70,9 +70,7 @@ register unsigned long current_stack_pointer asm("r15") __used;
|
|||
static inline struct thread_info *current_thread_info(void)
|
||||
{
|
||||
struct thread_info *ti;
|
||||
#if defined(CONFIG_SUPERH64)
|
||||
__asm__ __volatile__ ("getcon cr17, %0" : "=r" (ti));
|
||||
#elif defined(CONFIG_CPU_HAS_SR_RB)
|
||||
#if defined(CONFIG_CPU_HAS_SR_RB)
|
||||
__asm__ __volatile__ ("stc r7_bank, %0" : "=r" (ti));
|
||||
#else
|
||||
unsigned long __dummy;
|
||||
|
|
|
|||
|
|
@ -2,10 +2,6 @@
|
|||
#ifndef __ASM_SH_TLB_H
|
||||
#define __ASM_SH_TLB_H
|
||||
|
||||
#ifdef CONFIG_SUPERH64
|
||||
# include <asm/tlb_64.h>
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <linux/pagemap.h>
|
||||
|
||||
|
|
@ -14,7 +10,7 @@
|
|||
|
||||
#include <asm-generic/tlb.h>
|
||||
|
||||
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SUPERH64)
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
extern void tlb_wire_entry(struct vm_area_struct *, unsigned long, pte_t);
|
||||
extern void tlb_unwire_entry(void);
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -1,68 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* include/asm-sh/tlb_64.h
|
||||
*
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
*/
|
||||
#ifndef __ASM_SH_TLB_64_H
|
||||
#define __ASM_SH_TLB_64_H
|
||||
|
||||
/* ITLB defines */
|
||||
#define ITLB_FIXED 0x00000000 /* First fixed ITLB, see head.S */
|
||||
#define ITLB_LAST_VAR_UNRESTRICTED 0x000003F0 /* Last ITLB */
|
||||
|
||||
/* DTLB defines */
|
||||
#define DTLB_FIXED 0x00800000 /* First fixed DTLB, see head.S */
|
||||
#define DTLB_LAST_VAR_UNRESTRICTED 0x008003F0 /* Last DTLB */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/**
|
||||
* for_each_dtlb_entry - Iterate over free (non-wired) DTLB entries
|
||||
*
|
||||
* @tlb: TLB entry
|
||||
*/
|
||||
#define for_each_dtlb_entry(tlb) \
|
||||
for (tlb = cpu_data->dtlb.first; \
|
||||
tlb <= cpu_data->dtlb.last; \
|
||||
tlb += cpu_data->dtlb.step)
|
||||
|
||||
/**
|
||||
* for_each_itlb_entry - Iterate over free (non-wired) ITLB entries
|
||||
*
|
||||
* @tlb: TLB entry
|
||||
*/
|
||||
#define for_each_itlb_entry(tlb) \
|
||||
for (tlb = cpu_data->itlb.first; \
|
||||
tlb <= cpu_data->itlb.last; \
|
||||
tlb += cpu_data->itlb.step)
|
||||
|
||||
/**
|
||||
* __flush_tlb_slot - Flushes TLB slot @slot.
|
||||
*
|
||||
* @slot: Address of TLB slot.
|
||||
*/
|
||||
static inline void __flush_tlb_slot(unsigned long long slot)
|
||||
{
|
||||
__asm__ __volatile__ ("putcfg %0, 0, r63\n" : : "r" (slot));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
/* arch/sh64/mm/tlb.c */
|
||||
int sh64_tlb_init(void);
|
||||
unsigned long long sh64_next_free_dtlb_entry(void);
|
||||
unsigned long long sh64_get_wired_dtlb_entry(void);
|
||||
int sh64_put_wired_dtlb_entry(unsigned long long entry);
|
||||
void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
|
||||
unsigned long asid, unsigned long paddr);
|
||||
void sh64_teardown_tlb_slot(unsigned long long config_addr);
|
||||
#else
|
||||
#define sh64_tlb_init() do { } while (0)
|
||||
#define sh64_next_free_dtlb_entry() (0)
|
||||
#define sh64_get_wired_dtlb_entry() (0)
|
||||
#define sh64_put_wired_dtlb_entry(entry) do { } while (0)
|
||||
#define sh64_setup_tlb_slot(conf, virt, asid, phys) do { } while (0)
|
||||
#define sh64_teardown_tlb_slot(addr) do { } while (0)
|
||||
#endif /* CONFIG_MMU */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_SH_TLB_64_H */
|
||||
|
|
@ -4,11 +4,7 @@
|
|||
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
# include <asm/traps_32.h>
|
||||
#else
|
||||
# include <asm/traps_64.h>
|
||||
#endif
|
||||
|
||||
BUILD_TRAP_HANDLER(address_error);
|
||||
BUILD_TRAP_HANDLER(debug);
|
||||
|
|
|
|||
|
|
@ -1,35 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
* Copyright (C) 2004 Richard Curnow
|
||||
*/
|
||||
#ifndef __ASM_SH_TRAPS_64_H
|
||||
#define __ASM_SH_TRAPS_64_H
|
||||
|
||||
#include <cpu/registers.h>
|
||||
|
||||
extern void phys_stext(void);
|
||||
|
||||
#define lookup_exception_vector() \
|
||||
({ \
|
||||
unsigned long _vec; \
|
||||
\
|
||||
__asm__ __volatile__ ( \
|
||||
"getcon " __EXPEVT ", %0\n\t" \
|
||||
: "=r" (_vec) \
|
||||
); \
|
||||
\
|
||||
_vec; \
|
||||
})
|
||||
|
||||
static inline void trigger_address_error(void)
|
||||
{
|
||||
phys_stext();
|
||||
}
|
||||
|
||||
#define BUILD_TRAP_HANDLER(name) \
|
||||
asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
|
||||
#define TRAP_HANDLER_DECL
|
||||
|
||||
#endif /* __ASM_SH_TRAPS_64_H */
|
||||
|
|
@ -9,13 +9,8 @@
|
|||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
typedef u16 insn_size_t;
|
||||
typedef u32 reg_size_t;
|
||||
#else
|
||||
typedef u32 insn_size_t;
|
||||
typedef u64 reg_size_t;
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_SH_TYPES_H */
|
||||
|
|
|
|||
|
|
@ -96,11 +96,7 @@ struct __large_struct { unsigned long buf[100]; };
|
|||
__pu_err; \
|
||||
})
|
||||
|
||||
#ifdef CONFIG_SUPERH32
|
||||
# include <asm/uaccess_32.h>
|
||||
#else
|
||||
# include <asm/uaccess_64.h>
|
||||
#endif
|
||||
|
||||
extern long strncpy_from_user(char *dest, const char __user *src, long count);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,85 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_UACCESS_64_H
|
||||
#define __ASM_SH_UACCESS_64_H
|
||||
|
||||
/*
|
||||
* include/asm-sh/uaccess_64.h
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003, 2004 Paul Mundt
|
||||
*
|
||||
* User space memory access functions
|
||||
*
|
||||
* Copyright (C) 1999 Niibe Yutaka
|
||||
*
|
||||
* Based on:
|
||||
* MIPS implementation version 1.15 by
|
||||
* Copyright (C) 1996, 1997, 1998 by Ralf Baechle
|
||||
* and i386 version.
|
||||
*/
|
||||
|
||||
#define __get_user_size(x,ptr,size,retval) \
|
||||
do { \
|
||||
retval = 0; \
|
||||
x = 0; \
|
||||
switch (size) { \
|
||||
case 1: \
|
||||
retval = __get_user_asm_b((void *)&x, \
|
||||
(long)ptr); \
|
||||
break; \
|
||||
case 2: \
|
||||
retval = __get_user_asm_w((void *)&x, \
|
||||
(long)ptr); \
|
||||
break; \
|
||||
case 4: \
|
||||
retval = __get_user_asm_l((void *)&x, \
|
||||
(long)ptr); \
|
||||
break; \
|
||||
case 8: \
|
||||
retval = __get_user_asm_q((void *)&x, \
|
||||
(long)ptr); \
|
||||
break; \
|
||||
default: \
|
||||
__get_user_unknown(); \
|
||||
break; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
extern long __get_user_asm_b(void *, long);
|
||||
extern long __get_user_asm_w(void *, long);
|
||||
extern long __get_user_asm_l(void *, long);
|
||||
extern long __get_user_asm_q(void *, long);
|
||||
extern void __get_user_unknown(void);
|
||||
|
||||
#define __put_user_size(x,ptr,size,retval) \
|
||||
do { \
|
||||
retval = 0; \
|
||||
switch (size) { \
|
||||
case 1: \
|
||||
retval = __put_user_asm_b((void *)&x, \
|
||||
(__force long)ptr); \
|
||||
break; \
|
||||
case 2: \
|
||||
retval = __put_user_asm_w((void *)&x, \
|
||||
(__force long)ptr); \
|
||||
break; \
|
||||
case 4: \
|
||||
retval = __put_user_asm_l((void *)&x, \
|
||||
(__force long)ptr); \
|
||||
break; \
|
||||
case 8: \
|
||||
retval = __put_user_asm_q((void *)&x, \
|
||||
(__force long)ptr); \
|
||||
break; \
|
||||
default: \
|
||||
__put_user_unknown(); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
extern long __put_user_asm_b(void *, long);
|
||||
extern long __put_user_asm_w(void *, long);
|
||||
extern long __put_user_asm_l(void *, long);
|
||||
extern long __put_user_asm_q(void *, long);
|
||||
extern void __put_user_unknown(void);
|
||||
|
||||
#endif /* __ASM_SH_UACCESS_64_H */
|
||||
|
|
@ -1,9 +1,5 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
# ifdef CONFIG_SUPERH32
|
||||
# include <asm/unistd_32.h>
|
||||
# else
|
||||
# include <asm/unistd_64.h>
|
||||
# endif
|
||||
#include <asm/unistd_32.h>
|
||||
|
||||
#define NR_syscalls __NR_syscalls
|
||||
|
||||
|
|
|
|||
|
|
@ -28,19 +28,12 @@
|
|||
* to write an integer number of pages.
|
||||
*/
|
||||
|
||||
#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
|
||||
struct user_fpu_struct {
|
||||
unsigned long fp_regs[32];
|
||||
unsigned int fpscr;
|
||||
};
|
||||
#else
|
||||
struct user_fpu_struct {
|
||||
unsigned long fp_regs[16];
|
||||
unsigned long xfp_regs[16];
|
||||
unsigned long fpscr;
|
||||
unsigned long fpul;
|
||||
};
|
||||
#endif
|
||||
|
||||
struct user {
|
||||
struct pt_regs regs; /* entire machine state */
|
||||
|
|
|
|||
|
|
@ -10,8 +10,6 @@
|
|||
# define MODULE_PROC_FAMILY "SH3LE "
|
||||
# elif defined CONFIG_CPU_SH4
|
||||
# define MODULE_PROC_FAMILY "SH4LE "
|
||||
# elif defined CONFIG_CPU_SH5
|
||||
# define MODULE_PROC_FAMILY "SH5LE "
|
||||
# else
|
||||
# error unknown processor family
|
||||
# endif
|
||||
|
|
@ -22,8 +20,6 @@
|
|||
# define MODULE_PROC_FAMILY "SH3BE "
|
||||
# elif defined CONFIG_CPU_SH4
|
||||
# define MODULE_PROC_FAMILY "SH4BE "
|
||||
# elif defined CONFIG_CPU_SH5
|
||||
# define MODULE_PROC_FAMILY "SH5BE "
|
||||
# else
|
||||
# error unknown processor family
|
||||
# endif
|
||||
|
|
|
|||
|
|
@ -15,12 +15,4 @@
|
|||
#define DWARF_EH_FRAME
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SUPERH64
|
||||
#define EXTRA_TEXT \
|
||||
*(.text64) \
|
||||
*(.text..SHmedia32)
|
||||
#else
|
||||
#define EXTRA_TEXT
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SH_VMLINUX_LDS_H */
|
||||
|
|
|
|||
|
|
@ -1,12 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_CPU_SH5_ADDRSPACE_H
|
||||
#define __ASM_SH_CPU_SH5_ADDRSPACE_H
|
||||
|
||||
#define PHYS_PERIPHERAL_BLOCK 0x09000000
|
||||
#define PHYS_DMAC_BLOCK 0x0e000000
|
||||
#define PHYS_PCI_BLOCK 0x60000000
|
||||
#define PHYS_EMI_BLOCK 0xff000000
|
||||
|
||||
/* No segmentation.. */
|
||||
|
||||
#endif /* __ASM_SH_CPU_SH5_ADDRSPACE_H */
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_CPU_SH5_CACHE_H
|
||||
#define __ASM_SH_CPU_SH5_CACHE_H
|
||||
|
||||
/*
|
||||
* include/asm-sh/cpu-sh5/cache.h
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003, 2004 Paul Mundt
|
||||
*/
|
||||
|
||||
#define L1_CACHE_SHIFT 5
|
||||
|
||||
/* Valid and Dirty bits */
|
||||
#define SH_CACHE_VALID (1LL<<0)
|
||||
#define SH_CACHE_UPDATED (1LL<<57)
|
||||
|
||||
/* Unimplemented compat bits.. */
|
||||
#define SH_CACHE_COMBINED 0
|
||||
#define SH_CACHE_ASSOC 0
|
||||
|
||||
/* Cache flags */
|
||||
#define SH_CACHE_MODE_WT (1LL<<0)
|
||||
#define SH_CACHE_MODE_WB (1LL<<1)
|
||||
|
||||
/*
|
||||
* Control Registers.
|
||||
*/
|
||||
#define ICCR_BASE 0x01600000 /* Instruction Cache Control Register */
|
||||
#define ICCR_REG0 0 /* Register 0 offset */
|
||||
#define ICCR_REG1 1 /* Register 1 offset */
|
||||
#define ICCR0 ICCR_BASE+ICCR_REG0
|
||||
#define ICCR1 ICCR_BASE+ICCR_REG1
|
||||
|
||||
#define ICCR0_OFF 0x0 /* Set ICACHE off */
|
||||
#define ICCR0_ON 0x1 /* Set ICACHE on */
|
||||
#define ICCR0_ICI 0x2 /* Invalidate all in IC */
|
||||
|
||||
#define ICCR1_NOLOCK 0x0 /* Set No Locking */
|
||||
|
||||
#define OCCR_BASE 0x01E00000 /* Operand Cache Control Register */
|
||||
#define OCCR_REG0 0 /* Register 0 offset */
|
||||
#define OCCR_REG1 1 /* Register 1 offset */
|
||||
#define OCCR0 OCCR_BASE+OCCR_REG0
|
||||
#define OCCR1 OCCR_BASE+OCCR_REG1
|
||||
|
||||
#define OCCR0_OFF 0x0 /* Set OCACHE off */
|
||||
#define OCCR0_ON 0x1 /* Set OCACHE on */
|
||||
#define OCCR0_OCI 0x2 /* Invalidate all in OC */
|
||||
#define OCCR0_WT 0x4 /* Set OCACHE in WT Mode */
|
||||
#define OCCR0_WB 0x0 /* Set OCACHE in WB Mode */
|
||||
|
||||
#define OCCR1_NOLOCK 0x0 /* Set No Locking */
|
||||
|
||||
/*
|
||||
* SH-5
|
||||
* A bit of description here, for neff=32.
|
||||
*
|
||||
* |<--- tag (19 bits) --->|
|
||||
* +-----------------------------+-----------------+------+----------+------+
|
||||
* | | | ways |set index |offset|
|
||||
* +-----------------------------+-----------------+------+----------+------+
|
||||
* ^ 2 bits 8 bits 5 bits
|
||||
* +- Bit 31
|
||||
*
|
||||
* Cacheline size is based on offset: 5 bits = 32 bytes per line
|
||||
* A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
|
||||
* have a broader space for registers. These are outlined by
|
||||
* CACHE_?C_*_STEP below.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Instruction cache */
|
||||
#define CACHE_IC_ADDRESS_ARRAY 0x01000000
|
||||
|
||||
/* Operand Cache */
|
||||
#define CACHE_OC_ADDRESS_ARRAY 0x01800000
|
||||
|
||||
/* These declarations relate to cache 'synonyms' in the operand cache. A
|
||||
'synonym' occurs where effective address bits overlap between those used for
|
||||
indexing the cache sets and those passed to the MMU for translation. In the
|
||||
case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
|
||||
|
||||
#define CACHE_OC_N_SYNBITS 1 /* Number of synonym bits */
|
||||
#define CACHE_OC_SYN_SHIFT 12
|
||||
/* Mask to select synonym bit(s) */
|
||||
#define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
|
||||
|
||||
/*
|
||||
* Instruction cache can't be invalidated based on physical addresses.
|
||||
* No Instruction Cache defines required, then.
|
||||
*/
|
||||
|
||||
#endif /* __ASM_SH_CPU_SH5_CACHE_H */
|
||||
|
|
@ -1,113 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_CPU_SH5_IRQ_H
|
||||
#define __ASM_SH_CPU_SH5_IRQ_H
|
||||
|
||||
/*
|
||||
* include/asm-sh/cpu-sh5/irq.h
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Encoded IRQs are not considered worth to be supported.
|
||||
* Main reason is that there's no per-encoded-interrupt
|
||||
* enable/disable mechanism (as there was in SH3/4).
|
||||
* An all enabled/all disabled is worth only if there's
|
||||
* a cascaded IC to disable/enable/ack on. Until such
|
||||
* IC is available there's no such support.
|
||||
*
|
||||
* Presumably Encoded IRQs may use extra IRQs beyond 64,
|
||||
* below. Some logic must be added to cope with IRQ_IRL?
|
||||
* in an exclusive way.
|
||||
*
|
||||
* Priorities are set at Platform level, when IRQ_IRL0-3
|
||||
* are set to 0 Encoding is allowed. Otherwise it's not
|
||||
* allowed.
|
||||
*/
|
||||
|
||||
/* Independent IRQs */
|
||||
#define IRQ_IRL0 0
|
||||
#define IRQ_IRL1 1
|
||||
#define IRQ_IRL2 2
|
||||
#define IRQ_IRL3 3
|
||||
|
||||
#define IRQ_INTA 4
|
||||
#define IRQ_INTB 5
|
||||
#define IRQ_INTC 6
|
||||
#define IRQ_INTD 7
|
||||
|
||||
#define IRQ_SERR 12
|
||||
#define IRQ_ERR 13
|
||||
#define IRQ_PWR3 14
|
||||
#define IRQ_PWR2 15
|
||||
#define IRQ_PWR1 16
|
||||
#define IRQ_PWR0 17
|
||||
|
||||
#define IRQ_DMTE0 18
|
||||
#define IRQ_DMTE1 19
|
||||
#define IRQ_DMTE2 20
|
||||
#define IRQ_DMTE3 21
|
||||
#define IRQ_DAERR 22
|
||||
|
||||
#define IRQ_TUNI0 32
|
||||
#define IRQ_TUNI1 33
|
||||
#define IRQ_TUNI2 34
|
||||
#define IRQ_TICPI2 35
|
||||
|
||||
#define IRQ_ATI 36
|
||||
#define IRQ_PRI 37
|
||||
#define IRQ_CUI 38
|
||||
|
||||
#define IRQ_ERI 39
|
||||
#define IRQ_RXI 40
|
||||
#define IRQ_BRI 41
|
||||
#define IRQ_TXI 42
|
||||
|
||||
#define IRQ_ITI 63
|
||||
|
||||
#define NR_INTC_IRQS 64
|
||||
|
||||
#ifdef CONFIG_SH_CAYMAN
|
||||
#define NR_EXT_IRQS 32
|
||||
#define START_EXT_IRQS 64
|
||||
|
||||
/* PCI bus 2 uses encoded external interrupts on the Cayman board */
|
||||
#define IRQ_P2INTA (START_EXT_IRQS + (3*8) + 0)
|
||||
#define IRQ_P2INTB (START_EXT_IRQS + (3*8) + 1)
|
||||
#define IRQ_P2INTC (START_EXT_IRQS + (3*8) + 2)
|
||||
#define IRQ_P2INTD (START_EXT_IRQS + (3*8) + 3)
|
||||
|
||||
#define I8042_KBD_IRQ (START_EXT_IRQS + 2)
|
||||
#define I8042_AUX_IRQ (START_EXT_IRQS + 6)
|
||||
|
||||
#define IRQ_CFCARD (START_EXT_IRQS + 7)
|
||||
#define IRQ_PCMCIA (0)
|
||||
|
||||
#else
|
||||
#define NR_EXT_IRQS 0
|
||||
#endif
|
||||
|
||||
/* Default IRQs, fixed */
|
||||
#define TIMER_IRQ IRQ_TUNI0
|
||||
#define RTC_IRQ IRQ_CUI
|
||||
|
||||
/* Default Priorities, Platform may choose differently */
|
||||
#define NO_PRIORITY 0 /* Disabled */
|
||||
#define TIMER_PRIORITY 2
|
||||
#define RTC_PRIORITY TIMER_PRIORITY
|
||||
#define SCIF_PRIORITY 3
|
||||
#define INTD_PRIORITY 3
|
||||
#define IRL3_PRIORITY 4
|
||||
#define INTC_PRIORITY 6
|
||||
#define IRL2_PRIORITY 7
|
||||
#define INTB_PRIORITY 9
|
||||
#define IRL1_PRIORITY 10
|
||||
#define INTA_PRIORITY 12
|
||||
#define IRL0_PRIORITY 13
|
||||
#define TOP_PRIORITY 15
|
||||
|
||||
extern int intc_evt_to_irq[(0xE20/0x20)+1];
|
||||
extern int platform_int_priority[NR_INTC_IRQS];
|
||||
|
||||
#endif /* __ASM_SH_CPU_SH5_IRQ_H */
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_CPU_SH5_MMU_CONTEXT_H
|
||||
#define __ASM_SH_CPU_SH5_MMU_CONTEXT_H
|
||||
|
||||
/* Common defines */
|
||||
#define TLB_STEP 0x00000010
|
||||
#define TLB_PTEH 0x00000000
|
||||
#define TLB_PTEL 0x00000008
|
||||
|
||||
/* PTEH defines */
|
||||
#define PTEH_ASID_SHIFT 2
|
||||
#define PTEH_VALID 0x0000000000000001
|
||||
#define PTEH_SHARED 0x0000000000000002
|
||||
#define PTEH_MATCH_ASID 0x00000000000003ff
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/* This has to be a common function because the next location to fill
|
||||
* information is shared. */
|
||||
extern void __do_tlb_refill(unsigned long address, unsigned long long is_text_not_data, pte_t *pte);
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ASM_SH_CPU_SH5_MMU_CONTEXT_H */
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_CPU_SH5_REGISTERS_H
|
||||
#define __ASM_SH_CPU_SH5_REGISTERS_H
|
||||
|
||||
/*
|
||||
* include/asm-sh/cpu-sh5/registers.h
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2004 Richard Curnow
|
||||
*/
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
/* =====================================================================
|
||||
**
|
||||
** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
|
||||
** Assigns symbolic names to control & target registers.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Define some useful aliases for control registers.
|
||||
*/
|
||||
#define SR cr0
|
||||
#define SSR cr1
|
||||
#define PSSR cr2
|
||||
/* cr3 UNDEFINED */
|
||||
#define INTEVT cr4
|
||||
#define EXPEVT cr5
|
||||
#define PEXPEVT cr6
|
||||
#define TRA cr7
|
||||
#define SPC cr8
|
||||
#define PSPC cr9
|
||||
#define RESVEC cr10
|
||||
#define VBR cr11
|
||||
/* cr12 UNDEFINED */
|
||||
#define TEA cr13
|
||||
/* cr14-cr15 UNDEFINED */
|
||||
#define DCR cr16
|
||||
#define KCR0 cr17
|
||||
#define KCR1 cr18
|
||||
/* cr19-cr31 UNDEFINED */
|
||||
/* cr32-cr61 RESERVED */
|
||||
#define CTC cr62
|
||||
#define USR cr63
|
||||
|
||||
/*
|
||||
* ABI dependent registers (general purpose set)
|
||||
*/
|
||||
#define RET r2
|
||||
#define ARG1 r2
|
||||
#define ARG2 r3
|
||||
#define ARG3 r4
|
||||
#define ARG4 r5
|
||||
#define ARG5 r6
|
||||
#define ARG6 r7
|
||||
#define SP r15
|
||||
#define LINK r18
|
||||
#define ZERO r63
|
||||
|
||||
/*
|
||||
* Status register defines: used only by assembly sources (and
|
||||
* syntax independednt)
|
||||
*/
|
||||
#define SR_RESET_VAL 0x0000000050008000
|
||||
#define SR_HARMLESS 0x00000000500080f0 /* Write ignores for most */
|
||||
#define SR_ENABLE_FPU 0xffffffffffff7fff /* AND with this */
|
||||
|
||||
#if defined (CONFIG_SH64_SR_WATCH)
|
||||
#define SR_ENABLE_MMU 0x0000000084000000 /* OR with this */
|
||||
#else
|
||||
#define SR_ENABLE_MMU 0x0000000080000000 /* OR with this */
|
||||
#endif
|
||||
|
||||
#define SR_UNBLOCK_EXC 0xffffffffefffffff /* AND with this */
|
||||
#define SR_BLOCK_EXC 0x0000000010000000 /* OR with this */
|
||||
|
||||
#else /* Not __ASSEMBLY__ syntax */
|
||||
|
||||
/*
|
||||
** Stringify reg. name
|
||||
*/
|
||||
#define __str(x) #x
|
||||
|
||||
/* Stringify control register names for use in inline assembly */
|
||||
#define __SR __str(SR)
|
||||
#define __SSR __str(SSR)
|
||||
#define __PSSR __str(PSSR)
|
||||
#define __INTEVT __str(INTEVT)
|
||||
#define __EXPEVT __str(EXPEVT)
|
||||
#define __PEXPEVT __str(PEXPEVT)
|
||||
#define __TRA __str(TRA)
|
||||
#define __SPC __str(SPC)
|
||||
#define __PSPC __str(PSPC)
|
||||
#define __RESVEC __str(RESVEC)
|
||||
#define __VBR __str(VBR)
|
||||
#define __TEA __str(TEA)
|
||||
#define __DCR __str(DCR)
|
||||
#define __KCR0 __str(KCR0)
|
||||
#define __KCR1 __str(KCR1)
|
||||
#define __CTC __str(CTC)
|
||||
#define __USR __str(USR)
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_SH_CPU_SH5_REGISTERS_H */
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __ASM_SH_CPU_SH5_RTC_H
|
||||
#define __ASM_SH_CPU_SH5_RTC_H
|
||||
|
||||
#define rtc_reg_size sizeof(u32)
|
||||
#define RTC_BIT_INVERTED 0 /* The SH-5 RTC is surprisingly sane! */
|
||||
#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
|
||||
|
||||
#endif /* __ASM_SH_CPU_SH5_RTC_H */
|
||||
|
|
@ -1,8 +1,2 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
#ifndef __KERNEL__
|
||||
# ifdef __SH5__
|
||||
# include <asm/posix_types_64.h>
|
||||
# else
|
||||
# include <asm/posix_types_32.h>
|
||||
# endif
|
||||
#endif /* __KERNEL__ */
|
||||
#include <asm/posix_types_32.h>
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
#ifndef __ASM_SH_POSIX_TYPES_64_H
|
||||
#define __ASM_SH_POSIX_TYPES_64_H
|
||||
|
||||
typedef unsigned short __kernel_mode_t;
|
||||
#define __kernel_mode_t __kernel_mode_t
|
||||
typedef unsigned short __kernel_ipc_pid_t;
|
||||
#define __kernel_ipc_pid_t __kernel_ipc_pid_t
|
||||
typedef unsigned short __kernel_uid_t;
|
||||
#define __kernel_uid_t __kernel_uid_t
|
||||
typedef unsigned short __kernel_gid_t;
|
||||
#define __kernel_gid_t __kernel_gid_t
|
||||
typedef long unsigned int __kernel_size_t;
|
||||
#define __kernel_size_t __kernel_size_t
|
||||
typedef int __kernel_ssize_t;
|
||||
#define __kernel_ssize_t __kernel_ssize_t
|
||||
typedef int __kernel_ptrdiff_t;
|
||||
#define __kernel_ptrdiff_t __kernel_ptrdiff_t
|
||||
|
||||
typedef unsigned short __kernel_old_uid_t;
|
||||
#define __kernel_old_uid_t __kernel_old_uid_t
|
||||
typedef unsigned short __kernel_old_gid_t;
|
||||
#define __kernel_old_gid_t __kernel_old_gid_t
|
||||
typedef unsigned short __kernel_old_dev_t;
|
||||
#define __kernel_old_dev_t __kernel_old_dev_t
|
||||
|
||||
#include <asm-generic/posix_types.h>
|
||||
|
||||
#endif /* __ASM_SH_POSIX_TYPES_64_H */
|
||||
|
|
@ -25,11 +25,6 @@
|
|||
#define PT_DATA_ADDR 248 /* &(struct user)->start_data */
|
||||
#define PT_TEXT_LEN 252
|
||||
|
||||
#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
|
||||
#include <asm/ptrace_64.h>
|
||||
#else
|
||||
#include <asm/ptrace_32.h>
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _UAPI__ASM_SH_PTRACE_H */
|
||||
|
|
|
|||
|
|
@ -1,15 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
#ifndef _UAPI__ASM_SH_PTRACE_64_H
|
||||
#define _UAPI__ASM_SH_PTRACE_64_H
|
||||
|
||||
struct pt_regs {
|
||||
unsigned long long pc;
|
||||
unsigned long long sr;
|
||||
long long syscall_nr;
|
||||
unsigned long long regs[63];
|
||||
unsigned long long tregs[8];
|
||||
unsigned long long pad[2];
|
||||
};
|
||||
|
||||
|
||||
#endif /* _UAPI__ASM_SH_PTRACE_64_H */
|
||||
|
|
@ -5,18 +5,6 @@
|
|||
struct sigcontext {
|
||||
unsigned long oldmask;
|
||||
|
||||
#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
|
||||
/* CPU registers */
|
||||
unsigned long long sc_regs[63];
|
||||
unsigned long long sc_tregs[8];
|
||||
unsigned long long sc_pc;
|
||||
unsigned long long sc_sr;
|
||||
|
||||
/* FPU registers */
|
||||
unsigned long long sc_fpregs[32];
|
||||
unsigned int sc_fpscr;
|
||||
unsigned int sc_fpvalid;
|
||||
#else
|
||||
/* CPU registers */
|
||||
unsigned long sc_regs[16];
|
||||
unsigned long sc_pc;
|
||||
|
|
@ -32,7 +20,6 @@ struct sigcontext {
|
|||
unsigned int sc_fpscr;
|
||||
unsigned int sc_fpul;
|
||||
unsigned int sc_ownedfp;
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* __ASM_SH_SIGCONTEXT_H */
|
||||
|
|
|
|||
|
|
@ -16,66 +16,6 @@ struct __old_kernel_stat {
|
|||
unsigned long st_ctime;
|
||||
};
|
||||
|
||||
#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
|
||||
struct stat {
|
||||
unsigned short st_dev;
|
||||
unsigned short __pad1;
|
||||
unsigned long st_ino;
|
||||
unsigned short st_mode;
|
||||
unsigned short st_nlink;
|
||||
unsigned short st_uid;
|
||||
unsigned short st_gid;
|
||||
unsigned short st_rdev;
|
||||
unsigned short __pad2;
|
||||
unsigned long st_size;
|
||||
unsigned long st_blksize;
|
||||
unsigned long st_blocks;
|
||||
unsigned long st_atime;
|
||||
unsigned long st_atime_nsec;
|
||||
unsigned long st_mtime;
|
||||
unsigned long st_mtime_nsec;
|
||||
unsigned long st_ctime;
|
||||
unsigned long st_ctime_nsec;
|
||||
unsigned long __unused4;
|
||||
unsigned long __unused5;
|
||||
};
|
||||
|
||||
/* This matches struct stat64 in glibc2.1, hence the absolutely
|
||||
* insane amounts of padding around dev_t's.
|
||||
*/
|
||||
struct stat64 {
|
||||
unsigned short st_dev;
|
||||
unsigned char __pad0[10];
|
||||
|
||||
unsigned long st_ino;
|
||||
unsigned int st_mode;
|
||||
unsigned int st_nlink;
|
||||
|
||||
unsigned long st_uid;
|
||||
unsigned long st_gid;
|
||||
|
||||
unsigned short st_rdev;
|
||||
unsigned char __pad3[10];
|
||||
|
||||
long long st_size;
|
||||
unsigned long st_blksize;
|
||||
|
||||
unsigned long st_blocks; /* Number 512-byte blocks allocated. */
|
||||
unsigned long __pad4; /* future possible st_blocks high bits */
|
||||
|
||||
unsigned long st_atime;
|
||||
unsigned long st_atime_nsec;
|
||||
|
||||
unsigned long st_mtime;
|
||||
unsigned long st_mtime_nsec;
|
||||
|
||||
unsigned long st_ctime;
|
||||
unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */
|
||||
|
||||
unsigned long __unused1;
|
||||
unsigned long __unused2;
|
||||
};
|
||||
#else
|
||||
struct stat {
|
||||
unsigned long st_dev;
|
||||
unsigned long st_ino;
|
||||
|
|
@ -134,6 +74,5 @@ struct stat64 {
|
|||
};
|
||||
|
||||
#define STAT_HAVE_NSEC 1
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SH_STAT_H */
|
||||
|
|
|
|||
|
|
@ -13,14 +13,9 @@
|
|||
static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
|
||||
{
|
||||
__asm__(
|
||||
#ifdef __SH5__
|
||||
"byterev %1, %0\n\t"
|
||||
"shari %0, 32, %0"
|
||||
#else
|
||||
"swap.b %1, %0\n\t"
|
||||
"swap.w %0, %0\n\t"
|
||||
"swap.b %0, %0"
|
||||
#endif
|
||||
: "=r" (x)
|
||||
: "r" (x));
|
||||
|
||||
|
|
@ -31,12 +26,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
|
|||
static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
|
||||
{
|
||||
__asm__(
|
||||
#ifdef __SH5__
|
||||
"byterev %1, %0\n\t"
|
||||
"shari %0, 32, %0"
|
||||
#else
|
||||
"swap.b %1, %0"
|
||||
#endif
|
||||
: "=r" (x)
|
||||
: "r" (x));
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,2 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
#ifndef __KERNEL__
|
||||
# ifdef __SH5__
|
||||
# include <asm/unistd_64.h>
|
||||
# else
|
||||
# include <asm/unistd_32.h>
|
||||
# endif
|
||||
#endif
|
||||
#include <asm/unistd_32.h>
|
||||
|
|
|
|||
|
|
@ -1,423 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
#ifndef __ASM_SH_UNISTD_64_H
|
||||
#define __ASM_SH_UNISTD_64_H
|
||||
|
||||
/*
|
||||
* include/asm-sh/unistd_64.h
|
||||
*
|
||||
* This file contains the system call numbers.
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003 - 2007 Paul Mundt
|
||||
* Copyright (C) 2004 Sean McGoogan
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#define __NR_restart_syscall 0
|
||||
#define __NR_exit 1
|
||||
#define __NR_fork 2
|
||||
#define __NR_read 3
|
||||
#define __NR_write 4
|
||||
#define __NR_open 5
|
||||
#define __NR_close 6
|
||||
#define __NR_waitpid 7
|
||||
#define __NR_creat 8
|
||||
#define __NR_link 9
|
||||
#define __NR_unlink 10
|
||||
#define __NR_execve 11
|
||||
#define __NR_chdir 12
|
||||
#define __NR_time 13
|
||||
#define __NR_mknod 14
|
||||
#define __NR_chmod 15
|
||||
#define __NR_lchown 16
|
||||
/* 17 was sys_break */
|
||||
#define __NR_oldstat 18
|
||||
#define __NR_lseek 19
|
||||
#define __NR_getpid 20
|
||||
#define __NR_mount 21
|
||||
#define __NR_umount 22
|
||||
#define __NR_setuid 23
|
||||
#define __NR_getuid 24
|
||||
#define __NR_stime 25
|
||||
#define __NR_ptrace 26
|
||||
#define __NR_alarm 27
|
||||
#define __NR_oldfstat 28
|
||||
#define __NR_pause 29
|
||||
#define __NR_utime 30
|
||||
/* 31 was sys_stty */
|
||||
/* 32 was sys_gtty */
|
||||
#define __NR_access 33
|
||||
#define __NR_nice 34
|
||||
/* 35 was sys_ftime */
|
||||
#define __NR_sync 36
|
||||
#define __NR_kill 37
|
||||
#define __NR_rename 38
|
||||
#define __NR_mkdir 39
|
||||
#define __NR_rmdir 40
|
||||
#define __NR_dup 41
|
||||
#define __NR_pipe 42
|
||||
#define __NR_times 43
|
||||
/* 44 was sys_prof */
|
||||
#define __NR_brk 45
|
||||
#define __NR_setgid 46
|
||||
#define __NR_getgid 47
|
||||
#define __NR_signal 48
|
||||
#define __NR_geteuid 49
|
||||
#define __NR_getegid 50
|
||||
#define __NR_acct 51
|
||||
#define __NR_umount2 52
|
||||
/* 53 was sys_lock */
|
||||
#define __NR_ioctl 54
|
||||
#define __NR_fcntl 55
|
||||
/* 56 was sys_mpx */
|
||||
#define __NR_setpgid 57
|
||||
/* 58 was sys_ulimit */
|
||||
/* 59 was sys_olduname */
|
||||
#define __NR_umask 60
|
||||
#define __NR_chroot 61
|
||||
#define __NR_ustat 62
|
||||
#define __NR_dup2 63
|
||||
#define __NR_getppid 64
|
||||
#define __NR_getpgrp 65
|
||||
#define __NR_setsid 66
|
||||
#define __NR_sigaction 67
|
||||
#define __NR_sgetmask 68
|
||||
#define __NR_ssetmask 69
|
||||
#define __NR_setreuid 70
|
||||
#define __NR_setregid 71
|
||||
#define __NR_sigsuspend 72
|
||||
#define __NR_sigpending 73
|
||||
#define __NR_sethostname 74
|
||||
#define __NR_setrlimit 75
|
||||
#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
|
||||
#define __NR_getrusage 77
|
||||
#define __NR_gettimeofday 78
|
||||
#define __NR_settimeofday 79
|
||||
#define __NR_getgroups 80
|
||||
#define __NR_setgroups 81
|
||||
/* 82 was sys_select */
|
||||
#define __NR_symlink 83
|
||||
#define __NR_oldlstat 84
|
||||
#define __NR_readlink 85
|
||||
#define __NR_uselib 86
|
||||
#define __NR_swapon 87
|
||||
#define __NR_reboot 88
|
||||
#define __NR_readdir 89
|
||||
#define __NR_mmap 90
|
||||
#define __NR_munmap 91
|
||||
#define __NR_truncate 92
|
||||
#define __NR_ftruncate 93
|
||||
#define __NR_fchmod 94
|
||||
#define __NR_fchown 95
|
||||
#define __NR_getpriority 96
|
||||
#define __NR_setpriority 97
|
||||
/* 98 was sys_profil */
|
||||
#define __NR_statfs 99
|
||||
#define __NR_fstatfs 100
|
||||
/* 101 was sys_ioperm */
|
||||
#define __NR_socketcall 102 /* old implementation of socket systemcall */
|
||||
#define __NR_syslog 103
|
||||
#define __NR_setitimer 104
|
||||
#define __NR_getitimer 105
|
||||
#define __NR_stat 106
|
||||
#define __NR_lstat 107
|
||||
#define __NR_fstat 108
|
||||
#define __NR_olduname 109
|
||||
/* 110 was sys_iopl */
|
||||
#define __NR_vhangup 111
|
||||
/* 112 was sys_idle */
|
||||
/* 113 was sys_vm86old */
|
||||
#define __NR_wait4 114
|
||||
#define __NR_swapoff 115
|
||||
#define __NR_sysinfo 116
|
||||
#define __NR_ipc 117
|
||||
#define __NR_fsync 118
|
||||
#define __NR_sigreturn 119
|
||||
#define __NR_clone 120
|
||||
#define __NR_setdomainname 121
|
||||
#define __NR_uname 122
|
||||
#define __NR_cacheflush 123
|
||||
#define __NR_adjtimex 124
|
||||
#define __NR_mprotect 125
|
||||
#define __NR_sigprocmask 126
|
||||
/* 127 was sys_create_module */
|
||||
#define __NR_init_module 128
|
||||
#define __NR_delete_module 129
|
||||
/* 130 was sys_get_kernel_syms */
|
||||
#define __NR_quotactl 131
|
||||
#define __NR_getpgid 132
|
||||
#define __NR_fchdir 133
|
||||
#define __NR_bdflush 134
|
||||
#define __NR_sysfs 135
|
||||
#define __NR_personality 136
|
||||
/* 137 was sys_afs_syscall */
|
||||
#define __NR_setfsuid 138
|
||||
#define __NR_setfsgid 139
|
||||
#define __NR__llseek 140
|
||||
#define __NR_getdents 141
|
||||
#define __NR__newselect 142
|
||||
#define __NR_flock 143
|
||||
#define __NR_msync 144
|
||||
#define __NR_readv 145
|
||||
#define __NR_writev 146
|
||||
#define __NR_getsid 147
|
||||
#define __NR_fdatasync 148
|
||||
#define __NR__sysctl 149
|
||||
#define __NR_mlock 150
|
||||
#define __NR_munlock 151
|
||||
#define __NR_mlockall 152
|
||||
#define __NR_munlockall 153
|
||||
#define __NR_sched_setparam 154
|
||||
#define __NR_sched_getparam 155
|
||||
#define __NR_sched_setscheduler 156
|
||||
#define __NR_sched_getscheduler 157
|
||||
#define __NR_sched_yield 158
|
||||
#define __NR_sched_get_priority_max 159
|
||||
#define __NR_sched_get_priority_min 160
|
||||
#define __NR_sched_rr_get_interval 161
|
||||
#define __NR_nanosleep 162
|
||||
#define __NR_mremap 163
|
||||
#define __NR_setresuid 164
|
||||
#define __NR_getresuid 165
|
||||
/* 166 was sys_vm86 */
|
||||
/* 167 was sys_query_module */
|
||||
#define __NR_poll 168
|
||||
#define __NR_nfsservctl 169
|
||||
#define __NR_setresgid 170
|
||||
#define __NR_getresgid 171
|
||||
#define __NR_prctl 172
|
||||
#define __NR_rt_sigreturn 173
|
||||
#define __NR_rt_sigaction 174
|
||||
#define __NR_rt_sigprocmask 175
|
||||
#define __NR_rt_sigpending 176
|
||||
#define __NR_rt_sigtimedwait 177
|
||||
#define __NR_rt_sigqueueinfo 178
|
||||
#define __NR_rt_sigsuspend 179
|
||||
#define __NR_pread64 180
|
||||
#define __NR_pwrite64 181
|
||||
#define __NR_chown 182
|
||||
#define __NR_getcwd 183
|
||||
#define __NR_capget 184
|
||||
#define __NR_capset 185
|
||||
#define __NR_sigaltstack 186
|
||||
#define __NR_sendfile 187
|
||||
/* 188 reserved for getpmsg */
|
||||
/* 189 reserved for putpmsg */
|
||||
#define __NR_vfork 190
|
||||
#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
|
||||
#define __NR_mmap2 192
|
||||
#define __NR_truncate64 193
|
||||
#define __NR_ftruncate64 194
|
||||
#define __NR_stat64 195
|
||||
#define __NR_lstat64 196
|
||||
#define __NR_fstat64 197
|
||||
#define __NR_lchown32 198
|
||||
#define __NR_getuid32 199
|
||||
#define __NR_getgid32 200
|
||||
#define __NR_geteuid32 201
|
||||
#define __NR_getegid32 202
|
||||
#define __NR_setreuid32 203
|
||||
#define __NR_setregid32 204
|
||||
#define __NR_getgroups32 205
|
||||
#define __NR_setgroups32 206
|
||||
#define __NR_fchown32 207
|
||||
#define __NR_setresuid32 208
|
||||
#define __NR_getresuid32 209
|
||||
#define __NR_setresgid32 210
|
||||
#define __NR_getresgid32 211
|
||||
#define __NR_chown32 212
|
||||
#define __NR_setuid32 213
|
||||
#define __NR_setgid32 214
|
||||
#define __NR_setfsuid32 215
|
||||
#define __NR_setfsgid32 216
|
||||
#define __NR_pivot_root 217
|
||||
#define __NR_mincore 218
|
||||
#define __NR_madvise 219
|
||||
|
||||
/* Non-multiplexed socket family */
|
||||
#define __NR_socket 220
|
||||
#define __NR_bind 221
|
||||
#define __NR_connect 222
|
||||
#define __NR_listen 223
|
||||
#define __NR_accept 224
|
||||
#define __NR_getsockname 225
|
||||
#define __NR_getpeername 226
|
||||
#define __NR_socketpair 227
|
||||
#define __NR_send 228
|
||||
#define __NR_sendto 229
|
||||
#define __NR_recv 230
|
||||
#define __NR_recvfrom 231
|
||||
#define __NR_shutdown 232
|
||||
#define __NR_setsockopt 233
|
||||
#define __NR_getsockopt 234
|
||||
#define __NR_sendmsg 235
|
||||
#define __NR_recvmsg 236
|
||||
|
||||
/* Non-multiplexed IPC family */
|
||||
#define __NR_semop 237
|
||||
#define __NR_semget 238
|
||||
#define __NR_semctl 239
|
||||
#define __NR_msgsnd 240
|
||||
#define __NR_msgrcv 241
|
||||
#define __NR_msgget 242
|
||||
#define __NR_msgctl 243
|
||||
#define __NR_shmat 244
|
||||
#define __NR_shmdt 245
|
||||
#define __NR_shmget 246
|
||||
#define __NR_shmctl 247
|
||||
|
||||
#define __NR_getdents64 248
|
||||
#define __NR_fcntl64 249
|
||||
/* 250 is reserved for tux */
|
||||
/* 251 is unused */
|
||||
#define __NR_gettid 252
|
||||
#define __NR_readahead 253
|
||||
#define __NR_setxattr 254
|
||||
#define __NR_lsetxattr 255
|
||||
#define __NR_fsetxattr 256
|
||||
#define __NR_getxattr 257
|
||||
#define __NR_lgetxattr 258
|
||||
#define __NR_fgetxattr 259
|
||||
#define __NR_listxattr 260
|
||||
#define __NR_llistxattr 261
|
||||
#define __NR_flistxattr 262
|
||||
#define __NR_removexattr 263
|
||||
#define __NR_lremovexattr 264
|
||||
#define __NR_fremovexattr 265
|
||||
#define __NR_tkill 266
|
||||
#define __NR_sendfile64 267
|
||||
#define __NR_futex 268
|
||||
#define __NR_sched_setaffinity 269
|
||||
#define __NR_sched_getaffinity 270
|
||||
/* 271 is reserved for set_thread_area */
|
||||
/* 272 is reserved for get_thread_area */
|
||||
#define __NR_io_setup 273
|
||||
#define __NR_io_destroy 274
|
||||
#define __NR_io_getevents 275
|
||||
#define __NR_io_submit 276
|
||||
#define __NR_io_cancel 277
|
||||
#define __NR_fadvise64 278
|
||||
/* 279 is unused */
|
||||
#define __NR_exit_group 280
|
||||
|
||||
#define __NR_lookup_dcookie 281
|
||||
#define __NR_epoll_create 282
|
||||
#define __NR_epoll_ctl 283
|
||||
#define __NR_epoll_wait 284
|
||||
#define __NR_remap_file_pages 285
|
||||
#define __NR_set_tid_address 286
|
||||
#define __NR_timer_create 287
|
||||
#define __NR_timer_settime (__NR_timer_create+1)
|
||||
#define __NR_timer_gettime (__NR_timer_create+2)
|
||||
#define __NR_timer_getoverrun (__NR_timer_create+3)
|
||||
#define __NR_timer_delete (__NR_timer_create+4)
|
||||
#define __NR_clock_settime (__NR_timer_create+5)
|
||||
#define __NR_clock_gettime (__NR_timer_create+6)
|
||||
#define __NR_clock_getres (__NR_timer_create+7)
|
||||
#define __NR_clock_nanosleep (__NR_timer_create+8)
|
||||
#define __NR_statfs64 296
|
||||
#define __NR_fstatfs64 297
|
||||
#define __NR_tgkill 298
|
||||
#define __NR_utimes 299
|
||||
#define __NR_fadvise64_64 300
|
||||
/* 301 is reserved for vserver */
|
||||
/* 302 is reserved for mbind */
|
||||
/* 303 is reserved for get_mempolicy */
|
||||
/* 304 is reserved for set_mempolicy */
|
||||
#define __NR_mq_open 305
|
||||
#define __NR_mq_unlink (__NR_mq_open+1)
|
||||
#define __NR_mq_timedsend (__NR_mq_open+2)
|
||||
#define __NR_mq_timedreceive (__NR_mq_open+3)
|
||||
#define __NR_mq_notify (__NR_mq_open+4)
|
||||
#define __NR_mq_getsetattr (__NR_mq_open+5)
|
||||
/* 311 is reserved for kexec */
|
||||
#define __NR_waitid 312
|
||||
#define __NR_add_key 313
|
||||
#define __NR_request_key 314
|
||||
#define __NR_keyctl 315
|
||||
#define __NR_ioprio_set 316
|
||||
#define __NR_ioprio_get 317
|
||||
#define __NR_inotify_init 318
|
||||
#define __NR_inotify_add_watch 319
|
||||
#define __NR_inotify_rm_watch 320
|
||||
/* 321 is unused */
|
||||
#define __NR_migrate_pages 322
|
||||
#define __NR_openat 323
|
||||
#define __NR_mkdirat 324
|
||||
#define __NR_mknodat 325
|
||||
#define __NR_fchownat 326
|
||||
#define __NR_futimesat 327
|
||||
#define __NR_fstatat64 328
|
||||
#define __NR_unlinkat 329
|
||||
#define __NR_renameat 330
|
||||
#define __NR_linkat 331
|
||||
#define __NR_symlinkat 332
|
||||
#define __NR_readlinkat 333
|
||||
#define __NR_fchmodat 334
|
||||
#define __NR_faccessat 335
|
||||
#define __NR_pselect6 336
|
||||
#define __NR_ppoll 337
|
||||
#define __NR_unshare 338
|
||||
#define __NR_set_robust_list 339
|
||||
#define __NR_get_robust_list 340
|
||||
#define __NR_splice 341
|
||||
#define __NR_sync_file_range 342
|
||||
#define __NR_tee 343
|
||||
#define __NR_vmsplice 344
|
||||
#define __NR_move_pages 345
|
||||
#define __NR_getcpu 346
|
||||
#define __NR_epoll_pwait 347
|
||||
#define __NR_utimensat 348
|
||||
#define __NR_signalfd 349
|
||||
#define __NR_timerfd_create 350
|
||||
#define __NR_eventfd 351
|
||||
#define __NR_fallocate 352
|
||||
#define __NR_timerfd_settime 353
|
||||
#define __NR_timerfd_gettime 354
|
||||
#define __NR_signalfd4 355
|
||||
#define __NR_eventfd2 356
|
||||
#define __NR_epoll_create1 357
|
||||
#define __NR_dup3 358
|
||||
#define __NR_pipe2 359
|
||||
#define __NR_inotify_init1 360
|
||||
#define __NR_preadv 361
|
||||
#define __NR_pwritev 362
|
||||
#define __NR_rt_tgsigqueueinfo 363
|
||||
#define __NR_perf_event_open 364
|
||||
#define __NR_recvmmsg 365
|
||||
#define __NR_accept4 366
|
||||
#define __NR_fanotify_init 367
|
||||
#define __NR_fanotify_mark 368
|
||||
#define __NR_prlimit64 369
|
||||
#define __NR_name_to_handle_at 370
|
||||
#define __NR_open_by_handle_at 371
|
||||
#define __NR_clock_adjtime 372
|
||||
#define __NR_syncfs 373
|
||||
#define __NR_sendmmsg 374
|
||||
#define __NR_setns 375
|
||||
#define __NR_process_vm_readv 376
|
||||
#define __NR_process_vm_writev 377
|
||||
#define __NR_kcmp 378
|
||||
#define __NR_finit_module 379
|
||||
#define __NR_sched_getattr 380
|
||||
#define __NR_sched_setattr 381
|
||||
#define __NR_renameat2 382
|
||||
#define __NR_seccomp 383
|
||||
#define __NR_getrandom 384
|
||||
#define __NR_memfd_create 385
|
||||
#define __NR_bpf 386
|
||||
#define __NR_execveat 387
|
||||
#define __NR_userfaultfd 388
|
||||
#define __NR_membarrier 389
|
||||
#define __NR_mlock2 390
|
||||
#define __NR_copy_file_range 391
|
||||
#define __NR_preadv2 392
|
||||
#define __NR_pwritev2 393
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#define __NR_syscalls 394
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SH_UNISTD_64_H */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
# Makefile for the Linux/SuperH kernel.
|
||||
#
|
||||
|
||||
extra-y := head_$(BITS).o vmlinux.lds
|
||||
extra-y := head_32.o vmlinux.lds
|
||||
|
||||
ifdef CONFIG_FUNCTION_TRACER
|
||||
# Do not profile debug and lowlevel utilities
|
||||
|
|
@ -13,26 +13,26 @@ endif
|
|||
CFLAGS_REMOVE_return_address.o = -pg
|
||||
|
||||
obj-y := debugtraps.o dumpstack.o \
|
||||
idle.o io.o irq.o irq_$(BITS).o kdebugfs.o \
|
||||
idle.o io.o irq.o irq_32.o kdebugfs.o \
|
||||
machvec.o nmi_debug.o process.o \
|
||||
process_$(BITS).o ptrace.o ptrace_$(BITS).o \
|
||||
process_32.o ptrace.o ptrace_32.o \
|
||||
reboot.o return_address.o \
|
||||
setup.o signal_$(BITS).o sys_sh.o \
|
||||
syscalls_$(BITS).o time.o topology.o traps.o \
|
||||
traps_$(BITS).o unwinder.o
|
||||
setup.o signal_32.o sys_sh.o \
|
||||
syscalls_32.o time.o topology.o traps.o \
|
||||
traps_32.o unwinder.o
|
||||
|
||||
ifndef CONFIG_GENERIC_IOMAP
|
||||
obj-y += iomap.o
|
||||
obj-$(CONFIG_HAS_IOPORT_MAP) += ioport.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_SUPERH32) += sys_sh32.o
|
||||
obj-y += sys_sh32.o
|
||||
obj-y += cpu/
|
||||
obj-$(CONFIG_VSYSCALL) += vsyscall/
|
||||
obj-$(CONFIG_SMP) += smp.o
|
||||
obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o
|
||||
obj-$(CONFIG_KGDB) += kgdb.o
|
||||
obj-$(CONFIG_MODULES) += sh_ksyms_$(BITS).o module.o
|
||||
obj-$(CONFIG_MODULES) += sh_ksyms_32.o module.o
|
||||
obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
|
||||
obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
|
||||
obj-$(CONFIG_STACKTRACE) += stacktrace.o
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@ obj-$(CONFIG_CPU_SH2) = sh2/
|
|||
obj-$(CONFIG_CPU_SH2A) = sh2a/
|
||||
obj-$(CONFIG_CPU_SH3) = sh3/
|
||||
obj-$(CONFIG_CPU_SH4) = sh4/
|
||||
obj-$(CONFIG_CPU_SH5) = sh5/
|
||||
|
||||
# Special cases for family ancestry.
|
||||
|
||||
|
|
|
|||
|
|
@ -103,7 +103,7 @@ void __attribute__ ((weak)) l2_cache_init(void)
|
|||
/*
|
||||
* Generic first-level cache init
|
||||
*/
|
||||
#if defined(CONFIG_SUPERH32) && !defined(CONFIG_CPU_J2)
|
||||
#if !defined(CONFIG_CPU_J2)
|
||||
static void cache_init(void)
|
||||
{
|
||||
unsigned long ccr, flags;
|
||||
|
|
|
|||
|
|
@ -2,6 +2,5 @@
|
|||
#
|
||||
# Makefile for the Linux/SuperH CPU-specific IRQ handlers.
|
||||
#
|
||||
obj-$(CONFIG_SUPERH32) += imask.o
|
||||
obj-$(CONFIG_CPU_SH5) += intc-sh5.o
|
||||
obj-y += imask.o
|
||||
obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
|
||||
|
|
|
|||
|
|
@ -1,194 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* arch/sh/kernel/cpu/irq/intc-sh5.c
|
||||
*
|
||||
* Interrupt Controller support for SH5 INTC.
|
||||
*
|
||||
* Copyright (C) 2000, 2001 Paolo Alberelli
|
||||
* Copyright (C) 2003 Paul Mundt
|
||||
*
|
||||
* Per-interrupt selective. IRLM=0 (Fixed priority) is not
|
||||
* supported being useless without a cascaded interrupt
|
||||
* controller.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <cpu/irq.h>
|
||||
#include <asm/page.h>
|
||||
|
||||
/*
|
||||
* Maybe the generic Peripheral block could move to a more
|
||||
* generic include file. INTC Block will be defined here
|
||||
* and only here to make INTC self-contained in a single
|
||||
* file.
|
||||
*/
|
||||
#define INTC_BLOCK_OFFSET 0x01000000
|
||||
|
||||
/* Base */
|
||||
#define INTC_BASE PHYS_PERIPHERAL_BLOCK + \
|
||||
INTC_BLOCK_OFFSET
|
||||
|
||||
/* Address */
|
||||
#define INTC_ICR_SET (intc_virt + 0x0)
|
||||
#define INTC_ICR_CLEAR (intc_virt + 0x8)
|
||||
#define INTC_INTPRI_0 (intc_virt + 0x10)
|
||||
#define INTC_INTSRC_0 (intc_virt + 0x50)
|
||||
#define INTC_INTSRC_1 (intc_virt + 0x58)
|
||||
#define INTC_INTREQ_0 (intc_virt + 0x60)
|
||||
#define INTC_INTREQ_1 (intc_virt + 0x68)
|
||||
#define INTC_INTENB_0 (intc_virt + 0x70)
|
||||
#define INTC_INTENB_1 (intc_virt + 0x78)
|
||||
#define INTC_INTDSB_0 (intc_virt + 0x80)
|
||||
#define INTC_INTDSB_1 (intc_virt + 0x88)
|
||||
|
||||
#define INTC_ICR_IRLM 0x1
|
||||
#define INTC_INTPRI_PREGS 8 /* 8 Priority Registers */
|
||||
#define INTC_INTPRI_PPREG 8 /* 8 Priorities per Register */
|
||||
|
||||
|
||||
/*
|
||||
* Mapper between the vector ordinal and the IRQ number
|
||||
* passed to kernel/device drivers.
|
||||
*/
|
||||
int intc_evt_to_irq[(0xE20/0x20)+1] = {
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* 0x000 - 0x0E0 */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* 0x100 - 0x1E0 */
|
||||
0, 0, 0, 0, 0, 1, 0, 0, /* 0x200 - 0x2E0 */
|
||||
2, 0, 0, 3, 0, 0, 0, -1, /* 0x300 - 0x3E0 */
|
||||
32, 33, 34, 35, 36, 37, 38, -1, /* 0x400 - 0x4E0 */
|
||||
-1, -1, -1, 63, -1, -1, -1, -1, /* 0x500 - 0x5E0 */
|
||||
-1, -1, 18, 19, 20, 21, 22, -1, /* 0x600 - 0x6E0 */
|
||||
39, 40, 41, 42, -1, -1, -1, -1, /* 0x700 - 0x7E0 */
|
||||
4, 5, 6, 7, -1, -1, -1, -1, /* 0x800 - 0x8E0 */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* 0x900 - 0x9E0 */
|
||||
12, 13, 14, 15, 16, 17, -1, -1, /* 0xA00 - 0xAE0 */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* 0xB00 - 0xBE0 */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* 0xC00 - 0xCE0 */
|
||||
-1, -1, -1, -1, -1, -1, -1, -1, /* 0xD00 - 0xDE0 */
|
||||
-1, -1 /* 0xE00 - 0xE20 */
|
||||
};
|
||||
|
||||
static unsigned long intc_virt;
|
||||
static int irlm; /* IRL mode */
|
||||
|
||||
static void enable_intc_irq(struct irq_data *data)
|
||||
{
|
||||
unsigned int irq = data->irq;
|
||||
unsigned long reg;
|
||||
unsigned long bitmask;
|
||||
|
||||
if ((irq <= IRQ_IRL3) && (irlm == NO_PRIORITY))
|
||||
printk("Trying to use straight IRL0-3 with an encoding platform.\n");
|
||||
|
||||
if (irq < 32) {
|
||||
reg = INTC_INTENB_0;
|
||||
bitmask = 1 << irq;
|
||||
} else {
|
||||
reg = INTC_INTENB_1;
|
||||
bitmask = 1 << (irq - 32);
|
||||
}
|
||||
|
||||
__raw_writel(bitmask, reg);
|
||||
}
|
||||
|
||||
static void disable_intc_irq(struct irq_data *data)
|
||||
{
|
||||
unsigned int irq = data->irq;
|
||||
unsigned long reg;
|
||||
unsigned long bitmask;
|
||||
|
||||
if (irq < 32) {
|
||||
reg = INTC_INTDSB_0;
|
||||
bitmask = 1 << irq;
|
||||
} else {
|
||||
reg = INTC_INTDSB_1;
|
||||
bitmask = 1 << (irq - 32);
|
||||
}
|
||||
|
||||
__raw_writel(bitmask, reg);
|
||||
}
|
||||
|
||||
static struct irq_chip intc_irq_type = {
|
||||
.name = "INTC",
|
||||
.irq_enable = enable_intc_irq,
|
||||
.irq_disable = disable_intc_irq,
|
||||
};
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
|
||||
unsigned long reg;
|
||||
int i;
|
||||
|
||||
intc_virt = (unsigned long)ioremap(INTC_BASE, 1024);
|
||||
if (!intc_virt) {
|
||||
panic("Unable to remap INTC\n");
|
||||
}
|
||||
|
||||
|
||||
/* Set default: per-line enable/disable, priority driven ack/eoi */
|
||||
for (i = 0; i < NR_INTC_IRQS; i++)
|
||||
irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
|
||||
|
||||
|
||||
/* Disable all interrupts and set all priorities to 0 to avoid trouble */
|
||||
__raw_writel(-1, INTC_INTDSB_0);
|
||||
__raw_writel(-1, INTC_INTDSB_1);
|
||||
|
||||
for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
|
||||
__raw_writel( NO_PRIORITY, reg);
|
||||
|
||||
|
||||
#ifdef CONFIG_SH_CAYMAN
|
||||
{
|
||||
unsigned long data;
|
||||
|
||||
/* Set IRLM */
|
||||
/* If all the priorities are set to 'no priority', then
|
||||
* assume we are using encoded mode.
|
||||
*/
|
||||
irlm = platform_int_priority[IRQ_IRL0] +
|
||||
platform_int_priority[IRQ_IRL1] +
|
||||
platform_int_priority[IRQ_IRL2] +
|
||||
platform_int_priority[IRQ_IRL3];
|
||||
if (irlm == NO_PRIORITY) {
|
||||
/* IRLM = 0 */
|
||||
reg = INTC_ICR_CLEAR;
|
||||
i = IRQ_INTA;
|
||||
printk("Trying to use encoded IRL0-3. IRLs unsupported.\n");
|
||||
} else {
|
||||
/* IRLM = 1 */
|
||||
reg = INTC_ICR_SET;
|
||||
i = IRQ_IRL0;
|
||||
}
|
||||
__raw_writel(INTC_ICR_IRLM, reg);
|
||||
|
||||
/* Set interrupt priorities according to platform description */
|
||||
for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
|
||||
data |= platform_int_priority[i] <<
|
||||
((i % INTC_INTPRI_PPREG) * 4);
|
||||
if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
|
||||
/* Upon the 7th, set Priority Register */
|
||||
__raw_writel(data, reg);
|
||||
data = 0;
|
||||
reg += 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* And now let interrupts come in.
|
||||
* sti() is not enough, we need to
|
||||
* lower priority, too.
|
||||
*/
|
||||
__asm__ __volatile__("getcon " __SR ", %0\n\t"
|
||||
"and %0, %1, %0\n\t"
|
||||
"putcon %0, " __SR "\n\t"
|
||||
: "=&r" (__dummy0)
|
||||
: "r" (__dummy1));
|
||||
}
|
||||
|
|
@ -24,7 +24,6 @@ static const char *cpu_name[] = {
|
|||
[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
|
||||
[CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757",
|
||||
[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
|
||||
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
|
||||
[CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
|
||||
[CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
|
||||
[CPU_SH7372] = "SH7372", [CPU_SH7734] = "SH7734",
|
||||
|
|
|
|||
|
|
@ -391,6 +391,7 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
|
|||
&tmu0_device,
|
||||
&tmu1_device,
|
||||
&tmu2_device,
|
||||
&tmu3_device,
|
||||
};
|
||||
|
||||
static struct platform_device *sh7786_devices[] __initdata = {
|
||||
|
|
|
|||
|
|
@ -1,16 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Makefile for the Linux/SuperH SH-5 backends.
|
||||
#
|
||||
obj-y := entry.o probe.o switchto.o
|
||||
|
||||
obj-$(CONFIG_SH_FPU) += fpu.o
|
||||
obj-$(CONFIG_KALLSYMS) += unwind.o
|
||||
|
||||
# CPU subtype setup
|
||||
obj-$(CONFIG_CPU_SH5) += setup-sh5.o
|
||||
|
||||
# Primary on-chip clocks (common)
|
||||
clock-$(CONFIG_CPU_SH5) := clock-sh5.o
|
||||
|
||||
obj-y += $(clock-y)
|
||||
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