i.MX arm64 device tree update for 5.9:
- Update i.MX8M OCOTP device node name to match .yaml schema. - Add ftm_alarm0 device support for layerscape SoCs. - Add DSPI controller support for lx2160a device. - A series from Peng Fan to add aliases for various devices on i.MX8 SoCs. - Add Hantro G1/G2 VPU device support for imx8mq. - Add more thermal zone support for ls1028a, ls1043a and ls1046a. - Other small random changes. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl8VVUkUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM4J8wf+JD5crdfw+/458BsgX30HBfgd++CG RRJxeqx3CkHsPyMAza9wKWPZDASIDQaWIA3CKf2niQyR7jKxAd9JdMw+hBBMoG+I 4+uMRictK98rODP4bcGlLtUjdoncjCuAoa58tKSAiZ+SAEjlb5UHCXpbKtrPtQuY r4v+ODV82U1gIdDaZeOS1L40iQHwGO5/Aq+Ua8UvraoMTgHMW6Il86XlbE3Gk1Ql YrqAteG9SJm5cFRbrmmKisA3rLZoYqYYZ1Tb66kDKBrmTTzZTBmHE+5SE7DJwFh5 c74BHkARhw0lXhpQzcEK9jnR88+ZUqL+qbteVmotB4+54WbFrJEJ4/BejA== =sjzz -----END PGP SIGNATURE----- Merge tag 'imx-dt64-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX arm64 device tree update for 5.9: - Update i.MX8M OCOTP device node name to match .yaml schema. - Add ftm_alarm0 device support for layerscape SoCs. - Add DSPI controller support for lx2160a device. - A series from Peng Fan to add aliases for various devices on i.MX8 SoCs. - Add Hantro G1/G2 VPU device support for imx8mq. - Add more thermal zone support for ls1028a, ls1043a and ls1046a. - Other small random changes. * tag 'imx-dt64-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (26 commits) arm64: dts: lx2160a-rdb: fix shunt-resistor value arm64: dts: ls1028a-qds: Add DSPI flash nodes arm64: dts: lx2160a: Increase configuration space size arm64: dts: zii-ultra: update MDIO speed and preamble arm64: dts: ls1043a: update USB nodes status to match board config arm64: dts: imx8mn-evk: add pca9450 for i.mx8mn-evk board arm64: dts: imx8mp: add ddr pmu device node arm64: dts: ls1043a: add more thermal zone support arm64: dts: ls1046a: add more thermal zone support arm64: dts: layerscape: add ftm_alarm0 node arm64: dts: ls1028a: Add ftm_alarm0 DT node arm64: dts: lx2160a: add ftm_alarm0 DT node arm64: dts: lx2160a: add DT node for all DSPI controller arm64: dts: lx2160a: add dspi controller DT nodes arm64: dts: imx8mp: Add fallback compatible to ocotp node arm64: dts: imx8qxp: Add ethernet alias arm64: dts: imx8qxp: add i2c aliases arm64: dts: imx8qxp: add alias for lsio MU arm64: dts: imx8m: add mu node arm64: dts: imx8m: change ocotp node name on i.MX8M SoCs ... Link: https://lore.kernel.org/r/20200720085536.24138-4-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
3b796abd30
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|
@ -17,6 +17,7 @@
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|||
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aliases {
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crypto = &crypto;
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rtc1 = &ftm_alarm0;
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rtic-a = &rtic_a;
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rtic-b = &rtic_b;
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rtic-c = &rtic_c;
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@ -512,6 +513,20 @@
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<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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|
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rcpm: power-controller@1ee2140 {
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compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
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reg = <0x0 0x1ee2140 0x0 0x4>;
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#fsl,rcpm-wakeup-cells = <1>;
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};
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ftm_alarm0: timer@29d0000 {
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compatible = "fsl,ls1012a-ftm-alarm";
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reg = <0x0 0x29d0000 0x0 0x10000>;
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fsl,rcpm-wakeup = <&rcpm 0x20000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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big-endian;
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};
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};
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firmware {
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@ -107,6 +107,91 @@
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};
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};
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-cpol;
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spi-cpha;
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reg = <0>;
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spi-max-frequency = <10000000>;
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};
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flash@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-cpol;
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spi-cpha;
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reg = <1>;
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spi-max-frequency = <10000000>;
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};
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flash@2 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-cpol;
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spi-cpha;
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reg = <2>;
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spi-max-frequency = <10000000>;
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};
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};
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&dspi1 {
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bus-num = <1>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-cpol;
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spi-cpha;
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reg = <0>;
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spi-max-frequency = <10000000>;
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};
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flash@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-cpol;
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spi-cpha;
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reg = <1>;
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spi-max-frequency = <10000000>;
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};
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flash@2 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-cpol;
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spi-cpha;
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reg = <2>;
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spi-max-frequency = <10000000>;
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};
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};
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&dspi2 {
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bus-num = <2>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-cpol;
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spi-cpha;
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reg = <0>;
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spi-max-frequency = <10000000>;
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};
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};
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&duart0 {
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status = "okay";
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};
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@ -17,6 +17,10 @@
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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rtc1 = &ftm_alarm0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -129,11 +133,31 @@
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};
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thermal-zones {
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core-cluster {
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ddr-controller {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 0>;
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trips {
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ddr-ctrler-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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ddr-ctrler-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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core-cluster {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 1>;
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trips {
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core_cluster_alert: core-cluster-alert {
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temperature = <85000>;
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@ -983,6 +1007,19 @@
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};
|
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};
|
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};
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rcpm: power-controller@1e34040 {
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compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
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reg = <0x0 0x1e34040 0x0 0x1c>;
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#fsl,rcpm-wakeup-cells = <7>;
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};
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ftm_alarm0: timer@2800000 {
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compatible = "fsl,ls1028a-ftm-alarm";
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reg = <0x0 0x2800000 0x0 0x10000>;
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fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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malidp0: display@f080000 {
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@ -148,4 +148,8 @@
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};
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};
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&usb0 {
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status = "okay";
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};
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#include "fsl-ls1043-post.dtsi"
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@ -209,3 +209,11 @@
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fsl,tdm-interface;
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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@ -27,6 +27,7 @@
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ethernet4 = &enet4;
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ethernet5 = &enet5;
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ethernet6 = &enet6;
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rtc1 = &ftm_alarm0;
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};
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cpus {
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@ -149,19 +150,79 @@
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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ddr-controller {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 3>;
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thermal-sensors = <&tmu 0>;
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trips {
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cpu_alert: cpu-alert {
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ddr-ctrler-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu-crit {
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ddr-ctrler-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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serdes {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 1>;
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trips {
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serdes-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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serdes-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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fman {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 2>;
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trips {
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fman-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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fman-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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core-cluster {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 3>;
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trips {
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core_cluster_alert: core-cluster-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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core_cluster_crit: core-cluster-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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@ -170,7 +231,7 @@
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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trip = <&core_cluster_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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|
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@ -179,6 +240,26 @@
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};
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};
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};
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sec {
|
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 4>;
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|
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trips {
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sec-alert {
|
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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|
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sec-crit {
|
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temperature = <95000>;
|
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hysteresis = <2000>;
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type = "critical";
|
||||
};
|
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};
|
||||
};
|
||||
};
|
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|
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timer {
|
||||
|
|
@ -677,6 +758,7 @@
|
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snps,quirk-frame-length-adjustment = <0x20>;
|
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snps,dis_rxdet_inp3_quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb1: usb3@3000000 {
|
||||
|
|
@ -687,6 +769,7 @@
|
|||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2: usb3@3100000 {
|
||||
|
|
@ -697,6 +780,7 @@
|
|||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
|
|
@ -829,6 +913,19 @@
|
|||
big-endian;
|
||||
};
|
||||
|
||||
rcpm: power-controller@1ee2140 {
|
||||
compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
|
||||
reg = <0x0 0x1ee2140 0x0 0x4>;
|
||||
#fsl,rcpm-wakeup-cells = <1>;
|
||||
};
|
||||
|
||||
ftm_alarm0: timer@29d0000 {
|
||||
compatible = "fsl,ls1043a-ftm-alarm";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>;
|
||||
fsl,rcpm-wakeup = <&rcpm 0x20000>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
ethernet5 = &enet5;
|
||||
ethernet6 = &enet6;
|
||||
ethernet7 = &enet7;
|
||||
rtc1 = &ftm_alarm0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -117,19 +118,79 @@
|
|||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
ddr-controller {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 3>;
|
||||
thermal-sensors = <&tmu 0>;
|
||||
|
||||
trips {
|
||||
cpu_alert: cpu-alert {
|
||||
ddr-ctrler-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit: cpu-crit {
|
||||
ddr-ctrler-crit {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serdes {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 1>;
|
||||
|
||||
trips {
|
||||
serdes-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
serdes-crit {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fman {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 2>;
|
||||
|
||||
trips {
|
||||
fman-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
fman-crit {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
core-cluster {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 3>;
|
||||
|
||||
trips {
|
||||
core_cluster_alert: core-cluster-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
core_cluster_crit: core-cluster-crit {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
|
|
@ -138,7 +199,7 @@
|
|||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert>;
|
||||
trip = <&core_cluster_alert>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
|
|
@ -147,6 +208,26 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
sec {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 4>;
|
||||
|
||||
trips {
|
||||
sec-alert {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
sec-crit {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
|
|
@ -765,6 +846,20 @@
|
|||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
rcpm: power-controller@1ee2140 {
|
||||
compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
|
||||
reg = <0x0 0x1ee2140 0x0 0x4>;
|
||||
#fsl,rcpm-wakeup-cells = <1>;
|
||||
};
|
||||
|
||||
ftm_alarm0: timer@29d0000 {
|
||||
compatible = "fsl,ls1046a-ftm-alarm";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>;
|
||||
fsl,rcpm-wakeup = <&rcpm 0x20000>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
rtc1 = &ftm_alarm0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -781,6 +782,19 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
rcpm: power-controller@1e34040 {
|
||||
compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
|
||||
reg = <0x0 0x1e34040 0x0 0x18>;
|
||||
#fsl,rcpm-wakeup-cells = <6>;
|
||||
};
|
||||
|
||||
ftm_alarm0: timer@2800000 {
|
||||
compatible = "fsl,ls1088a-ftm-alarm";
|
||||
reg = <0x0 0x2800000 0x0 0x10000>;
|
||||
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
rtc1 = &ftm_alarm0;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
|
|
@ -763,6 +764,19 @@
|
|||
reg = <0x0 0x04000000 0x0 0x01000000>;
|
||||
interrupts = <0 12 4>;
|
||||
};
|
||||
|
||||
rcpm: power-controller@1e34040 {
|
||||
compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
|
||||
reg = <0x0 0x1e34040 0x0 0x18>;
|
||||
#fsl,rcpm-wakeup-cells = <6>;
|
||||
};
|
||||
|
||||
ftm_alarm0: timer@2800000 {
|
||||
compatible = "fsl,ls208xa-ftm-alarm";
|
||||
reg = <0x0 0x2800000 0x0 0x10000>;
|
||||
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
ddr1: memory-controller@1080000 {
|
||||
|
|
|
|||
|
|
@ -35,6 +35,42 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&dspi0 {
|
||||
status = "okay";
|
||||
|
||||
dflash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&dspi1 {
|
||||
status = "okay";
|
||||
|
||||
dflash1: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&dspi2 {
|
||||
status = "okay";
|
||||
|
||||
dflash2: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -121,7 +121,7 @@
|
|||
power-monitor@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
shunt-resistor = <500>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
//
|
||||
// Device Tree Include file for Layerscape-LX2160A family SoC.
|
||||
//
|
||||
// Copyright 2018 NXP
|
||||
// Copyright 2018-2020 NXP
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
|
@ -16,6 +16,10 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
rtc1 = &ftm_alarm0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -777,6 +781,45 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi0: spi@2100000 {
|
||||
compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 7>;
|
||||
clock-names = "dspi";
|
||||
spi-num-chipselects = <5>;
|
||||
bus-num = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi1: spi@2110000 {
|
||||
compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2110000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 7>;
|
||||
clock-names = "dspi";
|
||||
spi-num-chipselects = <5>;
|
||||
bus-num = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi2: spi@2120000 {
|
||||
compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2120000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 7>;
|
||||
clock-names = "dspi";
|
||||
spi-num-chipselects = <5>;
|
||||
bus-num = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc0: esdhc@2140000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x0 0x2140000 0x0 0x10000>;
|
||||
|
|
@ -888,6 +931,20 @@
|
|||
timeout-sec = <30>;
|
||||
};
|
||||
|
||||
rcpm: power-controller@1e34040 {
|
||||
compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
|
||||
reg = <0x0 0x1e34040 0x0 0x1c>;
|
||||
#fsl,rcpm-wakeup-cells = <7>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
ftm_alarm0: timer@2800000 {
|
||||
compatible = "fsl,lx2160a-ftm-alarm";
|
||||
reg = <0x0 0x2800000 0x0 0x10000>;
|
||||
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
usb0: usb@3100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
|
|
@ -957,7 +1014,7 @@
|
|||
pcie@3400000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x80 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
|
|
@ -985,7 +1042,7 @@
|
|||
pcie@3500000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x88 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
|
|
@ -1013,7 +1070,7 @@
|
|||
pcie@3600000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x90 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
0x90 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
|
|
@ -1041,7 +1098,7 @@
|
|||
pcie@3700000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
|
||||
0x98 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
0x98 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
|
|
@ -1069,7 +1126,7 @@
|
|||
pcie@3800000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
|
||||
0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
|
|
@ -1097,7 +1154,7 @@
|
|||
pcie@3900000 {
|
||||
compatible = "fsl,lx2160a-pcie";
|
||||
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
|
||||
0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
|
||||
0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "csr_axi_slave", "config_axi_slave";
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
|
|
|
|||
|
|
@ -18,10 +18,18 @@
|
|||
|
||||
aliases {
|
||||
ethernet0 = &fec1;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
|
|
@ -29,14 +37,6 @@
|
|||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &ecspi3;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -467,7 +467,7 @@
|
|||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
ocotp: efuse@30350000 {
|
||||
compatible = "fsl,imx8mm-ocotp", "syscon";
|
||||
reg = <0x30350000 0x10000>;
|
||||
clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
|
||||
|
|
@ -775,6 +775,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
mu: mailbox@30aa0000 {
|
||||
compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
|
||||
reg = <0x30aa0000 0x10000>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_MU_ROOT>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
usdhc1: mmc@30b40000 {
|
||||
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
|
|
|
|||
|
|
@ -13,6 +13,102 @@
|
|||
compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pmic: pmic@25 {
|
||||
compatible = "nxp,pca9450b";
|
||||
reg = <0x25>;
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 GPIO_ACTIVE_LOW>;
|
||||
|
||||
regulators {
|
||||
buck1: BUCK1{
|
||||
regulator-name = "BUCK1";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
buck2: BUCK2 {
|
||||
regulator-name = "BUCK2";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
nxp,dvs-run-voltage = <950000>;
|
||||
nxp,dvs-standby-voltage = <850000>;
|
||||
};
|
||||
|
||||
buck4: BUCK4{
|
||||
regulator-name = "BUCK4";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5: BUCK5{
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6: BUCK6 {
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2: LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3: LDO3 {
|
||||
regulator-name = "LDO3";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4: LDO4 {
|
||||
regulator-name = "LDO4";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5: LDO5 {
|
||||
regulator-name = "LDO5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
/delete-property/operating-points-v2;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -223,6 +223,12 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicirq {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
|
|
|
|||
|
|
@ -374,7 +374,7 @@
|
|||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
ocotp: efuse@30350000 {
|
||||
compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
|
||||
reg = <0x30350000 0x10000>;
|
||||
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
|
||||
|
|
@ -675,6 +675,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
mu: mailbox@30aa0000 {
|
||||
compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
|
||||
reg = <0x30aa0000 0x10000>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_MU_ROOT>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
usdhc1: mmc@30b40000 {
|
||||
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x30b40000 0x10000>;
|
||||
|
|
|
|||
|
|
@ -23,6 +23,12 @@
|
|||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
i2c4 = &i2c5;
|
||||
i2c5 = &i2c6;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
|
|
@ -307,8 +313,8 @@
|
|||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
compatible = "fsl,imx8mp-ocotp", "syscon";
|
||||
ocotp: efuse@30350000 {
|
||||
compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
|
||||
reg = <0x30350000 0x10000>;
|
||||
clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
|
||||
/* For nvmem subnodes */
|
||||
|
|
@ -621,6 +627,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
mu: mailbox@30aa0000 {
|
||||
compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
|
||||
reg = <0x30aa0000 0x10000>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MP_CLK_MU_ROOT>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
i2c5: i2c@30ad0000 {
|
||||
compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -730,5 +744,11 @@
|
|||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
ddr-pmu@3d800000 {
|
||||
compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
|
||||
reg = <0x3d800000 0x400000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -131,6 +131,8 @@
|
|||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <12500000>;
|
||||
suppress-preamble;
|
||||
status = "okay";
|
||||
|
||||
switch: switch@0 {
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &fec1;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
|
|
@ -29,6 +30,8 @@
|
|||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
|
|
@ -539,7 +542,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
ocotp: efuse@30350000 {
|
||||
compatible = "fsl,imx8mq-ocotp", "syscon";
|
||||
reg = <0x30350000 0x10000>;
|
||||
clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
|
||||
|
|
@ -675,6 +678,7 @@
|
|||
pgc_vpu: power-domain@6 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8M_POWER_DOMAIN_VPU>;
|
||||
clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
|
||||
};
|
||||
|
||||
pgc_disp: power-domain@7 {
|
||||
|
|
@ -959,6 +963,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
mu: mailbox@30aa0000 {
|
||||
compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
|
||||
reg = <0x30aa0000 0x10000>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
usdhc1: mmc@30b40000 {
|
||||
compatible = "fsl,imx8mq-usdhc",
|
||||
"fsl,imx7d-usdhc";
|
||||
|
|
@ -1142,6 +1154,32 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
vpu: video-codec@38300000 {
|
||||
compatible = "nxp,imx8mq-vpu";
|
||||
reg = <0x38300000 0x10000>,
|
||||
<0x38310000 0x10000>,
|
||||
<0x38320000 0x10000>;
|
||||
reg-names = "g1", "g2", "ctrl";
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "g1", "g2";
|
||||
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
|
||||
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
|
||||
clock-names = "g1", "g2", "bus";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
|
||||
<&clk IMX8MQ_CLK_VPU_G2>,
|
||||
<&clk IMX8MQ_CLK_VPU_BUS>,
|
||||
<&clk IMX8MQ_VPU_PLL_BYPASS>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
|
||||
<&clk IMX8MQ_VPU_PLL_OUT>,
|
||||
<&clk IMX8MQ_SYS1_PLL_800M>,
|
||||
<&clk IMX8MQ_VPU_PLL>;
|
||||
assigned-clock-rates = <600000000>, <600000000>,
|
||||
<800000000>, <0>;
|
||||
power-domains = <&pgc_vpu>;
|
||||
};
|
||||
|
||||
pcie0: pcie@33800000 {
|
||||
compatible = "fsl,imx8mq-pcie";
|
||||
reg = <0x33800000 0x400000>,
|
||||
|
|
|
|||
|
|
@ -19,6 +19,8 @@
|
|||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &fec1;
|
||||
ethernet1 = &fec2;
|
||||
gpio0 = &lsio_gpio0;
|
||||
gpio1 = &lsio_gpio1;
|
||||
gpio2 = &lsio_gpio2;
|
||||
|
|
@ -27,10 +29,18 @@
|
|||
gpio5 = &lsio_gpio5;
|
||||
gpio6 = &lsio_gpio6;
|
||||
gpio7 = &lsio_gpio7;
|
||||
i2c0 = &adma_i2c0;
|
||||
i2c1 = &adma_i2c1;
|
||||
i2c2 = &adma_i2c2;
|
||||
i2c3 = &adma_i2c3;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
mu0 = &lsio_mu0;
|
||||
mu1 = &lsio_mu1;
|
||||
mu2 = &lsio_mu2;
|
||||
mu3 = &lsio_mu3;
|
||||
mu4 = &lsio_mu4;
|
||||
serial0 = &adma_lpuart0;
|
||||
serial1 = &adma_lpuart1;
|
||||
serial2 = &adma_lpuart2;
|
||||
|
|
|
|||
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