drm/meson: Add G12A support for the DW-HDMI Glue
The Amlogic G12A embeds the same Synopsys DW-HDMI Controller, but with : - a "backport" of the HDR signaling registers from more recent DW-HDMI controllers, this will need a tweak since it's not normally present on this version of the DW-HDMI controller - A direct mapping of TOP and DW-HDMI registers instead of an internal bus accessed using read/write registers - Support for RX-SENSE, but not yet implemented - Support for HDMI 2.1 Dynamic HDR, but not yet implemented - Different registers mapping for the HDMI PHY setup This patchs adds support for these changes while providing exact same support as the previous GXBB, GXL & GXM SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-12-narmstrong@baylibre.com
This commit is contained in:
Neil Armstrong
Родитель
4deb190aa3
Коммит
3b7c1237a7
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@ -20,6 +20,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/component.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/reset.h>
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#include <linux/clk.h>
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@ -105,6 +106,7 @@
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#define HDMITX_TOP_ADDR_REG 0x0
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#define HDMITX_TOP_DATA_REG 0x4
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#define HDMITX_TOP_CTRL_REG 0x8
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#define HDMITX_TOP_G12A_OFFSET 0x8000
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/* Controller Communication Channel */
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#define HDMITX_DWC_ADDR_REG 0x10
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@ -118,6 +120,8 @@
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#define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
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#define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
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#define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
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#define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
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#define HHI_HDMI_PHY_CNTL5 0x3b4 /* 0xed */
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static DEFINE_SPINLOCK(reg_lock);
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@ -127,12 +131,26 @@ enum meson_venc_source {
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MESON_VENC_SOURCE_ENCP = 2,
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};
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struct meson_dw_hdmi;
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struct meson_dw_hdmi_data {
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unsigned int (*top_read)(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr);
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void (*top_write)(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data);
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unsigned int (*dwc_read)(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr);
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void (*dwc_write)(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data);
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};
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struct meson_dw_hdmi {
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struct drm_encoder encoder;
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struct dw_hdmi_plat_data dw_plat_data;
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struct meson_drm *priv;
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struct device *dev;
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void __iomem *hdmitx;
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const struct meson_dw_hdmi_data *data;
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struct reset_control *hdmitx_apb;
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struct reset_control *hdmitx_ctrl;
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struct reset_control *hdmitx_phy;
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@ -174,6 +192,12 @@ static unsigned int dw_hdmi_top_read(struct meson_dw_hdmi *dw_hdmi,
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return data;
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}
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static unsigned int dw_hdmi_g12a_top_read(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr)
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{
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return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
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}
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static inline void dw_hdmi_top_write(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data)
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{
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@ -191,18 +215,24 @@ static inline void dw_hdmi_top_write(struct meson_dw_hdmi *dw_hdmi,
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spin_unlock_irqrestore(®_lock, flags);
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}
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static inline void dw_hdmi_g12a_top_write(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data)
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{
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writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2));
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}
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/* Helper to change specific bits in PHY registers */
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static inline void dw_hdmi_top_write_bits(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr,
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unsigned int mask,
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unsigned int val)
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{
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unsigned int data = dw_hdmi_top_read(dw_hdmi, addr);
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unsigned int data = dw_hdmi->data->top_read(dw_hdmi, addr);
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data &= ~mask;
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data |= val;
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dw_hdmi_top_write(dw_hdmi, addr, data);
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dw_hdmi->data->top_write(dw_hdmi, addr, data);
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}
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static unsigned int dw_hdmi_dwc_read(struct meson_dw_hdmi *dw_hdmi,
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@ -226,6 +256,12 @@ static unsigned int dw_hdmi_dwc_read(struct meson_dw_hdmi *dw_hdmi,
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return data;
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}
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static unsigned int dw_hdmi_g12a_dwc_read(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr)
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{
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return readb(dw_hdmi->hdmitx + addr);
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}
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static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data)
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{
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@ -243,18 +279,24 @@ static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi *dw_hdmi,
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spin_unlock_irqrestore(®_lock, flags);
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}
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static inline void dw_hdmi_g12a_dwc_write(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr, unsigned int data)
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{
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writeb(data, dw_hdmi->hdmitx + addr);
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}
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/* Helper to change specific bits in controller registers */
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static inline void dw_hdmi_dwc_write_bits(struct meson_dw_hdmi *dw_hdmi,
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unsigned int addr,
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unsigned int mask,
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unsigned int val)
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{
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unsigned int data = dw_hdmi_dwc_read(dw_hdmi, addr);
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unsigned int data = dw_hdmi->data->dwc_read(dw_hdmi, addr);
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data &= ~mask;
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data |= val;
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dw_hdmi_dwc_write(dw_hdmi, addr, data);
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dw_hdmi->data->dwc_write(dw_hdmi, addr, data);
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}
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/* Bridge */
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@ -300,6 +342,24 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi *dw_hdmi,
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33632122);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2000115b);
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}
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} else if (dw_hdmi_is_compatible(dw_hdmi,
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"amlogic,meson-g12a-dw-hdmi")) {
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if (pixel_clock >= 371250) {
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/* 5.94Gbps, 3.7125Gbps */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x0000080b);
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} else if (pixel_clock >= 297000) {
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/* 2.97Gbps */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb6262);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003);
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} else {
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/* 1.485Gbps, and below */
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb4242);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
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regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003);
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}
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}
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}
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@ -375,7 +435,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
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regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
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/* Bring out of reset */
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0);
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0);
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/* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
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dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
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@ -384,24 +444,25 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
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0x3 << 4, 0x3 << 4);
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/* Enable normal output to PHY */
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
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/* TMDS pattern setup (TOFIX Handle the YUV420 case) */
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if (mode->clock > 340000) {
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0);
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
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0);
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
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0x03ff03ff);
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} else {
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
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0x001f001f);
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,
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0x001f001f);
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}
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/* Load TMDS pattern */
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);
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msleep(20);
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);
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/* Setup PHY parameters */
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meson_hdmi_phy_setup_mode(dw_hdmi, mode);
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@ -412,7 +473,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
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/* BIT_INVERT */
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if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
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dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi"))
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dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
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dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
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regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
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BIT(17), 0);
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else
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@ -480,7 +542,7 @@ static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
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{
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struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
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return !!dw_hdmi_top_read(dw_hdmi, HDMITX_TOP_STAT0) ?
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return !!dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_STAT0) ?
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connector_status_connected : connector_status_disconnected;
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}
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@ -490,11 +552,11 @@ static void dw_hdmi_setup_hpd(struct dw_hdmi *hdmi,
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struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data;
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/* Setup HPD Filter */
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER,
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER,
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(0xa << 12) | 0xa0);
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/* Clear interrupts */
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
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HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL);
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/* Unmask interrupts */
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@ -515,8 +577,8 @@ static irqreturn_t dw_hdmi_top_irq(int irq, void *dev_id)
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struct meson_dw_hdmi *dw_hdmi = dev_id;
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u32 stat;
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stat = dw_hdmi_top_read(dw_hdmi, HDMITX_TOP_INTR_STAT);
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dw_hdmi_top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat);
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stat = dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_INTR_STAT);
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dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat);
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/* HPD Events, handle in the threaded interrupt handler */
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if (stat & (HDMITX_TOP_INTR_HPD_RISE | HDMITX_TOP_INTR_HPD_FALL)) {
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@ -685,7 +747,9 @@ static const struct drm_encoder_helper_funcs
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static int meson_dw_hdmi_reg_read(void *context, unsigned int reg,
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unsigned int *result)
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{
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*result = dw_hdmi_dwc_read(context, reg);
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struct meson_dw_hdmi *dw_hdmi = context;
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*result = dw_hdmi->data->dwc_read(dw_hdmi, reg);
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return 0;
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@ -694,7 +758,9 @@ static int meson_dw_hdmi_reg_read(void *context, unsigned int reg,
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static int meson_dw_hdmi_reg_write(void *context, unsigned int reg,
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unsigned int val)
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{
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dw_hdmi_dwc_write(context, reg, val);
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struct meson_dw_hdmi *dw_hdmi = context;
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dw_hdmi->data->dwc_write(dw_hdmi, reg, val);
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return 0;
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}
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@ -708,6 +774,20 @@ static const struct regmap_config meson_dw_hdmi_regmap_config = {
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.fast_io = true,
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};
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static const struct meson_dw_hdmi_data meson_dw_hdmi_gx_data = {
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.top_read = dw_hdmi_top_read,
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.top_write = dw_hdmi_top_write,
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.dwc_read = dw_hdmi_dwc_read,
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.dwc_write = dw_hdmi_dwc_write,
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};
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static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
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.top_read = dw_hdmi_g12a_top_read,
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.top_write = dw_hdmi_g12a_top_write,
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.dwc_read = dw_hdmi_g12a_dwc_read,
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.dwc_write = dw_hdmi_g12a_dwc_write,
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};
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static bool meson_hdmi_connector_is_available(struct device *dev)
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{
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struct device_node *ep, *remote;
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@ -734,6 +814,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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const struct meson_dw_hdmi_data *match;
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struct meson_dw_hdmi *meson_dw_hdmi;
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struct drm_device *drm = data;
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struct meson_drm *priv = drm->dev_private;
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@ -750,6 +831,12 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
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return -ENODEV;
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}
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match = of_device_get_match_data(&pdev->dev);
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if (!match) {
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dev_err(&pdev->dev, "failed to get match data\n");
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return -ENODEV;
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}
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meson_dw_hdmi = devm_kzalloc(dev, sizeof(*meson_dw_hdmi),
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GFP_KERNEL);
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if (!meson_dw_hdmi)
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@ -757,6 +844,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
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meson_dw_hdmi->priv = priv;
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meson_dw_hdmi->dev = dev;
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meson_dw_hdmi->data = match;
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dw_plat_data = &meson_dw_hdmi->dw_plat_data;
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encoder = &meson_dw_hdmi->encoder;
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@ -857,24 +945,28 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
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reset_control_reset(meson_dw_hdmi->hdmitx_phy);
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/* Enable APB3 fail on error */
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writel_bits_relaxed(BIT(15), BIT(15),
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meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);
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writel_bits_relaxed(BIT(15), BIT(15),
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meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG);
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if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
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writel_bits_relaxed(BIT(15), BIT(15),
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meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);
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writel_bits_relaxed(BIT(15), BIT(15),
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meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG);
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}
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/* Bring out of reset */
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dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_SW_RESET, 0);
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meson_dw_hdmi->data->top_write(meson_dw_hdmi,
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HDMITX_TOP_SW_RESET, 0);
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msleep(20);
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dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_CLK_CNTL, 0xff);
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meson_dw_hdmi->data->top_write(meson_dw_hdmi,
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HDMITX_TOP_CLK_CNTL, 0xff);
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/* Enable HDMI-TX Interrupt */
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dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
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HDMITX_TOP_INTR_CORE);
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meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
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HDMITX_TOP_INTR_CORE);
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||||
dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN,
|
||||
HDMITX_TOP_INTR_CORE);
|
||||
meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN,
|
||||
HDMITX_TOP_INTR_CORE);
|
||||
|
||||
/* Bridge / Connector */
|
||||
|
||||
|
|
@ -923,9 +1015,14 @@ static int meson_dw_hdmi_remove(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static const struct of_device_id meson_dw_hdmi_of_table[] = {
|
||||
{ .compatible = "amlogic,meson-gxbb-dw-hdmi" },
|
||||
{ .compatible = "amlogic,meson-gxl-dw-hdmi" },
|
||||
{ .compatible = "amlogic,meson-gxm-dw-hdmi" },
|
||||
{ .compatible = "amlogic,meson-gxbb-dw-hdmi",
|
||||
.data = &meson_dw_hdmi_gx_data },
|
||||
{ .compatible = "amlogic,meson-gxl-dw-hdmi",
|
||||
.data = &meson_dw_hdmi_gx_data },
|
||||
{ .compatible = "amlogic,meson-gxm-dw-hdmi",
|
||||
.data = &meson_dw_hdmi_gx_data },
|
||||
{ .compatible = "amlogic,meson-g12a-dw-hdmi",
|
||||
.data = &meson_dw_hdmi_g12a_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, meson_dw_hdmi_of_table);
|
||||
|
|
|
|||
|
|
@ -21,9 +21,12 @@
|
|||
#define __MESON_DW_HDMI_H
|
||||
|
||||
/*
|
||||
* Bit 7 RW Reserved. Default 1.
|
||||
* Bit 6 RW Reserved. Default 1.
|
||||
* Bit 5 RW Reserved. Default 1.
|
||||
* Bit 15-10: RW Reserved. Default 1 starting from G12A
|
||||
* Bit 9 RW sw_reset_i2c starting from G12A
|
||||
* Bit 8 RW sw_reset_axiarb starting from G12A
|
||||
* Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
|
||||
* Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
|
||||
* Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
|
||||
* Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
|
||||
* Default 1.
|
||||
* Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
|
||||
|
|
@ -39,12 +42,16 @@
|
|||
#define HDMITX_TOP_SW_RESET (0x000)
|
||||
|
||||
/*
|
||||
* Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable
|
||||
* Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
|
||||
* Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
|
||||
* Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
|
||||
* Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
|
||||
* Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
|
||||
* Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0.
|
||||
* Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable
|
||||
* Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable
|
||||
* Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable
|
||||
* Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A
|
||||
* Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
|
||||
* Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
|
||||
* Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0.
|
||||
|
|
@ -53,6 +60,8 @@
|
|||
#define HDMITX_TOP_CLK_CNTL (0x001)
|
||||
|
||||
/*
|
||||
* Bit 31:28 RW rxsense_glitch_width: starting from G12A
|
||||
* Bit 27:16 RW rxsense_valid_width: starting from G12A
|
||||
* Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0.
|
||||
* Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0.
|
||||
*/
|
||||
|
|
@ -61,6 +70,9 @@
|
|||
/*
|
||||
* intr_maskn: MASK_N, one bit per interrupt source.
|
||||
* 1=Enable interrupt source; 0=Disable interrupt source. Default 0.
|
||||
* [ 7] rxsense_fall starting from G12A
|
||||
* [ 6] rxsense_rise starting from G12A
|
||||
* [ 5] err_i2c_timeout starting from G12A
|
||||
* [ 4] hdcp22_rndnum_err
|
||||
* [ 3] nonce_rfrsh_rise
|
||||
* [ 2] hpd_fall_intr
|
||||
|
|
@ -73,6 +85,9 @@
|
|||
* Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
|
||||
* bit, read back the interrupt status.
|
||||
* Bit 31 R IP interrupt status
|
||||
* Bit 7 RW rxsense_fall starting from G12A
|
||||
* Bit 6 RW rxsense_rise starting from G12A
|
||||
* Bit 5 RW err_i2c_timeout starting from G12A
|
||||
* Bit 2 RW hpd_fall
|
||||
* Bit 1 RW hpd_rise
|
||||
* Bit 0 RW IP interrupt
|
||||
|
|
@ -80,6 +95,9 @@
|
|||
#define HDMITX_TOP_INTR_STAT (0x004)
|
||||
|
||||
/*
|
||||
* [7] rxsense_fall starting from G12A
|
||||
* [6] rxsense_rise starting from G12A
|
||||
* [5] err_i2c_timeout starting from G12A
|
||||
* [4] hdcp22_rndnum_err
|
||||
* [3] nonce_rfrsh_rise
|
||||
* [2] hpd_fall
|
||||
|
|
@ -91,6 +109,8 @@
|
|||
#define HDMITX_TOP_INTR_CORE BIT(0)
|
||||
#define HDMITX_TOP_INTR_HPD_RISE BIT(1)
|
||||
#define HDMITX_TOP_INTR_HPD_FALL BIT(2)
|
||||
#define HDMITX_TOP_INTR_RXSENSE_RISE BIT(6)
|
||||
#define HDMITX_TOP_INTR_RXSENSE_FALL BIT(7)
|
||||
|
||||
/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
|
||||
* 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
|
||||
|
|
@ -140,7 +160,9 @@
|
|||
*/
|
||||
#define HDMITX_TOP_REVOCMEM_STAT (0x00D)
|
||||
|
||||
/* Bit 0 R filtered HPD status. */
|
||||
/* Bit 1 R filtered RxSense status
|
||||
* Bit 0 R filtered HPD status.
|
||||
*/
|
||||
#define HDMITX_TOP_STAT0 (0x00E)
|
||||
|
||||
#endif /* __MESON_DW_HDMI_H */
|
||||
|
|
|
|||
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