Merge branch 'clk-ralink' into clk-next
- Proper clk driver for Mediatek MT7621 SoCs * clk-ralink: MAINTAINERS: add MT7621 CLOCK maintainer staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' staging: mt7621-dts: make use of new 'mt7621-clk' clk: ralink: add clock driver for mt7621 SoC dt: bindings: add mt7621-sysc device tree binding documentation dt-bindings: clock: add dt binding header for mt7621 clocks
This commit is contained in:
Stephen Boyd
Коммит
3ba2d41dca
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@ -0,0 +1,68 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MT7621 Clock Device Tree Bindings
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maintainers:
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- Sergio Paracuellos <sergio.paracuellos@gmail.com>
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description: |
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The MT7621 has a PLL controller from where the cpu clock is provided
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as well as derived clocks for the bus and the peripherals. It also
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can gate SoC device clocks.
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Each clock is assigned an identifier and client nodes use this identifier
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to specify the clock which they consume.
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All these identifiers could be found in:
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[1]: <include/dt-bindings/clock/mt7621-clk.h>.
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The clocks are provided inside a system controller node.
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properties:
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compatible:
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items:
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- const: mediatek,mt7621-sysc
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- const: syscon
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reg:
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maxItems: 1
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"#clock-cells":
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description:
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The first cell indicates the clock number, see [1] for available
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clocks.
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const: 1
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ralink,memctl:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle of syscon used to control memory registers
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clock-output-names:
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maxItems: 8
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required:
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- compatible
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- reg
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- '#clock-cells'
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- ralink,memctl
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt7621-clk.h>
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sysc: sysc@0 {
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compatible = "mediatek,mt7621-sysc", "syscon";
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reg = <0x0 0x100>;
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#clock-cells = <1>;
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ralink,memctl = <&memc>;
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clock-output-names = "xtal", "cpu", "bus",
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"50m", "125m", "150m",
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"250m", "270m";
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};
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@ -11295,6 +11295,12 @@ L: linux-wireless@vger.kernel.org
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S: Maintained
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F: drivers/net/wireless/mediatek/mt7601u/
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MEDIATEK MT7621 CLOCK DRIVER
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M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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S: Maintained
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F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
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F: drivers/clk/ralink/clk-mt7621.c
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MEDIATEK MT7621/28/88 I2C DRIVER
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M: Stefan Roese <sr@denx.de>
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L: linux-i2c@vger.kernel.org
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|
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@ -112,8 +112,8 @@ phys_addr_t mips_cpc_default_phys_base(void)
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
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rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
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rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
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rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
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if (!rt_sysc_membase || !rt_memc_membase)
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panic("Failed to remap core resources");
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@ -181,7 +181,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
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if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
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name = "MT7621";
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soc_info->compatible = "mtk,mt7621-soc";
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soc_info->compatible = "mediatek,mt7621-soc";
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} else {
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panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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}
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|
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@ -390,6 +390,7 @@ source "drivers/clk/meson/Kconfig"
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source "drivers/clk/mstar/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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source "drivers/clk/qcom/Kconfig"
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source "drivers/clk/ralink/Kconfig"
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source "drivers/clk/renesas/Kconfig"
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source "drivers/clk/rockchip/Kconfig"
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source "drivers/clk/samsung/Kconfig"
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|
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@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
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obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
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obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
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obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
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obj-y += ralink/
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obj-y += renesas/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
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|
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@ -0,0 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# MediaTek Mt7621 Clock Driver
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#
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config CLK_MT7621
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bool "Clock driver for MediaTek MT7621"
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depends on SOC_MT7621 || COMPILE_TEST
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default SOC_MT7621
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select MFD_SYSCON
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help
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This driver supports MediaTek MT7621 basic clocks.
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
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@ -0,0 +1,495 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Mediatek MT7621 Clock Driver
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* Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/mt7621-clk.h>
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/* Configuration registers */
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#define SYSC_REG_SYSTEM_CONFIG0 0x10
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#define SYSC_REG_SYSTEM_CONFIG1 0x14
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#define SYSC_REG_CLKCFG0 0x2c
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#define SYSC_REG_CLKCFG1 0x30
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#define SYSC_REG_CUR_CLK_STS 0x44
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#define MEMC_REG_CPU_PLL 0x648
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#define XTAL_MODE_SEL_MASK GENMASK(8, 6)
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#define CPU_CLK_SEL_MASK GENMASK(31, 30)
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#define CUR_CPU_FDIV_MASK GENMASK(12, 8)
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#define CUR_CPU_FFRAC_MASK GENMASK(4, 0)
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#define CPU_PLL_PREDIV_MASK GENMASK(13, 12)
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#define CPU_PLL_FBDIV_MASK GENMASK(10, 4)
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struct mt7621_clk_priv {
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struct regmap *sysc;
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struct regmap *memc;
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};
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struct mt7621_clk {
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struct clk_hw hw;
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struct mt7621_clk_priv *priv;
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};
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struct mt7621_fixed_clk {
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u8 idx;
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const char *name;
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const char *parent_name;
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unsigned long rate;
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struct clk_hw *hw;
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};
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struct mt7621_gate {
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u8 idx;
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const char *name;
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const char *parent_name;
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struct mt7621_clk_priv *priv;
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u32 bit_idx;
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struct clk_hw hw;
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};
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#define GATE(_id, _name, _pname, _shift) \
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{ \
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.idx = _id, \
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.name = _name, \
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.parent_name = _pname, \
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.bit_idx = _shift \
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}
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static struct mt7621_gate mt7621_gates[] = {
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GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
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GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
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GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
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GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
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GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
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GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)),
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GATE(MT7621_CLK_GDMA, "gdma", "bus", BIT(14)),
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GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)),
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GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)),
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GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)),
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GATE(MT7621_CLK_SPI, "spi", "bus", BIT(18)),
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GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)),
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GATE(MT7621_CLK_UART2, "uart2", "50m", BIT(20)),
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GATE(MT7621_CLK_UART3, "uart3", "50m", BIT(21)),
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GATE(MT7621_CLK_ETH, "eth", "50m", BIT(23)),
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GATE(MT7621_CLK_PCIE0, "pcie0", "125m", BIT(24)),
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GATE(MT7621_CLK_PCIE1, "pcie1", "125m", BIT(25)),
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GATE(MT7621_CLK_PCIE2, "pcie2", "125m", BIT(26)),
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GATE(MT7621_CLK_CRYPTO, "crypto", "250m", BIT(29)),
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GATE(MT7621_CLK_SHXC, "shxc", "50m", BIT(30))
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};
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static inline struct mt7621_gate *to_mt7621_gate(struct clk_hw *hw)
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{
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return container_of(hw, struct mt7621_gate, hw);
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}
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static int mt7621_gate_enable(struct clk_hw *hw)
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{
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struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
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struct regmap *sysc = clk_gate->priv->sysc;
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return regmap_update_bits(sysc, SYSC_REG_CLKCFG1,
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clk_gate->bit_idx, clk_gate->bit_idx);
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}
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static void mt7621_gate_disable(struct clk_hw *hw)
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{
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struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
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struct regmap *sysc = clk_gate->priv->sysc;
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regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0);
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}
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static int mt7621_gate_is_enabled(struct clk_hw *hw)
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{
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struct mt7621_gate *clk_gate = to_mt7621_gate(hw);
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struct regmap *sysc = clk_gate->priv->sysc;
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u32 val;
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if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))
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return 0;
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return val & BIT(clk_gate->bit_idx);
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}
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static const struct clk_ops mt7621_gate_ops = {
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.enable = mt7621_gate_enable,
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.disable = mt7621_gate_disable,
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.is_enabled = mt7621_gate_is_enabled,
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};
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static int mt7621_gate_ops_init(struct device *dev,
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struct mt7621_gate *sclk)
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{
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struct clk_init_data init = {
|
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/*
|
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* Until now no clock driver existed so
|
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* these SoC drivers are not prepared
|
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* yet for the clock. We don't want kernel to
|
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* disable anything so we add CLK_IS_CRITICAL
|
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* flag here.
|
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*/
|
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.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
|
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.num_parents = 1,
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.parent_names = &sclk->parent_name,
|
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.ops = &mt7621_gate_ops,
|
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.name = sclk->name,
|
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};
|
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|
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sclk->hw.init = &init;
|
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return devm_clk_hw_register(dev, &sclk->hw);
|
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}
|
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|
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static int mt7621_register_gates(struct device *dev,
|
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struct clk_hw_onecell_data *clk_data,
|
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struct mt7621_clk_priv *priv)
|
||||
{
|
||||
struct clk_hw **hws = clk_data->hws;
|
||||
struct mt7621_gate *sclk;
|
||||
int ret, i;
|
||||
|
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for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) {
|
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sclk = &mt7621_gates[i];
|
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sclk->priv = priv;
|
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ret = mt7621_gate_ops_init(dev, sclk);
|
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if (ret) {
|
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dev_err(dev, "Couldn't register clock %s\n", sclk->name);
|
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goto err_clk_unreg;
|
||||
}
|
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|
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hws[sclk->idx] = &sclk->hw;
|
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}
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk_unreg:
|
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while (--i >= 0) {
|
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sclk = &mt7621_gates[i];
|
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clk_hw_unregister(&sclk->hw);
|
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}
|
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return ret;
|
||||
}
|
||||
|
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#define FIXED(_id, _name, _rate) \
|
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{ \
|
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.idx = _id, \
|
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.name = _name, \
|
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.parent_name = "xtal", \
|
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.rate = _rate \
|
||||
}
|
||||
|
||||
static struct mt7621_fixed_clk mt7621_fixed_clks[] = {
|
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FIXED(MT7621_CLK_50M, "50m", 50000000),
|
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FIXED(MT7621_CLK_125M, "125m", 125000000),
|
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FIXED(MT7621_CLK_150M, "150m", 150000000),
|
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FIXED(MT7621_CLK_250M, "250m", 250000000),
|
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FIXED(MT7621_CLK_270M, "270m", 270000000),
|
||||
};
|
||||
|
||||
static int mt7621_register_fixed_clocks(struct device *dev,
|
||||
struct clk_hw_onecell_data *clk_data)
|
||||
{
|
||||
struct clk_hw **hws = clk_data->hws;
|
||||
struct mt7621_fixed_clk *sclk;
|
||||
int ret, i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) {
|
||||
sclk = &mt7621_fixed_clks[i];
|
||||
sclk->hw = clk_hw_register_fixed_rate(dev, sclk->name,
|
||||
sclk->parent_name, 0,
|
||||
sclk->rate);
|
||||
if (IS_ERR(sclk->hw)) {
|
||||
dev_err(dev, "Couldn't register clock %s\n", sclk->name);
|
||||
ret = PTR_ERR(sclk->hw);
|
||||
goto err_clk_unreg;
|
||||
}
|
||||
|
||||
hws[sclk->idx] = sclk->hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk_unreg:
|
||||
while (--i >= 0) {
|
||||
sclk = &mt7621_fixed_clks[i];
|
||||
clk_hw_unregister_fixed_rate(sclk->hw);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline struct mt7621_clk *to_mt7621_clk(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct mt7621_clk, hw);
|
||||
}
|
||||
|
||||
static unsigned long mt7621_xtal_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct mt7621_clk *clk = to_mt7621_clk(hw);
|
||||
struct regmap *sysc = clk->priv->sysc;
|
||||
u32 val;
|
||||
|
||||
regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG0, &val);
|
||||
val = FIELD_GET(XTAL_MODE_SEL_MASK, val);
|
||||
|
||||
if (val <= 2)
|
||||
return 20000000;
|
||||
if (val <= 5)
|
||||
return 40000000;
|
||||
|
||||
return 25000000;
|
||||
}
|
||||
|
||||
static unsigned long mt7621_cpu_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long xtal_clk)
|
||||
{
|
||||
static const u32 prediv_tbl[] = { 0, 1, 2, 2 };
|
||||
struct mt7621_clk *clk = to_mt7621_clk(hw);
|
||||
struct regmap *sysc = clk->priv->sysc;
|
||||
struct regmap *memc = clk->priv->memc;
|
||||
u32 clkcfg, clk_sel, curclk, ffiv, ffrac;
|
||||
u32 pll, prediv, fbdiv;
|
||||
unsigned long cpu_clk;
|
||||
|
||||
regmap_read(sysc, SYSC_REG_CLKCFG0, &clkcfg);
|
||||
clk_sel = FIELD_GET(CPU_CLK_SEL_MASK, clkcfg);
|
||||
|
||||
regmap_read(sysc, SYSC_REG_CUR_CLK_STS, &curclk);
|
||||
ffiv = FIELD_GET(CUR_CPU_FDIV_MASK, curclk);
|
||||
ffrac = FIELD_GET(CUR_CPU_FFRAC_MASK, curclk);
|
||||
|
||||
switch (clk_sel) {
|
||||
case 0:
|
||||
cpu_clk = 500000000;
|
||||
break;
|
||||
case 1:
|
||||
regmap_read(memc, MEMC_REG_CPU_PLL, &pll);
|
||||
fbdiv = FIELD_GET(CPU_PLL_FBDIV_MASK, pll);
|
||||
prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll);
|
||||
cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
|
||||
break;
|
||||
default:
|
||||
cpu_clk = xtal_clk;
|
||||
}
|
||||
|
||||
return cpu_clk / ffiv * ffrac;
|
||||
}
|
||||
|
||||
static unsigned long mt7621_bus_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
return parent_rate / 4;
|
||||
}
|
||||
|
||||
#define CLK_BASE(_name, _parent, _recalc) { \
|
||||
.init = &(struct clk_init_data) { \
|
||||
.name = _name, \
|
||||
.ops = &(const struct clk_ops) { \
|
||||
.recalc_rate = _recalc, \
|
||||
}, \
|
||||
.parent_data = &(const struct clk_parent_data) { \
|
||||
.name = _parent, \
|
||||
.fw_name = _parent \
|
||||
}, \
|
||||
.num_parents = _parent ? 1 : 0 \
|
||||
}, \
|
||||
}
|
||||
|
||||
static struct mt7621_clk mt7621_clks_base[] = {
|
||||
{ CLK_BASE("xtal", NULL, mt7621_xtal_recalc_rate) },
|
||||
{ CLK_BASE("cpu", "xtal", mt7621_cpu_recalc_rate) },
|
||||
{ CLK_BASE("bus", "cpu", mt7621_bus_recalc_rate) },
|
||||
};
|
||||
|
||||
static struct clk_hw *mt7621_clk_early[MT7621_CLK_MAX];
|
||||
|
||||
static int mt7621_register_early_clocks(struct device_node *np,
|
||||
struct clk_hw_onecell_data *clk_data,
|
||||
struct mt7621_clk_priv *priv)
|
||||
{
|
||||
struct clk_hw **hws = clk_data->hws;
|
||||
struct mt7621_clk *sclk;
|
||||
int ret, i, j;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) {
|
||||
sclk = &mt7621_clks_base[i];
|
||||
sclk->priv = priv;
|
||||
ret = of_clk_hw_register(np, &sclk->hw);
|
||||
if (ret) {
|
||||
pr_err("Couldn't register top clock %i\n", i);
|
||||
goto err_clk_unreg;
|
||||
}
|
||||
|
||||
hws[i] = &sclk->hw;
|
||||
mt7621_clk_early[i] = &sclk->hw;
|
||||
}
|
||||
|
||||
for (j = i; j < MT7621_CLK_MAX; j++)
|
||||
mt7621_clk_early[j] = ERR_PTR(-EPROBE_DEFER);
|
||||
|
||||
return 0;
|
||||
|
||||
err_clk_unreg:
|
||||
while (--i >= 0) {
|
||||
sclk = &mt7621_clks_base[i];
|
||||
clk_hw_unregister(&sclk->hw);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __init mt7621_clk_init(struct device_node *node)
|
||||
{
|
||||
struct mt7621_clk_priv *priv;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int ret, i, count;
|
||||
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return;
|
||||
|
||||
priv->sysc = syscon_node_to_regmap(node);
|
||||
if (IS_ERR(priv->sysc)) {
|
||||
pr_err("Could not get sysc syscon regmap\n");
|
||||
goto free_clk_priv;
|
||||
}
|
||||
|
||||
priv->memc = syscon_regmap_lookup_by_phandle(node, "ralink,memctl");
|
||||
if (IS_ERR(priv->memc)) {
|
||||
pr_err("Could not get memc syscon regmap\n");
|
||||
goto free_clk_priv;
|
||||
}
|
||||
|
||||
count = ARRAY_SIZE(mt7621_clks_base) +
|
||||
ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
|
||||
clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
goto free_clk_priv;
|
||||
|
||||
ret = mt7621_register_early_clocks(node, clk_data, priv);
|
||||
if (ret) {
|
||||
pr_err("Couldn't register top clocks\n");
|
||||
goto free_clk_data;
|
||||
}
|
||||
|
||||
clk_data->num = count;
|
||||
|
||||
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (ret) {
|
||||
pr_err("Couldn't add clk hw provider\n");
|
||||
goto unreg_clk_top;
|
||||
}
|
||||
|
||||
return;
|
||||
|
||||
unreg_clk_top:
|
||||
for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++) {
|
||||
struct mt7621_clk *sclk = &mt7621_clks_base[i];
|
||||
|
||||
clk_hw_unregister(&sclk->hw);
|
||||
}
|
||||
|
||||
free_clk_data:
|
||||
kfree(clk_data);
|
||||
|
||||
free_clk_priv:
|
||||
kfree(priv);
|
||||
}
|
||||
CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
|
||||
|
||||
static int mt7621_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mt7621_clk_priv *priv;
|
||||
int ret, i, count;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->sysc = syscon_node_to_regmap(np);
|
||||
if (IS_ERR(priv->sysc)) {
|
||||
ret = PTR_ERR(priv->sysc);
|
||||
dev_err(dev, "Could not get sysc syscon regmap\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
priv->memc = syscon_regmap_lookup_by_phandle(np, "ralink,memctl");
|
||||
if (IS_ERR(priv->memc)) {
|
||||
ret = PTR_ERR(priv->memc);
|
||||
dev_err(dev, "Could not get memc syscon regmap\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
count = ARRAY_SIZE(mt7621_clks_base) +
|
||||
ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
|
||||
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
|
||||
GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mt7621_clks_base); i++)
|
||||
clk_data->hws[i] = mt7621_clk_early[i];
|
||||
|
||||
ret = mt7621_register_fixed_clocks(dev, clk_data);
|
||||
if (ret) {
|
||||
dev_err(dev, "Couldn't register fixed clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mt7621_register_gates(dev, clk_data, priv);
|
||||
if (ret) {
|
||||
dev_err(dev, "Couldn't register fixed clock gates\n");
|
||||
goto unreg_clk_fixed;
|
||||
}
|
||||
|
||||
clk_data->num = count;
|
||||
|
||||
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
|
||||
if (ret) {
|
||||
dev_err(dev, "Couldn't add clk hw provider\n");
|
||||
goto unreg_clk_gates;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
unreg_clk_gates:
|
||||
for (i = 0; i < ARRAY_SIZE(mt7621_gates); i++) {
|
||||
struct mt7621_gate *sclk = &mt7621_gates[i];
|
||||
|
||||
clk_hw_unregister(&sclk->hw);
|
||||
}
|
||||
|
||||
unreg_clk_fixed:
|
||||
for (i = 0; i < ARRAY_SIZE(mt7621_fixed_clks); i++) {
|
||||
struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i];
|
||||
|
||||
clk_hw_unregister_fixed_rate(sclk->hw);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id mt7621_clk_of_match[] = {
|
||||
{ .compatible = "mediatek,mt7621-sysc" },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver mt7621_clk_driver = {
|
||||
.probe = mt7621_clk_probe,
|
||||
.driver = {
|
||||
.name = "mt7621-clk",
|
||||
.of_match_table = mt7621_clk_of_match,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(mt7621_clk_driver);
|
||||
|
|
@ -100,17 +100,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&sysclock {
|
||||
compatible = "fixed-clock";
|
||||
/* This is normally 1/4 of cpuclock */
|
||||
clock-frequency = <225000000>;
|
||||
};
|
||||
|
||||
&cpuclock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <900000000>;
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/mt7621-clk.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
|
|
@ -27,27 +28,6 @@
|
|||
serial0 = &uartlite;
|
||||
};
|
||||
|
||||
cpuclock: cpuclock@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
||||
/* FIXME: there should be way to detect this */
|
||||
clock-frequency = <880000000>;
|
||||
};
|
||||
|
||||
sysclock: sysclock@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
|
||||
/* This is normally 1/4 of cpuclock */
|
||||
clock-frequency = <220000000>;
|
||||
};
|
||||
|
||||
mmc_clock: mmc_clock@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
mmc_fixed_3v3: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
|
@ -76,12 +56,17 @@
|
|||
#size-cells = <1>;
|
||||
|
||||
sysc: sysc@0 {
|
||||
compatible = "mtk,mt7621-sysc";
|
||||
compatible = "mediatek,mt7621-sysc", "syscon";
|
||||
reg = <0x0 0x100>;
|
||||
#clock-cells = <1>;
|
||||
ralink,memctl = <&memc>;
|
||||
clock-output-names = "xtal", "cpu", "bus",
|
||||
"50m", "125m", "150m",
|
||||
"250m", "270m";
|
||||
};
|
||||
|
||||
wdt: wdt@100 {
|
||||
compatible = "mtk,mt7621-wdt";
|
||||
compatible = "mediatek,mt7621-wdt";
|
||||
reg = <0x100 0x100>;
|
||||
};
|
||||
|
||||
|
|
@ -101,8 +86,8 @@
|
|||
compatible = "mediatek,mt7621-i2c";
|
||||
reg = <0x900 0x100>;
|
||||
|
||||
clocks = <&sysclock>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_I2C>;
|
||||
clock-names = "i2c";
|
||||
resets = <&rstctrl 16>;
|
||||
reset-names = "i2c";
|
||||
|
||||
|
|
@ -119,8 +104,8 @@
|
|||
compatible = "mediatek,mt7621-i2s";
|
||||
reg = <0xa00 0x100>;
|
||||
|
||||
clocks = <&sysclock>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_I2S>;
|
||||
clock-names = "i2s";
|
||||
resets = <&rstctrl 17>;
|
||||
reset-names = "i2s";
|
||||
|
||||
|
|
@ -138,17 +123,17 @@
|
|||
};
|
||||
|
||||
memc: memc@5000 {
|
||||
compatible = "mtk,mt7621-memc";
|
||||
compatible = "mediatek,mt7621-memc", "syscon";
|
||||
reg = <0x5000 0x1000>;
|
||||
};
|
||||
|
||||
cpc: cpc@1fbf0000 {
|
||||
compatible = "mtk,mt7621-cpc";
|
||||
compatible = "mediatek,mt7621-cpc";
|
||||
reg = <0x1fbf0000 0x8000>;
|
||||
};
|
||||
|
||||
mc: mc@1fbf8000 {
|
||||
compatible = "mtk,mt7621-mc";
|
||||
compatible = "mediatek,mt7621-mc";
|
||||
reg = <0x1fbf8000 0x8000>;
|
||||
};
|
||||
|
||||
|
|
@ -156,8 +141,8 @@
|
|||
compatible = "ns16550a";
|
||||
reg = <0xc00 0x100>;
|
||||
|
||||
clocks = <&sysclock>;
|
||||
clock-frequency = <50000000>;
|
||||
clocks = <&sysc MT7621_CLK_UART1>;
|
||||
clock-names = "uart1";
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -173,7 +158,8 @@
|
|||
compatible = "ralink,mt7621-spi";
|
||||
reg = <0xb00 0x100>;
|
||||
|
||||
clocks = <&sysclock>;
|
||||
clocks = <&sysc MT7621_CLK_SPI>;
|
||||
clock-names = "spi";
|
||||
|
||||
resets = <&rstctrl 18>;
|
||||
reset-names = "spi";
|
||||
|
|
@ -189,6 +175,8 @@
|
|||
compatible = "ralink,rt3883-gdma";
|
||||
reg = <0x2800 0x800>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_GDMA>;
|
||||
clock-names = "gdma";
|
||||
resets = <&rstctrl 14>;
|
||||
reset-names = "dma";
|
||||
|
||||
|
|
@ -206,6 +194,8 @@
|
|||
compatible = "mediatek,mt7621-hsdma";
|
||||
reg = <0x7000 0x1000>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_HSDMA>;
|
||||
clock-names = "hsdma";
|
||||
resets = <&rstctrl 5>;
|
||||
reset-names = "hsdma";
|
||||
|
||||
|
|
@ -311,11 +301,6 @@
|
|||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clkctrl: clkctrl {
|
||||
compatible = "ralink,rt2880-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sdhci: sdhci@1E130000 {
|
||||
status = "disabled";
|
||||
|
||||
|
|
@ -334,7 +319,8 @@
|
|||
pinctrl-0 = <&sdhci_pins>;
|
||||
pinctrl-1 = <&sdhci_pins>;
|
||||
|
||||
clocks = <&mmc_clock &mmc_clock>;
|
||||
clocks = <&sysc MT7621_CLK_SHXC>,
|
||||
<&sysc MT7621_CLK_50M>;
|
||||
clock-names = "source", "hclk";
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -349,7 +335,7 @@
|
|||
0x1e1d0700 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
|
||||
clocks = <&sysclock>;
|
||||
clocks = <&sysc MT7621_CLK_XTAL>;
|
||||
clock-names = "sys_ck";
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -368,19 +354,22 @@
|
|||
timer {
|
||||
compatible = "mti,gic-timer";
|
||||
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
|
||||
clocks = <&cpuclock>;
|
||||
clocks = <&sysc MT7621_CLK_CPU>;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@1e003000 {
|
||||
status = "disabled";
|
||||
|
||||
compatible = "mtk,mt7621-nand";
|
||||
compatible = "mediatek,mt7621-nand";
|
||||
bank-width = <2>;
|
||||
reg = <0x1e003000 0x800
|
||||
0x1e003800 0x800>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clocks = <&sysc MT7621_CLK_NAND>;
|
||||
clock-names = "nand";
|
||||
};
|
||||
|
||||
ethsys: syscon@1e000000 {
|
||||
|
|
@ -394,8 +383,9 @@
|
|||
compatible = "mediatek,mt7621-eth";
|
||||
reg = <0x1e100000 0x10000>;
|
||||
|
||||
clocks = <&sysclock>;
|
||||
clock-names = "ethif";
|
||||
clocks = <&sysc MT7621_CLK_FE>,
|
||||
<&sysc MT7621_CLK_ETH>;
|
||||
clock-names = "fe", "ethif";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -521,7 +511,9 @@
|
|||
|
||||
resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
|
||||
reset-names = "pcie0", "pcie1", "pcie2";
|
||||
clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
|
||||
clocks = <&sysc MT7621_CLK_PCIE0>,
|
||||
<&sysc MT7621_CLK_PCIE1>,
|
||||
<&sysc MT7621_CLK_PCIE2>;
|
||||
clock-names = "pcie0", "pcie1", "pcie2";
|
||||
phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
|
||||
phy-names = "pcie-phy0", "pcie-phy2";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT7621_H
|
||||
#define _DT_BINDINGS_CLK_MT7621_H
|
||||
|
||||
#define MT7621_CLK_XTAL 0
|
||||
#define MT7621_CLK_CPU 1
|
||||
#define MT7621_CLK_BUS 2
|
||||
#define MT7621_CLK_50M 3
|
||||
#define MT7621_CLK_125M 4
|
||||
#define MT7621_CLK_150M 5
|
||||
#define MT7621_CLK_250M 6
|
||||
#define MT7621_CLK_270M 7
|
||||
|
||||
#define MT7621_CLK_HSDMA 8
|
||||
#define MT7621_CLK_FE 9
|
||||
#define MT7621_CLK_SP_DIVTX 10
|
||||
#define MT7621_CLK_TIMER 11
|
||||
#define MT7621_CLK_PCM 12
|
||||
#define MT7621_CLK_PIO 13
|
||||
#define MT7621_CLK_GDMA 14
|
||||
#define MT7621_CLK_NAND 15
|
||||
#define MT7621_CLK_I2C 16
|
||||
#define MT7621_CLK_I2S 17
|
||||
#define MT7621_CLK_SPI 18
|
||||
#define MT7621_CLK_UART1 19
|
||||
#define MT7621_CLK_UART2 20
|
||||
#define MT7621_CLK_UART3 21
|
||||
#define MT7621_CLK_ETH 22
|
||||
#define MT7621_CLK_PCIE0 23
|
||||
#define MT7621_CLK_PCIE1 24
|
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#define MT7621_CLK_PCIE2 25
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#define MT7621_CLK_CRYPTO 26
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#define MT7621_CLK_SHXC 27
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#define MT7621_CLK_MAX 28
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#endif /* _DT_BINDINGS_CLK_MT7621_H */
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