bnxt_en: Initialize context memory to the value specified by firmware.
Some chips that need host context memory as a backing store requires the memory to be initialized to a non-zero value. Query the value from firmware and initialize the context memory accordingly. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com>
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f9b69d7f62
Коммит
3be8136ce1
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@ -2688,6 +2688,9 @@ static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
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if (!rmem->pg_arr[i])
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return -ENOMEM;
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if (rmem->init_val)
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memset(rmem->pg_arr[i], rmem->init_val,
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rmem->page_size);
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if (rmem->nr_pages > 1 || rmem->depth > 0) {
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if (i == rmem->nr_pages - 2 &&
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(rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
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@ -6487,6 +6490,7 @@ static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
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le16_to_cpu(resp->mrav_num_entries_units);
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ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
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ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
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ctx->ctx_kind_initializer = resp->ctx_kind_initializer;
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} else {
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rc = 0;
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}
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@ -6641,7 +6645,7 @@ static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
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static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
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struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
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u8 depth)
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u8 depth, bool use_init_val)
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{
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struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
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int rc;
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@ -6679,6 +6683,8 @@ static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
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rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
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rmem->depth = 1;
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rmem->nr_pages = MAX_CTX_PAGES;
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if (use_init_val)
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rmem->init_val = bp->ctx->ctx_kind_initializer;
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if (i == (nr_tbls - 1)) {
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int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
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@ -6693,6 +6699,8 @@ static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
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rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
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if (rmem->nr_pages > 1 || depth)
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rmem->depth = 1;
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if (use_init_val)
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rmem->init_val = bp->ctx->ctx_kind_initializer;
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rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
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}
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return rc;
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@ -6783,21 +6791,21 @@ static int bnxt_alloc_ctx_mem(struct bnxt *bp)
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ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
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extra_qps;
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mem_size = ctx->qp_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true);
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if (rc)
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return rc;
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ctx_pg = &ctx->srq_mem;
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ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
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mem_size = ctx->srq_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true);
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if (rc)
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return rc;
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ctx_pg = &ctx->cq_mem;
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ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
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mem_size = ctx->cq_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, true);
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if (rc)
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return rc;
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@ -6805,14 +6813,14 @@ static int bnxt_alloc_ctx_mem(struct bnxt *bp)
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ctx_pg->entries = ctx->vnic_max_vnic_entries +
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ctx->vnic_max_ring_table_entries;
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mem_size = ctx->vnic_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true);
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if (rc)
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return rc;
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ctx_pg = &ctx->stat_mem;
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ctx_pg->entries = ctx->stat_max_entries;
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mem_size = ctx->stat_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, true);
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if (rc)
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return rc;
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@ -6828,7 +6836,7 @@ static int bnxt_alloc_ctx_mem(struct bnxt *bp)
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num_ah = 1024 * 128;
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ctx_pg->entries = num_mr + num_ah;
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mem_size = ctx->mrav_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, true);
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if (rc)
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return rc;
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ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
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@ -6840,7 +6848,7 @@ static int bnxt_alloc_ctx_mem(struct bnxt *bp)
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ctx_pg = &ctx->tim_mem;
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ctx_pg->entries = ctx->qp_mem.entries;
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mem_size = ctx->tim_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false);
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if (rc)
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return rc;
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ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
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@ -6854,7 +6862,7 @@ skip_rdma:
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ctx_pg = ctx->tqm_mem[i];
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ctx_pg->entries = entries;
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mem_size = ctx->tqm_entry_size * entries;
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
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rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, false);
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if (rc)
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return rc;
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ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
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@ -721,6 +721,7 @@ struct bnxt_ring_mem_info {
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#define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
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u16 depth;
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u8 init_val;
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void **pg_arr;
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dma_addr_t *dma_arr;
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@ -1352,6 +1353,7 @@ struct bnxt_ctx_mem_info {
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u32 tim_max_entries;
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u16 mrav_num_entries_units;
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u8 tqm_entries_multiple;
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u8 ctx_kind_initializer;
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u32 flags;
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#define BNXT_CTX_FLAG_INITED 0x01
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